WM8772 w 24-bit, 192kHz 6-Channel Codec with Volume Control DESCRIPTION FEATURES • The WM8772 is a multi-channel audio codec ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Audio Performance − • • A stereo 24-bit multi-bit sigma delta ADC is used. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHz to 96kHz are supported. The 32-lead version allows separate ADC and DAC samples rates. • ADC and DAC can run at different sample rates (32 pin TQFP version only) 3-Wire SPI Serial or Hardware Control Interface Programmable Audio Data Interface Modes • • Three stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. 103dB SNR (‘A’ weighted @ 48kHz) DAC − 100dB SNR (‘A’ weighted @ 48kHz) ADC (TQFP) DAC Sampling Frequency: 8kHz – 192kHz ADC Sampling Frequency: 32kHz – 96kHz − − 16/20/24/32 bit Word Lengths Three Independent stereo DAC outputs with independent digital volume controls Master or Slave Audio Data Interface • The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. • The device is controlled via a 3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 28 lead SSOP or 32 lead TQFP. I2S, Left, Right Justified or DSP • 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation • 28 lead SSOP or 32 lead TQFP Package • • • DVD Players Surround Sound AV Processors and Hi-Fi systems Automotive Audio DIN2 DIN3 APPLICATIONS AGND AVDD MCLK DIN1 LRC BCLK DOUT REFADC VREFP VMID VREFN BLOCK DIAGRAM - 28 LEAD SSOP VREFN VREFP LOW PASS FILTER VOUT1R STEREO DAC LOW PASS FILTER VOUT2R STEREO DAC LOW PASS FILTER VREFN AINL AINR AUDIO INTERFACE & STEREO ADC DIGITAL FILTERS VOUT2L VOUT3L VOUT3R W WM8772EDS MD/DM MC/IWL ML/I2S MODE MUTE DVDD DGND CONTROL INTERFACE VOUT1L STEREO DAC WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, October 2005, Rev 4.2 Copyright 2005 Wolfson Microelectronics plc WM8772 Production Data AGND AVDD ADCMCLK* DOUT ADCLRC* ADCBCLK* DACBCLK* DACLRC* DIN1 DIN2 DIN3 DACMCLK* ADCVREFN REFADC DACVREFP VMID DACVREFN BLOCK DIAGRAM – 32 LEAD TQFP VREFN VREFP AINL AINR AUDIO INTERFACE & STEREO ADC STEREO DAC LOW PASS FILTER STEREO DAC LOW PASS FILTER STEREO DAC LOW PASS FILTER DIGITAL FILTERS VOUT2L VOUT2R VOUT3L VOUT3R W WM8772EFT MD/DM MC/IWL ML/I2S MODE MUTE DVDD DGND CONTROL INTERFACE VOUT1L VOUT1R * extra pins on TQFP allow separate clocking of ADC and DAC w PD Rev 4.2 October 2005 2 WM8772 Production Data TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM - 28 LEAD SSOP ....................................................................1 BLOCK DIAGRAM – 32 LEAD TQFP ....................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION - 28 LEAD SSOP .............................................................5 ORDERING INFORMATION ..................................................................................5 PIN CONFIGURATION 32 LEAD TQFP...............................................................6 ORDERING INFORMATION ..................................................................................6 PIN DESCRIPTION – 28 LEAD SSOP...................................................................7 PIN DESCRIPTION – 32 LEAD TQFP ...................................................................8 ABSOLUTE MAXIMUM RATINGS.........................................................................9 RECOMMENDED OPERATING CONDITIONS ...................................................10 ELECTRICAL CHARACTERISTICS ....................................................................10 TERMINOLOGY .......................................................................................................... 12 DIGITAL FILTER CHARACTERISTICS ...............................................................13 DAC FILTER RESPONSES......................................................................................... 13 ADC FILTER RESPONSES......................................................................................... 14 ADC HIGH PASS FILTER ........................................................................................... 14 DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 14 WM8772EDS – 28 LEAD SSOP ..........................................................................16 MASTER CLOCK TIMING....................................................................................16 DIGITAL AUDIO INTERFACE – MASTER MODE ....................................................... 16 MPU INTERFACE TIMING .......................................................................................... 19 DEVICE DESCRIPTION.......................................................................................20 INTRODUCTION ......................................................................................................... 20 AUDIO DATA SAMPLING RATES............................................................................... 20 HARDWARE CONTROL MODES ............................................................................... 21 DIGITAL AUDIO INTERFACE ..................................................................................... 23 POWERDOWN MODES ............................................................................................. 28 ZERO DETECT ........................................................................................................... 28 SOFTWARE CONTROL INTERFACE OPERATION................................................... 29 REGISTER MAP - 28 PIN SSOP ........................................................................30 CONTROL INTERFACE REGISTERS ........................................................................ 31 APPLICATIONS INFORMATION .........................................................................39 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 39 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 40 PACKAGE DIMENSIONS ....................................................................................42 WM8722EFT - 32 LEAD TQFP ............................................................................43 MASTER CLOCK TIMING....................................................................................43 DIGITAL AUDIO INTERFACE – MASTER MODE ....................................................... 43 MPU INTERFACE TIMING .......................................................................................... 46 w PD Rev 4.2 October 2005 3 WM8772 Production Data DEVICE DESCRIPTION.......................................................................................48 INTRODUCTION ......................................................................................................... 48 AUDIO DATA SAMPLING RATES............................................................................... 48 HARDWARE CONTROL MODES ............................................................................... 49 DIGITAL AUDIO INTERFACE ..................................................................................... 51 POWERDOWN MODES ............................................................................................. 57 ZERO DETECT ........................................................................................................... 57 SOFTWARE CONTROL INTERFACE OPERATION................................................... 57 REGISTER MAP – 32 PIN TQFP .........................................................................58 CONTROL INTERFACE REGISTERS ........................................................................ 59 APPLICATIONS INFORMATION .........................................................................69 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 69 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 70 PACKAGE DIMENSIONS ....................................................................................72 IMPORTANT NOTICE ..........................................................................................73 ADDRESS: .................................................................................................................. 73 w PD Rev 4.2 October 2005 4 WM8772 Production Data PIN CONFIGURATION - 28 LEAD SSOP MODE 1 28 AVDD MCLK 2 27 AGND 3 26 VOUT3R VOUT3L BCLK LRC 4 25 DVDD 5 24 VOUT2R DGND 6 23 VOUT2L DIN1 7 22 VOUT1R DIN2 8 21 VOUT1L DIN3 9 20 AINL AINR 10 19 ML/I2S 11 18 VMID MC/IWL 12 17 VREFP MD/DM 13 16 VREFN MUTE 14 15 REFADC DOUT ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE WM8772SEDS/V -25 to +85oC WM8772SEDS/RV o -25 to +85 C MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 28-lead SSOP (Pb free) MSL3 260oC 28-lead SSOP (Pb free, tape and reel) MSL3 260oC Note: Reel quantity = 2,000 w PD Rev 4.2 October 2005 5 WM8772 Production Data VMID 20 19 AINR VOUT1L 21 AINL VOUT2L 24 23 22 VOUT2R VOUT1R VOUT3L PIN CONFIGURATION 32 LEAD TQFP 18 17 DACBCLK ADCLRC 1 2 3 4 5 6 7 8 DOUT 9 ADCBCLK DIN3 10 ML/I2S DACMLCK DIN1 12 11 31 32 MC/IWL ADCMCLK DIN2 15 14 13 29 30 MD/DM AVDD MODE DGND 16 26 27 28 DACVREFN DVDD 25 DACVREFP AGND DACLRC VOUT3R ADCVREFN REFADC MUTE ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8772SEFT/V -25 to +85oC WM8772SEFT/RV -25 to +85 C o MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 32-lead TQFP (Pb free) MSL2 260oC 32-lead TQFP (Pb free, tape and reel) MSL2 260 C PACKAGE o Note: Reel quantity = 2,200 w PD Rev 4.2 October 2005 6 WM8772 Production Data PIN DESCRIPTION – 28 LEAD SSOP PIN NAME TYPE 1 MODE Digital input Control format selection 0 = Software control 1 = Hardware control DESCRIPTION 2 MCLK Digital input Master clock; 256, 384, 512 or 768fs (fs = word clock frequency) (combined ADCMCLK and DACMCLK) 3 BCLK Digital input/output Audio interface bit clock (combined ADCBCLK and DACBCLK) 4 LRC Digital input/output Audio left/right word clock (combined ADCLRC and DACLRC) 5 DVDD Supply Digital positive supply 6 DGND Supply Digital negative supply 7 DIN1 Digital input DAC channel 1 data input 8 DIN2 Digital input DAC channel 2 data input 9 DIN3 Digital input DAC channel 3 data input 10 DOUT Digital output 11 ML/I2S Digital input Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format 12 MC/IWL Digital input Software Mode: Serial control interface clock Hardware Mode: Audio data input word length 13 MD/DM Digital input Software Mode: Serial interface data Hardware Mode: De-emphasis selection 14 MUTE Digital input/output DAC Zero Flag output or DAC mute input 15 REFADC Analogue output 16 VREFN Supply ADC and DAC negative supply 17 VREFP Supply DAC positive reference supply 18 VMID Analogue output 19 AINR Analogue input ADC right input 20 AINL Analogue input ADC left input 21 VOUT1L Analogue output DAC channel 1 left output 22 VOUT1R Analogue output DAC channel 1 right output 23 VOUT2L Analogue output DAC channel 2 left output 24 VOUT2R Analogue output DAC channel 2 right output 25 VOUT3L Analogue output DAC channel 3 left output 26 VOUT3R Analogue output DAC channel 3 right output 27 AGND Supply Analogue negative supply and substrate connection 28 AVDD Supply Analogue positive supply ADC data output ADC reference buffer decoupling pin; 10uF external decoupling Midrail divider decoupling pin; 10uF external decoupling Note: Digital input pins have Schmitt trigger input buffers. w PD Rev 4.2 October 2005 7 WM8772 Production Data PIN DESCRIPTION – 32 LEAD TQFP PIN NAME TYPE 1 ADCLRC Digital Input/Output ADC left/right word clock DESCRIPTION 2 DACLRC Digital Input/Output DAC left/right word clock 3 DVDD Supply Digital positive supply 4 DGND Supply Digital negative supply 5 DIN1 Digital Input DAC channel 1 data input 6 DIN2 Digital Input DAC channel 2 data input 7 DIN3 Digital Input DAC channel 3 data input 8 DOUT Digital Output 9 ML/I2S Digital Input Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format 10 MC/IWL Digital Input Software Mode: Serial control interface clock Hardware Mode: Audio data input word length 11 MD/DM Digital Input Software Mode: Serial interface data Hardware Mode: De-emphasis selection 12 MUTE Digital Input/Output DAC Zero Flag output or DAC Mute Input 13 REFADC Analogue Output 14 ADCVREFN Supply ADC negative supply 15 DACVREFN Supply DAC negative supply 16 DACVREFP Supply 17 VMID Analogue Output 18 AINR Analogue Input ADC right input 19 AINL Analogue Input ADC left input 20 VOUT1L Analogue Output DAC channel 1 left output 21 VOUT1R Analogue Output DAC channel 1 right output 22 VOUT2L Analogue Output DAC channel 2 left output 23 VOUT2R Analogue Output DAC channel 2 right output 24 VOUT3L Analogue Output DAC channel 3 left output 25 VOUT3R Analogue Output DAC channel 3 right output 26 AGND Supply Analogue negative supply and substrate connection 27 AVDD Supply Analogue positive supply 28 MODE Digital Input Control format selection 0 = Software control 1 = Hardware control 29 ADCMCLK Digital Input Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) 30 DACMCLK Digital Input Master DAC clock; 256, 384, 512 or 768fs (fs = word clock frequency) 31 ADCBCLK Digital Input/Output ADC audio interface bit clock 32 DACBCLK Digital Input/Output DAC audio interface bit clock ADC data output ADC reference buffer decoupling pin; 10uF external decoupling DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling Note: Digital input pins have Schmitt trigger input buffers. w PD Rev 4.2 October 2005 8 WM8772 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage MIN MAX -0.3V +5V -0.3V +7V Voltage range digital inputs 1 DGND -0.3V DVDD +0.3V Voltage range analogue inputs 1 AGND -0.3V AVDD +0.3V Master Clock Frequency 37MHz Operating temperature range, TA -25°C +85°C Storage temperature after soldering -65°C +150°C Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Refer to Ordering Information, p5 and p6 +183°C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. w PD Rev 4.2 October 2005 9 WM8772 Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Digital supply range Analogue supply range Ground MAX UNIT DVDD TEST CONDITIONS MIN 2.7 TYP 3.6 V AVDD, VREFP 2.7 5.5 V +0.3 V AGND, VREFN, DGND 0 Difference DGND to AGND -0.3 0 V Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. ELECTRICAL CHARACTERISTICS Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, 32-pin TQFP version unless otherwise stated. ADC/DAC in Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC Performance (Load = 10kΩ, 50pF) 0dBFs Full scale output voltage 1.0 x VREFP/5 Vrms 103 dB SNR (Note 1,2,4) A-weighted, @ fs = 48kHz SNR (Note 1,2,4) A-weighted @ fs = 96kHz 102 dB SNR (Note 1,2,4) A-weighted @ fs = 192kHz 101 dB SNR (Note 1,2,4) A-weighted @ fs = 48kHz, AVDD = 3.3V 99 dB SNR (Note 1,2,4) A-weighted @ fs = 96kHz, AVDD = 3.3V 99 dB 103 dB Dynamic Range (Note 2,4) DNR Total Harmonic Distortion (THD) Mute Attenuation A-weighted, -60dB full scale input w PSRR 90 1kHz, 0dB.Fs -90 1kHz Input, 0dB gain 100 dB 100 dB 1kHz 100mVp-p 50 dB 20Hz to 20kHz 100mVp-p 45 dB DAC channel separation Power Supply Rejection Ratio 95 -80 dB PD Rev 4.2 October 2005 10 WM8772 Production Data Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, 32-pin TQFP version unless otherwise stated. ADC/DAC in Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADC Performance Input Signal Level (0dB) 2.0 x REFADC/5 Vrms Input resistance 20 kΩ Input capacitance 10 pF 100 dB SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 48kHz SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 96kHz 64 x OSR 100 dB SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 48kHz, AVDD = 3.3V 93 dB SNR (Note 1,2,4) A-weighted, 0dB gain @ fs = 96kHz, AVDD = 3.3V 64 x OSR 93 dB Total Harmonic Distortion (THD) ADC Channel Separation Mute Attenuation Power Supply Rejection Ratio PSRR 80 kHz, 0dBFs -80 dB 1kHz, -1dBFs -82 dB dB 1kHz Input 90 1kHz Input, 0dB gain 90 dB 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp 45 dB Digital Logic Levels (CMOS Levels) Input LOW level VIL Input HIGH level VIH 0.3 x DVDD 0.7 x DVDD Input leakage current ±0.2 Input capacitance ±1 5 Output LOW VOL IOL=1mA Output HIGH VOH IOH= -1mA V V µA pF 0.1 x DVDD 0.9 x DVDD V V Analogue Reference Levels Reference voltage VVMID Potential divider resistance RVMID VREFP/2 – 50mV VREFP to VMID and VMID to VREFN VREFP/2 VREFP/2 + 50mV 50 V kΩ Supply Current Analogue supply current Digital supply current AVDD, VREFP = 5V 45 mA DVDD = 3.3V 16 mA Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). w PD Rev 4.2 October 2005 11 WM8772 Production Data TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w PD Rev 4.2 October 2005 12 WM8772 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter ±0.01 dB Passband 0 0.4535fs -6dB 0.5fs ±0.01 Passband ripple Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs -65 dB DAC Filter ±0.05 dB Passband 0.444fs -3dB 0.487fs ±0.05 Passband ripple Stopband dB 0.555fs Stopband Attenuation f > 0.555fs -60 dB Table 1 Digital Filter Characteristics DAC FILTER RESPONSES 0.2 0 0.15 -20 Response (dB) Response (dB) 0.1 -40 -60 0.05 0 -0.05 -80 -0.1 -100 -0.15 -120 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 1 DAC Digital Filter Frequency Response – 44.1, 48 and 96KHz 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 2 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 0 -0.2 Response (dB) Response (dB) -20 -40 -0.4 -0.6 -60 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 Figure 3 DAC Digital Filter Frequency Response – 192KHz w 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 4 DAC Digital Filter Ripple – 192kHz PD Rev 4.2 October 2005 13 WM8772 Production Data ADC FILTER RESPONSES 0.02 0 0.015 0.01 Response (dB) Response (dB) -20 -40 0.005 0 -0.005 -60 -0.01 -0.015 -80 -0.02 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 5 ADC Digital Filter Frequency Response 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 6 ADC Digital Filter Ripple ADC HIGH PASS FILTER The WM8772EDS has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H ( z) = 1 − z −1 1 − 0.9995z −1 DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 Figure 7 De-Emphasis Frequency Response (32kHz) w 16 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 8 De-Emphasis Error (32KHz) PD Rev 4.2 October 2005 14 WM8772 Production Data 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 9 De-Emphasis Frequency Response (44.1KHz) 0 5 10 Frequency (kHz) 15 20 Figure 10 De-Emphasis Error (44.1KHz) 0 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 11 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 12 De-Emphasis Error (48kHz) PD Rev 4.2 October 2005 15 WM8772EDS – 28 LEAD SSOP Production Data PAGES 12 TO 36 DESCRIBE THE OPERATION OF THE WM8772EDS 28 LEAD SSOP PRODUCT VARIANT. PAGES 37 TO 66 DESCRIBE THE OPERATION OF THE WM8772EFT 32 LEAD TQFP PRODUCT VARIANT. WM8772EDS – 28 LEAD SSOP MASTER CLOCK TIMING t MCLKL MCLK tMCLKH t MCLKY Figure 13 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high tMCLKH 11 ns MCLK System clock pulse width low tMCLKL 11 ns MCLK System clock cycle time tMCLKY 28 MCLK Duty cycle 40:60 ns 60:40 Table 2 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE – MASTER MODE BCLK LRC DSP/ ENCODER/ DECODER WM8772 CODEC DOUT DIN1/2/3 3 Figure 14 Audio Interface - Master Mode w PD Rev 4.2 October 2005 16 WM8772EDS – 28 LEAD SSOP Production Data BCLK (Output) tDL LRC (Output) tDDA DOUT DIN1/2/3 tDST tDHT Figure 15 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge tDL 0 10 ns DOUT propagation delay from BCLK falling edge tDDA 0 10 ns DIN1/2/3 setup time to BCLK rising edge tDST 10 ns DIN1/2/3 hold time from BCLK rising edge tDHT 10 ns Table 3 Digital Audio Data Timing – Master Mode w PD Rev 4.2 October 2005 17 WM8772EDS – 28 LEAD SSOP Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE LRC BCLK WM8772 CODEC DSP ENCODER/ DECODER DOUT DIN1/2/3 3 Figure 16 Audio Interface – Slave Mode tBCH tBCL BCLK tBCY LRC tDS tLRH tLRSU DIN1/2/3 tDD tDH DOUT Figure 17 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRC set-up time to BCLK rising edge tLRSU 10 ns LRC hold time from BCLK rising edge tLRH 10 ns DIN1/2/3 set-up time to BCLK rising edge tDS 10 ns DIN1/2/3 hold time from BCLK rising edge tDH 10 ns w PD Rev 4.2 October 2005 18 WM8772EDS – 28 LEAD SSOP Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL DOUT propagation delay from BCLK falling edge TEST CONDITIONS MIN tDD TYP 0 MAX UNIT 10 ns Table 4 Digital Audio Data Timing – Slave Mode MPU INTERFACE TIMING tCSL tCSH ML/I2S tSCY tCSS tSCS tSCL tSCH MC/IWL MD/DM LSB tDSU tDHO Figure 18 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT MC/IWL rising edge to ML/I2S rising edge tSCS 60 ns MC/IWL pulse cycle time tSCY 80 ns MC/IWL pulse width low tSCL 30 ns MC/IWL pulse width high tSCH 30 ns MD/DM to MC/IWL set-up time tDSU 20 ns MC/IWL to MD/DM hold time tDHO 20 ns ML/I2S pulse width low tCSL 20 ns ML/I2S pulse width high tCSH 20 ns ML/I2S rising to MC/IWL rising tCSS 20 ns Table 5 3-Wire SPI Compatible Control Interface Input Timing Information w PD Rev 4.2 October 2005 19 WM8772EDS – 28 LEAD SSOP Production Data DEVICE DESCRIPTION INTRODUCTION WM8772EDS is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multibit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as three separate stereo DACs and a stereo ADC in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3, the stereo ADC has it’s own data output DOUT. The word clock LRC, bit clock BCLK and master clock MCLK are shared between them. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode LRC and BCLK are all inputs. In Master mode LRC and BCLK are all outputs. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, for operation of both the ADC and DAC master clocks of 256fs, 384fs, 512fs and 768fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits RATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate master clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The master clock for WM8772EDS supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only). For ADC operation sample rates from 256fs to 768fs are supported. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8772EDS has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with LRC, although the WM8772EDS is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EDS. The signal processing for the WM8772EDS typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. w PD Rev 4.2 October 2005 20 WM8772EDS – 28 LEAD SSOP Production Data SAMPLING RATE (LRC) System Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 24.576 36.864 48kHz 6.144 9.216 12.288 18.432 96kHz 12.288 18.432 24.576 36.864 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Table 6 System Clock Frequencies Versus Sampling Rate (ADC does not support 128fs and 192fs) HARDWARE CONTROL MODES When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware mode the ADC and DAC will only run in slave mode. MUTE AND AUTOMUTE OPERATION In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected. Table 7 Mute and Automute Control Figure 19 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample. 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 19 Application and Release of Soft Mute w PD Rev 4.2 October 2005 21 WM8772EDS – 28 LEAD SSOP Production Data The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kΩ resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10kΩ source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below Figure 20. IZD (Register Bit) AUTOMUTED (Internal Signal) 10kΩ Ω SOFTMUTE (Internal Signal) MUTE PIN MUTE (Register Bit) Figure 20 Selection Logic for MUTE Modes INPUT FORMAT SELECTION In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for both the ADC and DAC. ML/I2S MC/IWL INPUT DATA MODE 0 0 24-bit right justified 0 1 20-bit right justified 1 0 16-bit I2S 1 1 24-bit I2S Table 8 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (LRC) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. DE-EMPHASIS CONTROL In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM DE-EMPHASIS 0 Off 1 On Table 9 De-emphasis Control w PD Rev 4.2 October 2005 22 WM8772EDS – 28 LEAD SSOP Production Data DIGITAL AUDIO INTERFACE MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EDS and DOUT is always an output. The default is Slave mode. In Slave mode, LRC and BCLK are inputs to the WM8772EDS (Figure 21). DIN1/2/3 and LRC are sampled by the WM8772EDS on the rising edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRC are sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK. LRC WM8772 CODEC BCLK DSP ENCODER/ DECODER DOUT DIN1/2/3 3 Figure 21 Slave Mode In Master mode, LRC and BCLK are outputs from the WM8772EDS (Figure 22). LRC and BCLK are generated by the WM8772EDS. DIN1/2/3 are sampled by the WM8772EDS on the rising edge of BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of BCLK, and DOUT changes on the rising edge of BCLK. BCLK WM8772 CODEC DSP/ ENCODER/ DECODER LRC DOUT DIN1/2/3 3 Figure 22 Master Mode w PD Rev 4.2 October 2005 23 WM8772EDS – 28 LEAD SSOP Production Data AUDIO INTERFACE FORMATS Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: • Left Justified mode • Right Justified mode • I2S mode • DSP mode A • DSP mode B All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with LRC indicating whether the left or right channel is present. LRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per LRC period is 2 times the selected word length. LRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRC is acceptable provided the above requirements are met. In DSP mode A or Mode B, all 6 DAC channels are time multiplexed onto DIN1. LRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRC period is 6 times the selected word length. Any mark to space ratio is acceptable on LRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or mode B, with LRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs per LRC period is 2 times the selected word length if only the ADC is being operated. LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the first rising edge of BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of BCLK as LRC and may be sampled on the rising edge of BCLK. LRC is high during the left samples and low during the right samples (Figure 23). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN1/2/3/ DOUT 1 MSB 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 23 Left Justified Mode Timing Diagram w PD Rev 4.2 October 2005 24 WM8772EDS – 28 LEAD SSOP Production Data RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding a LRC transition and may be sampled on the rising edge of BCLK. LRC are high during the left samples and low during the right samples (Figure 24). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN1/2/3/ DOUT 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 24 Right Justified Mode Timing Diagram 2 I S MODE In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the second rising edge of BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an LRC transition and may be sampled on the rising edge of BCLK. LRC are low during the left samples and high during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK 1 BCLK 1 BCLK DIN1/2/3/ DOUT 1 2 3 MSB n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 25 I2S Mode Timing Diagram w PD Rev 4.2 October 2005 25 WM8772EDS – 28 LEAD SSOP Production Data DSP MODE A In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the second rising edge on BCLK following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 26). Figure 26 DSP Mode Audio Interface - Mode A Slave, DAC 1 BCLK 1 BCLK 1/fs DACLRC DACBCLK CHANNEL 1 LEFT DIN1 1 2 MSB CHANNEL 1 RIGHT n n-1 1 2 n-1 n CHANNEL 2 LEFT 1 2 CHANNEL 3 RIGHT n-1 NO VALID DATA n LSB Input Word Length (IWL) Figure 27 DSP Mode Audio Interface - Mode A Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high LRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 26) Figure 28 DSP Mode Audio Interface - Mode A Slave, ADC w PD Rev 4.2 October 2005 26 WM8772EDS – 28 LEAD SSOP Production Data 1 BCLK 1 BCLK 1/fs ADCLRC ADCBCLK LEFT CHANNEL DOUT 1 2 RIGHT CHANNEL n n-1 MSB 1 2 n-1 NO VALID DATA n LSB Input Word Length (IWL) Figure 29 DSP Mode Audio Interface - Mode A Master, ADC DSP MODE B In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the first BCLK rising edge following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 30). Figure 30 DSP Mode Audio Interface - Mode B Slave, DAC 1/fs DACLRC DACBCLK CHANNEL 1 LEFT DIN1 1 2 MSB CHANNEL 1 RIGHT n n-1 1 2 n-1 CHANNEL 2 LEFT n 1 2 CHANNEL 3 RIGHT n-1 n NO VALID DATA 1 LSB Input Word Length (IWL) Figure 31 DSP Mode Audio Interface - Mode B Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of BCLK as the low to high LRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 32). w PD Rev 4.2 October 2005 27 WM8772EDS – 28 LEAD SSOP Production Data Figure 32 DSP Mode Audio Interface - Mode B Slave, ADC 1/fs ADCLRC BCK LEFT CHANNEL 1 DOUT 2 MSB RIGHT CHANNEL n n-1 1 2 n-1 NO VALID DATA n 1 LSB Input Word Length (IWL) Figure 33 DSP Mode Audio Interface - Mode B Master, ADC In both DSP mode A and mode B, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right. POWERDOWN MODES The WM8772EDS has powerdown control bits allowing specific parts of the WM8772EDS to be powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the ADC and DACs are powered down before setting PDWN. ZERO DETECT The WM8772EDS has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal (see Table 10) which may then be used to control external muting circuits. A ‘1’ on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD. DZFM[1:0] MUTE 00 All channels zero 01 Channel 1 zero 10 Channel 2 zero 11 Channel 3 zero Table 10 Zero Flag Output Select w PD Rev 4.2 October 2005 28 WM8772EDS – 28 LEAD SSOP Production Data SOFTWARE CONTROL INTERFACE OPERATION The WM8772EDS is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 34. ML/I2S MC/IWL MD/DM B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Figure 34 3-Wire SPI Compatible Interface w 1. B[15:9] are Control Address Bits 2. B[8:0] are Control Data Bits 3. ML/I2S is edge sensitive – the data is latched on the rising edge of ML/I2S. PD Rev 4.2 October 2005 29 WM8772EDS – 28 LEAD SSOP Production Data REGISTER MAP - 28 PIN SSOP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EDS can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 R0(00h) 0 0 0 0 0 0 0 UPDATE LDA1[7:0] 011111111 R1(01h) 0 0 0 0 0 0 1 UPDATE RDA1[7:0] 011111111 R2(02h) 0 0 0 0 0 1 0 PL[8:5] B2 B1 B0 PDWN IZD ATC MUTE DEEMP 100100000 All DAC PHASE[8:6] IWL[5:4] BCP DEFAULT All DAC FMT[1:0] LRP 000000000 R3(03h) 0 0 0 0 0 1 1 R4(04h) 0 0 0 0 1 0 0 UPDATE LDA2[7:0] 011111111 R5(05h) 0 0 0 0 1 0 1 UPDATE RDA2[7:0] 011111111 R6(06h) 0 0 0 0 1 1 0 UPDATE LDA3[7:0] 011111111 R7(07h) 0 0 0 0 1 1 1 UPDATE RDA3[7:0] 011111111 R8(08h) 0 0 0 1 0 0 0 UPDATE MASTDA[7:0] 011111111 R9(09h) 0 0 0 1 0 0 1 DEEMP[8:6] R10(0Ah) 0 0 0 1 0 1 0 RATE[8:6] R11(0Bh) 0 0 0 1 0 1 1 ADC OSR R12(0Ch) 0 0 0 1 1 0 0 0 R31(1Fh) 0 0 1 1 1 1 1 w DMUTE[5:3] MS 010 0 MPD DZFM[2:1] PWRDNALL DACPD[3:1] 0 0 0 RESET 00 ADCHP AMUTE ALL ZCD 000000000 ADCPD 010000000 00 001000000 AMUTEL AMUTER 000000000 000000000 PD Rev 4.2 October 2005 30 WM8772EDS – 28 LEAD SSOP Production Data CONTROL INTERFACE REGISTERS ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Channel Control 3 ATC 0 DESCRIPTION Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations INFINITE ZERO DETECT ENABLE Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Channel Control 4 IZD 0 DESCRIPTION Infinite Zero Mute Enable 0 : Disable inifinite zero mute 1: Enable infinite zero mute With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo channel receives a non-zero input. DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: w REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Control 8:5 PL[3:0] 1001 DESCRIPTION PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 1111 (L+R)/2 (L+R)/2 PD Rev 4.2 October 2005 31 WM8772EDS – 28 LEAD SSOP Production Data ADC AND DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 1:0 FMT [1:0] 00 DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B 2 In left justified, right justified or I S modes, the LRP register bit controls the polarity of LRC. If this bit is set high, the expected polarity of LRC will be the opposite of that shown Figure 23, Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between mode A and mode B. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 2 LRP 0 DESCRIPTION In left/right/I2S Modes: LRC Polarity (normal) 0 : Normal LRC polarity 1: Inverted LRC polarity In DSP Mode: 0 : DSP mode A 1: DSP mode B By default, LRC and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change on the falling edge. By default, LRC and DOUT are sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change LRC and DOUT on the rising edge of BCLK can be supported by setting the BCP register bit. Data sources that change LRC and DIN1/2/3 on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 23 to Figure 33. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 3 BCP 0 DESCRIPTION BCLK Polarity (DSP Modes): 0: Normal BCLK polarity 1: Inverted BCLK polarity The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 5:4 IWL [1:0] 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8772EDS pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels. w PD Rev 4.2 October 2005 32 WM8772EDS – 28 LEAD SSOP Production Data DAC OUTPUT PHASE The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS BIT LABEL DEFAULT 0000011 DAC Phase 8:6 PHASE [2:0] 000 DESCRIPTION Bit DAC Phase 0 DAC1L/R 1 = invert 1 DAC2L/R 1 = invert 2 DAC3L/R 1 = invert DIGITAL ZERO CROSS-DETECT The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS BIT LABEL DEFAULT 0001001 DAC Control 0 ZCD 0 DESCRIPTION DAC Digital Volume Zero Cross Disable: 0: Zero cross detect enabled 1: Zero cross detect disabled MUTE FLAG OUTPUT The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the MUTEB pin. A ‘1’ on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS BIT LABEL DEFAULT 0001001 Zero Flag 2:1 DZFM[1:0] 00 DESCRIPTION Selects the output MUTE pin (A ‘1’ indicates 1024 consecutive zero input samples on the DAC channels selected. 00: All channels zero 01: Channel 1 zero 10: Channel 2 zero 11: Channel 3 zero DAC MUTE MODES The WM8772EDS has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a ‘soft’ mute to the input of the digital filters of the channel muted. REGISTER ADDRESS 0001001 DAC Mute w BIT 5:3 LABEL DMUTE [2:0] DEFAULT 000 DESCRIPTION DAC Soft Mute Select DMUTE [2:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Not MUTE Not MUTE Not MUTE 001 MUTE Not MUTE Not MUTE 010 Not MUTE MUTE Not MUTE Not MUTE 011 MUTE MUTE 100 Not MUTE Not MUTE MUTE 101 MUTE Not MUTE MUTE 110 Not MUTE MUTE MUTE PD Rev 4.2 October 2005 33 WM8772EDS – 28 LEAD SSOP Production Data Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Mute 0 MUTEALL 0 DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels Refer to Figure 19 for the plot of application and release of soft mute. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output. ADC MUTE MODES Each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS BIT LABEL DEFAULT 0001100 ADC Mute 0 AMUTER 0 ADC Mute Select: 0 : Normal operation 1: mute ADC right DESCRIPTION 1 AMUTEL 0 ADC Mute Select: 0 : Normal operation 1: mute ADC left 2 AMUTEALL 0 ADC Mute Select: 0 : Normal operation 1: mute both ADC channels DE-EMPHASIS MODE Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001001 DAC De-Emphahsis Control [8:6] DEEMPH [1:0] 000 De-emphasis Channel Selection Select: DEEMPH [1:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS 001 DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS 010 Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS 011 DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS 100 Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS 101 DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS 110 Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS Refer to Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for details of the DeEmphasis performance at different sample rates. w REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC DEMP 1 DEEMP ALL 0 DESCRIPTION DEMMP Select: 0 : Normal operation 1: De-emphasis all channels PD Rev 4.2 October 2005 34 WM8772EDS – 28 LEAD SSOP Production Data POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the DAC’s on the WM8772EDS, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS BIT LABEL DEFAULT 0000010 Powerdown Control 2 PDWN 0 DESCRIPTION Power Down all DAC’s Select: 0: All DAC’s enabled 1: All DAC’s disabled The ADC and DACs may also be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Powerdown Control 0 ADCPD 0 ADC Disable: 0: Active 1: Disable DESCRIPTION 3:1 DACPD[2:0] 000 DAC Disable DACPD [2:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Active Active Active 001 DISABLE Active Active 010 Active DISABLE Active 011 DISABLE DISABLE Active 100 Active Active DISABLE 101 DISABLE Active DISABLE 110 Active DISABLE DISABLE 111 DISABLE DISABLE DISABLE MASTER POWERDOWN This control bit powers down the references for the whole chop. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Interface Control 4 PWRDNALL 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down MASTER MODE SELECT Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRC and BCLK are outputs and are generated by the WM8772EDS. In Slave mode LRC and BCLK are inputs to WM8772EDS. w REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001010 Interface Control 5 MS 0 DAC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode PD Rev 4.2 October 2005 35 WM8772EDS – 28 LEAD SSOP Production Data MASTER MODE LRC FREQUENCY SELECT In Master mode the WM8772EDS generates LRC and BCLK. These clocks are derived from the master clock and the ratio of MCLK to LRC is set by RATE. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Interface Control 8:6 RATE [2:0] 010 DESCRIPTION Master Mode MCLK:LRC Ratio Select: 000: 128fs (DAC only) 001: 192fs (DAC only) 010: 256fs 011: 384fs 100: 512fs 101: 768fs ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a 128fs oversampling rate irrespective of what this bit is set to. REGISTER ADDRESS BIT DEFAULT DESCRIPTION LABEL 0001011 ADC Oversampling Rate 8 ADCOSR 0 ADC Oversampling Rate Select: 0: 128x oversampling 1: 64x oversampling ADC HIGHPASS FILTER DISABLE The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS BIT LABEL DEFAULT 0001100 ADC Control 3 ADCHPD 0 DESCRIPTION ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled MUTE PIN DECODE The MUTE pin can either be used an output or an input. When used as an input the MUTE pins action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DAC’s. w REGISTER ADDRESS BIT LABEL DEFAULT 0001100 ADC Control 6 MPD 0 DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable PD Rev 4.2 October 2005 36 WM8772EDS – 28 LEAD SSOP Production Data DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000000 Digital Attenuation DACL1 7:0 LDA1[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 11 8 UPDATE Not latched 0000001 Digital Attenuation DACR1 7:0 RDA1[6:0] 11111111 (0dB) 8 UPDATE Not latched 0000100 Digital Attenuation DACL2 7:0 LDA2[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000101 Digital Attenuation DACR2 7:0 RDA2[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000110 Digital Attenuation DACL3 7:0 LDA3[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000111 Digital Attenuation DACR3 7:0 RDA3[7:0] 11111111 (0dB) 8 UPDATE Not latched 0001000 Master Digital Attenuation (all channels) 7:0 MASTDA [7:0] 11111111 (0dB) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. L/RDAX[7:0] ATTENUATION LEVEL 00(hex) -∞ dB (mute) 01(hex) -127dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 11 Digital Volume Control Attenuation Levels w PD Rev 4.2 October 2005 37 WM8772EDS – 28 LEAD SSOP Production Data SOFTWARE REGISTER RESET Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed. w PD Rev 4.2 October 2005 38 WM8772EDS – 28 LEAD SSOP Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION De-coupling for DVDD and AVDD. C1 and C5 10µF C2 to C4 0.1µF C8 and C9 1µF C6 and C10 0.1µF C7 and C11 10µF C12 10µF Filtering for VREFP. Omit if AVDD low noise. R1 33Ω Filtering for VREP. Use 0Ω if AVDD low noise. De-coupling for DVDD and AVDD. Analogue input high pass filter capacitors Reference de-coupling capacitors for VMID and ADCREF pin. Table 12 External Components Description w PD Rev 4.2 October 2005 39 WM8772EDS – 28 LEAD SSOP Production Data SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8772EDS produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 35 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results. 1.0nF 10uF 1.8kΩ Ω 7.5kΩ Ω 51Ω Ω VOUT1L 10kΩ Ω 680pF 4.7kΩ Ω 4.7kΩ Ω OP_FIL VOUT1R OP_FIL VOUT2L OP_FIL VOUT2R OP_FIL VOUT3L OP_FIL VOUT3R OP_FIL Figure 35 Recommended Post DAC Filter Circuit w PD Rev 4.2 October 2005 40 WM8772EDS – 28 LEAD SSOP Production Data To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below. Figure 36 Output Clamp Circuit When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held ‘on’, NPN transistors Q4 to Q9 of the clamp circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully charged transistors Q10 and Q4 to Q9 are switched off setting the outputs active. When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In turn, transistors Q4 to Q9 of the clamp circuits are switched on holding the outputs of the evaluation board near to GND until the rest of the circuitry on the board has settled. Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS supply drops quicker than any other supply to ensure that the outputs are clamped during the period when ‘pop’ noise may occur. w PD Rev 4.2 October 2005 41 WM8772EDS – 28 LEAD SSOP Production Data PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) b DM007.E e 28 15 E1 1 D E GAUGE PLANE 14 c A A2 A1 Θ L 0.25 L1 -C0.10 C Symbols A A1 A2 b c D e E E1 L L1 θ MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 o 0 REF: Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 SEATING PLANE MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 o 8 JEDEC.95, MO-150 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD Rev 4.2 October 2005 42 WM8772EFT – 32 LEAD TQFP Production Data WM8722EFT - 32 LEAD TQFP MASTER CLOCK TIMING t MCLKL ADCMCLK/ DACMCLK tMCLKH t MCLKY Figure 37 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information ADCMCLK and DACMCLK System clock pulse width high tMCLKH 11 ns ADCMCLK and DACMCLK System clock pulse width low tMCLKL 11 ns ADCMCLK and DACMCLK System clock cycle time tMCLKY 28 ns ADCMCLK and DACMCLK Duty cycle 40:60 60:40 Table 13 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE – MASTER MODE ADCBCLK ADCLRC DACBCLK WM8772 CODEC DACLRC DSP/ ENCODER/ DECODER DOUT DIN1/2/3 3 Figure 38 Audio Interface - Master Mode w PD Rev 4.2 October 2005 43 WM8772EFT – 32 LEAD TQFP Production Data ADCBCLK/ DACBCLK (Outputs) tDL ADCLRC/ DACLRC (Outputs) tDDA DOUT DIN1/2/3 tDST tDHT Figure 39 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from ADCBCLK/DACBCLK falling edge tDL 0 10 ns DOUT propagation delay from ADCBCLK falling edge tDDA 0 10 ns DIN1/2/3 setup time to DACBCLK rising edge tDST 10 ns DIN1/2/3 hold time from DACBCLK rising edge tDHT 10 ns Table 14 Digital Audio Data Timing – Master Mode w PD Rev 4.2 October 2005 44 WM8772EFT – 32 LEAD TQFP Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE ADCBCLK ADCLRC DSP ENCODER/ DECODER WM8772 DACBCLK CODEC DACLRC DOUT DIN1/2/3 3 Figure 40 Audio Interface – Slave Mode tBCH DACBCLK/ ADCBCLK tBCL tBCY DACLRC/ ADCLRC tDS tLRH tLRSU DIN1/2/3 tDD tDH DOUT Figure 41 Digital Audio Data Timing – Slave Mode w PD Rev 4.2 October 2005 45 WM8772EFT – 32 LEAD TQFP Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCBCLK/DACBCLK cycle time tBCY 50 ns ADCBCLK/DACBCLK pulse width high tBCH 20 ns ADCBCLK/DACBCLK pulse width low tBCL 20 ns ADCLRC/DACLRC set-up time to ADCBCLK/DACBCLK rising edge tLRSU 10 ns ADCLRC/DACLRC hold time from ADCBCLK/DACBCLK rising edge tLRH 10 ns DIN1/2/3 set-up time to DACBCLK rising edge tDS 10 ns DIN1/2/3 hold time from DACBCLK rising edge tDH 10 ns DOUT propagation delay from ADCBCLK falling edge tDD 0 10 ns Table 15 Digital Audio Data Timing – Slave Mode MPU INTERFACE TIMING tCSL tCSH ML/I2S tSCY tSCH tCSS tSCL tSCS MC/IWL MD/DM LSB tDSU tDHO Figure 42 SPI Compatible Control Interface Input Timing w PD Rev 4.2 October 2005 46 WM8772EFT – 32 LEAD TQFP Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated SYMBOL MIN MC/IWL rising edge to ML/I2S rising edge PARAMETER tSCS 60 TYP MAX UNIT ns MC/IWL pulse cycle time tSCY 80 ns MC/IWL pulse width low tSCL 30 ns MC/IWL pulse width high tSCH 30 ns MD/DM to MC/IWL set-up time tDSU 20 ns MC/IWL to MD/DM hold time tDHO 20 ns ML/I2S pulse width low tCSL 20 ns ML/I2S pulse width high tCSH 20 ns ML/I2S rising to MC/IWL rising tCSS 20 ns Table 16 3-Wire SPI Compatible Control Interface Input Timing Information w PD Rev 4.2 October 2005 47 WM8772EFT – 32 LEAD TQFP Production Data DEVICE DESCRIPTION INTRODUCTION WM8772EFT is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multibit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as three separate stereo DACs and a stereo ADC in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3. DAC word clock DACLRC, DAC bit clock DACBCLK and DAC master clock DACMCLK are shared between them. The stereo ADC has it’s own data output DOUT, word clock ADCLRC, bit clock ADCBCLK and ADC master clock ADCMCLK. This allows the ADC and DAC to run independently. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all inputs. In Master mode ADCLRC and ADCBCLK, DACLRC and DACBCLK are all outputs. The DAC’s and ADC can be in any combination of master or slave mode. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC, and 256fs, 384fs, 512fs, and 768fs is provided for the ADC. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bits ADCRATE and DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate master clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the ADC and DAC MCLK input pin(s) with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. The DAC master clock for WM8772EFT supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only). The ADC master clock for WM8772EFT supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8772EFT has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master clocks must be synchronised with ADCLRC and DACLRC respectively, although the WM8772EFT is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EFT. w PD Rev 4.2 October 2005 48 WM8772EFT – 32 LEAD TQFP Production Data The signal processing for the WM8772EFT typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. SAMPLING RATE (DACLRC/ ADCLRC) System Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 24.576 36.864 48kHz 6.144 9.216 12.288 18.432 96kHz 12.288 18.432 24.576 36.864 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Table 17 System Clock Frequencies Versus Sampling Rate (ADC does not support 128fs and 192fs) HARDWARE CONTROL MODES When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware mode the ADC and DAC will only run in slave mode. MUTE AND AUTOMUTE OPERATION In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 Normal Operation 1 Mute DAC channels Floating Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected. Table 18 Mute and Automute Control Figure 43 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample. w PD Rev 4.2 October 2005 49 WM8772EFT – 32 LEAD TQFP Production Data 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 43 Application and Release of Soft Mute The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kΩ resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10kΩ source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below Figure 20. IZD (Register Bit) AUTOMUTED (Internal Signal) 10kΩ Ω MUTE PIN SOFTMUTE (Internal Signal) MUTE (Register Bit) Figure 44 Selection Logic for MUTE Modes w PD Rev 4.2 October 2005 50 WM8772EFT – 32 LEAD TQFP Production Data INPUT FORMAT SELECTION In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for both the ADC and DAC. ML/I2S MC/IWL 0 0 24-bit right justified INPUT DATA MODE 0 1 20-bit right justified 1 0 16-bit I2S 1 1 24-bit I2S Table 19 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (ADCLRC and DACLRC) are high for a minimum of 24 bit clocks (ADCBCLK and DACBCLK) and low for a minimum of 24 bit clocks. DE-EMPHASIS CONTROL In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM DE-EMPHASIS 0 Off 1 On Table 20 De-emphasis Control DIGITAL AUDIO INTERFACE MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the DACMS and ADCMS control bits. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EFT and DOUT is always an output. The default is Slave mode for ADC and DAC. In Slave mode, ADCLRC, DACLRC and ADCBCLK, DACBCLK are inputs to the WM8772EFT (Figure 21). DIN1/2/3, ADCLRC and DACLRC are sampled by the WM8772EFT on the rising edge of ADCBCLK and DACBCLK respectively. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 and DACLRC are sampled on the falling edge of DACBCLK. By setting the control bit ADCBCP the polarity of ADCBCLK may be reversed so that ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of ADCBCLK. ADCBCLK ADCLRC DSP ENCODER/ DECODER WM8772 DACBCLK CODEC DACLRC DOUT DIN1/2/3 3 Figure 45 Slave Mode In Master mode, ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the WM8772EFT (Figure 22). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the WM8772EFT. w PD Rev 4.2 October 2005 51 WM8772EFT – 32 LEAD TQFP Production Data DIN1/2/3 are sampled by the WM8772EFT on the rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of DACBCLK. By setting control bit ADCBCP the polarity of ADCBCLK may be reversed so that DOUT changes on the rising edge of ADCBCLK. ADCBCLK ADCLRC DACBCLK DSP/ ENCODER/ DECODER WM8772 CODEC DACLRC DOUT DIN1/2/3 3 Figure 46 Master Mode AUDIO INTERFACE FORMATS Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: • Left Justified mode • Right Justified mode • I2S mode • DSP mode A • DSP mode B All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC or DACLRC indicating whether the left or right channel is present. ADCLRC or DACLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of DACBCLK/ADCBCLK’s per DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word length DACBCLK/ADCBCLK’s and low for a minimum of word length DACBCLK/ADCBCLK’s. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements are met. In DSP mode A or mode B, all 6 DAC channels are time multiplexed onto DIN1. DACLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLK’s per DACLRC period is 6 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP mode A or mode B, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of ADCBCLK’s per ADCLRC period is 2 times the selected word length w PD Rev 4.2 October 2005 52 WM8772EFT – 32 LEAD TQFP Production Data LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 47). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN1/2/3/ DOUT 1 2 3 n-2 n-1 MSB n 1 LSB 2 3 n-2 n-1 MSB n LSB Figure 47 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EFT on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples ( Figure 48). 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN1/2/3/ DOUT 1 2 3 n-2 n-1 MSB n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 48 Right Justified Mode Timing Diagram w PD Rev 4.2 October 2005 53 WM8772EFT – 32 LEAD TQFP Production Data 2 I S MODE In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK 1 BCLK 1 BCLK DIN1/2/3/ DOUT 1 2 3 n-2 n-1 n 1 LSB MSB 2 3 n-2 n-1 n LSB MSB Figure 49 I2S Mode Timing Diagram DSP MODE A In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 50). Figure 50 DSP Mode Audio Interface - Mode A Slave, DAC 1 BCLK 1 BCLK 1/fs DACLRC DACBCLK CHANNEL 1 LEFT DIN1 1 2 MSB CHANNEL 1 RIGHT n-1 n 1 2 n-1 n CHANNEL 2 LEFT 1 2 CHANNEL 3 RIGHT NO VALID DATA n-1 n LSB Input Word Length (IWL) Figure 51 DSP Mode Audio Interface - Mode A Master, DAC w PD Rev 4.2 October 2005 54 WM8772EFT – 32 LEAD TQFP Production Data The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 52) Figure 52 DSP Mode Audio Interface - Mode A Slave, ADC 1 BCLK 1 BCLK 1/fs ADCLRC ADCBCLK LEFT CHANNEL DOUT 1 2 MSB RIGHT CHANNEL n n-1 1 2 n-1 NO VALID DATA n LSB Input Word Length (IWL) Figure 53 DSP Mode Audio Interface - Mode A Master, ADC DSP MODE B In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the first DACBCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 54). Figure 54 DSP Mode Audio Interface - Mode B Slave, DAC w PD Rev 4.2 October 2005 55 WM8772EFT – 32 LEAD TQFP Production Data 1/fs DACLRC DACBCLK CHANNEL 1 LEFT DIN1 1 2 CHANNEL 1 RIGHT n n-1 MSB 1 2 n-1 CHANNEL 2 LEFT n 1 2 CHANNEL 3 RIGHT n-1 n NO VALID DATA 1 LSB Input Word Length (IWL) Figure 55 DSP Mode Audio Interface - Mode B Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 56). Figure 56 DSP Mode Audio Interface - Mode A Slave, ADC 1/fs ADCLRC BCK LEFT CHANNEL DOUT 1 2 MSB RIGHT CHANNEL n n-1 1 2 n-1 NO VALID DATA n 1 LSB Input Word Length (IWL) Figure 57 DSP Mode Audio Interface - Mode B Master, ADC In both DSP mode A and mode B , DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right. w PD Rev 4.2 October 2005 56 WM8772EFT – 32 LEAD TQFP Production Data POWERDOWN MODES The WM8772EFT has powerdown control bits allowing specific parts of the WM8772EFT to be powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the ADC and DACs are powered down before setting PDWN. ZERO DETECT The WM8772EFT has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal (see Table 10) which may then be used to control external muting circuits. A ‘1’ on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD. DZFM[1:0] MUTE 00 All channels zero 01 Channel 1 zero 10 Channel 2 zero 11 Channel 3 zero Table 21 Zero Flag Output Select SOFTWARE CONTROL INTERFACE OPERATION The WM8772EFT is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. The control interfaces are 5V tolerant; meaning that the control interface input signals ML/I2S, MC/IWL and MD/DM may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. MUTE and MODE are also 5V tolerant. 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 34. ML/I2S MC/IWL MD/DM B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Figure 58 3-Wire SPI Compatible Interface w 4. B[15:9] are Control Address Bits 5. B[8:0] are Control Data Bits 6. ML/I2S is edge-sensitive – the data is latched on the rising edge of ML/I2S. PD Rev 4.2 October 2005 57 WM8772EFT – 32 LEAD TQFP Production Data REGISTER MAP – 32 PIN TQFP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EFT can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 R0(00h) 0 0 0 0 0 0 0 UPDATE LDA1[7:0] 011111111 R1(01h) 0 0 0 0 0 0 1 UPDATE RDA1[7:0] 011111111 R2(02h) 0 0 0 0 0 1 0 PL[8:5] B2 B1 PDWN IZD ATC DACIWL[5:4] DACBCP DACLRP DEFAULT MUTE DEEMP All DAC PHASE[8:6] B0 100100000 All DAC DACFMT[1:0] 000000000 R3(03h) 0 0 0 0 0 1 1 R4(04h) 0 0 0 0 1 0 0 UPDATE LDA2[7:0] 011111111 R5(05h) 0 0 0 0 1 0 1 UPDATE RDA2[7:0] 011111111 R6(06h) 0 0 0 0 1 1 0 UPDATE LDA3[7:0] 011111111 R7(07h) 0 0 0 0 1 1 1 UPDATE RDA3[7:0] 011111111 R8(08h) 0 0 0 1 0 0 0 UPDATE MASTDA[7:0] 011111111 R9(09h) 0 0 0 1 0 0 1 DEEMP[8:6] R10(0Ah) 0 0 0 1 0 1 0 DACRATE[8:6] R11(0Bh) 0 0 0 1 0 1 1 ADC OSR R12(0Ch) 0 0 0 1 1 0 0 0 R31(1Fh) 0 0 1 1 1 1 1 w SYNC DMUTE[5:3] DACMS PWRDN DACPD[3:1] ALL ADCRATE[7:5] ADCMS MPD ADCLRP ADCBCP DZFM[2:1] RESET ADCIWL[3:2] ADCHP AMUTE ALL ZCD 000000000 ADCPD 010000000 ADCFMT[1:0] 001000000 AMUTEL AMUTER 000000000 000000000 PD Rev 4.2 October 2005 58 WM8772EFT – 32 LEAD TQFP Production Data CONTROL INTERFACE REGISTERS ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Channel Control 3 ATC 0 DESCRIPTION Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations INFINITE ZERO DETECT ENABLE Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Channel Control 4 IZD 0 DESCRIPTION Infinite zero mute enable 0: Disable infinite zero mute 1: Enable infinite zero mute With IZD enabled, applying 1024 consecutive zero input samples to each input will cause the relevant DAC to be muted to VMID. Mute will be removed as soon as that channel receives a non-zero input. DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: w REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Control 8:5 PL[3:0] 1001 DESCRIPTION PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 1111 (L+R)/2 (L+R)/2 PD Rev 4.2 October 2005 59 WM8772EFT – 32 LEAD TQFP Production Data DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the DACFMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 1:0 DACFMT [1:0] 00 DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B 2 In left justified, right justified or I S modes, the DACLRP register bit controls the polarity of DACLRC. If this bit is set high, the expected polarity of DACLRC will be the opposite of that shown Figure 23, Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the DACLRP register bit is used to select between mode A and mode B. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 2 DACLRP 0 DESCRIPTION In Left/Right/I2S Modes: DACLRC Polarity (normal) 0 : Normal DACLRC polarity 1: Inverted DACLRC polarity In DSP Mode: 0 : DSP mode A 1: DSP mode B By default, DACLRC and DIN1/2/3 are sampled on the rising edge of DACBCLK and should ideally change on the falling edge. Data sources that change DACLRC and DIN1/2/3 on the rising edge of DACBCLK can be supported by setting the BCP register bit. Setting DACBCP to 1 inverts the polarity of DACBCLK to the inverse of that shown in Figure 47 to Figure 57. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000011 Interface Control 3 DACBCP 0 DACBCLK Polarity (DSP Modes) 0 : Normal BCLK polarity 1: Inverted BCLK polarity The DACIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT 0000011 Interface Control 5:4 DACIWL [1:0] 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: If 32-bit mode is selected in right justified mode, the WM8772EFT defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8772EFT pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels. w PD Rev 4.2 October 2005 60 WM8772EFT – 32 LEAD TQFP Production Data DAC OUTPUT PHASE The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS BIT LABEL DEFAULT 0000011 DAC Phase 8:6 PHASE [2:0] 000 DESCRIPTION Bit DAC Phase 0 DAC1L/R 1 = invert 1 DAC2L/R 1 = invert 2 DAC3L/R 1 = invert DIGITAL ZERO CROSS-DETECT The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS BIT LABEL DEFAULT 0001001 DAC Control 0 ZCD 0 DESCRIPTION DAC Digital Volume Zero Cross Disable: 0: Zero cross detect enabled 1: Zero cross detect disabled MUTE FLAG OUTPUT The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the MUTEB pin. A ‘1’ on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001001 Zero Flag 2:1 DZFM[1:0] 00 Selects the output MUTE pin (A ‘1’ indicates 1024 consecutive zero input samples on the DAC channels selected. 00: All channels zero 01: Channel 1 zero 10: Channel 2 zero 11: Channel 3 zero DAC MUTE MODES The WM8772EFT has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a ‘soft’ mute to the input of the digital filters of the channel muted. w REGISTER ADDRESS BIT LABEL DEFAULT 0001001 DAC Mute 5:3 DMUTE [2:0] 000 DESCRIPTION DAC Soft Mute Select DMUTE [2:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Not MUTE Not MUTE Not MUTE 001 MUTE Not MUTE Not MUTE 010 Not MUTE MUTE Not MUTE Not MUTE 011 MUTE MUTE 100 Not MUTE Not MUTE MUTE 101 MUTE Not MUTE MUTE 110 Not MUTE MUTE MUTE PD Rev 4.2 October 2005 61 WM8772EFT – 32 LEAD TQFP Production Data Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC Mute 0 MUTEALL 0 DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels Refer to Figure 43 for the plot of application and release of soft mute. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output. ADC MUTE MODES Each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS BIT LABEL DEFAULT 0001100 ADC Mute 0 AMUTER 0 ADC Mute Select: 0 : Normal operation 1: mute ADC right DESCRIPTION 1 AMUTEL 0 ADC Mute Select: 0 : Normal operation 1: mute ADC left 2 AMUTEALL 0 ADC Mute Select: 0 : Normal operation 1: mute both ADC channels DE-EMPHASIS MODE Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001001 DAC De-emphahsis Control [8:6] DEEMPH 000 De-emphasis Channel Selection Select: [1:0] DEEMPH [1:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS 001 DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS 010 Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS 011 DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS 100 Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS 101 DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS 110 Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS Refer to Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for details of the DeEmphasis performance at different sample rates. w REGISTER ADDRESS BIT LABEL DEFAULT 0000010 DAC DEMP 1 DEEMP ALL 0 DESCRIPTION DEMMP Select: 0 : Normal operation 1: De-emphasis all channels PD Rev 4.2 October 2005 62 WM8772EFT – 32 LEAD TQFP Production Data POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the DAC’s on the WM8772EFT, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS BIT LABEL DEFAULT 0000010 Powerdown Control 2 PDWN 0 DESCRIPTION Power Down all DAC’s Select: 0: All DAC’s enabled 1: All DAC’s disabled The ADC and DACs may also be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. Resetting DACD will reinitialise the digital filters. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Powerdown Control 0 ADCPD 0 ADC Disable: 0: Active 1: Disable DESCRIPTION 3:1 DACPD [2:0] 000 DAC Disable DACPD [2:0] DAC CHANNEL 1 DAC CHANNEL 2 DAC CHANNEL 3 000 Active Active Active 001 DISABLE Active Active 010 Active DISABLE Active 011 DISABLE DISABLE Active 100 Active Active DISABLE 101 DISABLE Active DISABLE 110 Active DISABLE DISABLE 111 DISABLE DISABLE DISABLE MASTER POWERDOWN This control bit powers down the references for the whole chop. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Interface Control 4 PWRDNALL 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down DAC MASTER MODE SELECT Control bit DACMS selects between audio interface Master and Slave Modes. In Master mode DACLRC and DACBCLK are outputs and are generated by the WM8772EFT. In Slave mode DACCLRC, DACLRC and DACBCLK are inputs to WM8772EFT. w REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Interface Control 5 DACMS 0 DESCRIPTION DAC Audio Interface Master/Slave Mode Select: 0: Slave Mode 1: Master Mode PD Rev 4.2 October 2005 63 WM8772EFT – 32 LEAD TQFP Production Data MASTER MODE DACLRC FREQUENCY SELECT In Master mode the WM8772EFT generates DACLRC and DACBCLK. These clocks are derived from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE. REGISTER ADDRESS BIT LABEL DEFAULT 0001010 Interface Control 8:6 DACRATE [2:0] 010 DESCRIPTION Master Mode DACMCLK:DACLRC Ratio Select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs ADC DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the ADCFMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT 0001011 Interface Control 1:0 ADCFMT[1:0] 00 DESCRIPTION Interface Format Select 00: Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode A or B The ADCIWL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001011 Interface Control 3:2 ADCIWL[1:0] 00 Input Word Length 00: 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. ADC MASTER MODE SELECT Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8772EFT. In Slave mode ADCLRC and ADCBCLK are inputs to WM8772EFT. w REGISTER ADDRESS BIT LABEL DEFAULT 0001011 Interface Control 4 ADCMS 0 DESCRIPTION ADC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode PD Rev 4.2 October 2005 64 WM8772EFT – 32 LEAD TQFP Production Data MASTER MODE ADCLRC FREQUENCY SELECT In Master mode the WM8772EFT generates ADCLRC and ADCBCLK. These clocks are derived from the master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE. REGISTER ADDRESS BIT LABEL DEFAULT 0001011 ADCLRC and ADCBCLK Frequency Select 7:5 ADCRATE [2:0] 010 DESCRIPTION Master Mode ADCMCLK:ADCLRC Ratio Select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a 128fs oversampling rate irrespective of what this bit is set to. REGISTER ADDRESS BIT LABEL DEFAULT 0001011 ADC Oversampling Rate 8 ADCOSR 0 DESCRIPTION ADC Oversampling Rate Select 0: 128x oversampling 1: 64x oversampling ADC HIGHPASS FILTER DISABLE The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001100 ADC Control 3 ADCHPD 0 ADC Highpass Filter Disable: 0: Highpass filter enabled 1: Highpass filter disabled In left justified, right justified or I2S modes, the ADCLRP register bit controls the polarity of ADCLRC. If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure 47, Figure 48, and Figure 49. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register bit is used to select between modes A and B. REGISTER ADDRESS BIT LABEL DEFAULT 0001100 Interface Control 4 ADCLRP 0 DESCRIPTION In Left/Right/I2S Modes: ADCLRC Polarity (normal) 0: normal DACLRC polarity 1: inverted DACLRC polarity In DSP Mode: 0: DSP mode A 1: DSP mode B By default, DACLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the polarity of ADCBCLK to the inverse of that shown in Figure 47 to Figure 57. w PD Rev 4.2 October 2005 65 WM8772EFT – 32 LEAD TQFP Production Data REGISTER ADDRESS BIT LABEL DEFAULT 0001100 Interface Control 5 ADCBCP 0 DESCRIPTION ADCBCLK Polarity (DSP Modes): 0: normal BCLK polarity 1: inverted BCLK polarity MUTE PIN DECODE The MUTE pin can either be used an output or an input. When used as an input the MUTE pins action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DACs. REGISTER ADDRESS BIT LABEL DEFAULT 0001100 ADC Control 6 MPD 0 DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable DAC TO ADC SYNC If the DAC and ADC use the same MCLK, and they are operating in the same fs mode setting the SYNC bit will improve performance by synchronising the internal clock between the two blocks. Setting this at any other time may or may not improve or degrade the performance of the device. w REGISTER ADDRESS BIT LABEL DEFAULT 0001100 SYNC Control 7 SYNC 0 DESCRIPTION SYNC Function: 0: Disable 1: Enable PD Rev 4.2 October 2005 66 WM8772EFT – 32 LEAD TQFP Production Data DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000000 Digital Attenuation DACL1 7:0 LDA1[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 11 8 UPDATE Not latched 0000001 Digital Attenuation DACR1 7:0 RDA1[6:0] 11111111 (0dB) 8 UPDATE Not latched 0000100 Digital Attenuation DACL2 7:0 LDA2[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000101 Digital Attenuation DACR2 7:0 RDA2[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000110 Digital Attenuation DACL3 7:0 LDA3[7:0] 11111111 (0dB) 8 UPDATE Not latched 0000111 Digital Attenuation DACR3 7:0 RDA3[7:0] 11111111 (0dB) 8 UPDATE Not latched 0001000 Master Digital Attenuation (all channels) 7:0 MASTDA [7:0] 11111111 (0dB) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. L/RDAX[7:0] ATTENUATION LEVEL 00(hex) -∞ dB (mute) 01(hex) -127dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 22 Digital Volume Control Attenuation Levels w PD Rev 4.2 October 2005 67 WM8772EFT – 32 LEAD TQFP Production Data SOFTWARE REGISTER RESET Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed. w PD Rev 4.2 October 2005 68 WM8772EFT – 32 LEAD TQFP Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION De-coupling for DVDD and AVDD. C1 and C5 10µF C2 to C4 0.1µF C8 and C9 1µF C6 and C10 0.1µF C7 and C11 10µF C12 10µF Filtering for VREFP. Omit if AVDD low noise. R1 33Ω Filtering for VREP. Use 0Ω if AVDD low noise. De-coupling for DVDD and AVDD. Analogue input high pass filter capacitors Reference de-coupling capacitors for VMID and ADCREF pin. Table 23 External Components Description w PD Rev 4.2 October 2005 69 WM8772EFT – 32 LEAD TQFP Production Data SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8772EFT produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 59 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results. 1.0nF 10uF 1.8kΩ Ω 7.5kΩ Ω 51Ω Ω VOUT1L Ω 10kΩ 680pF 4.7kΩ Ω 4.7kΩ Ω OP_FIL VOUT1R OP_FIL VOUT2L OP_FIL VOUT2R OP_FIL VOUT3L OP_FIL VOUT3R OP_FIL Figure 59 Recommended Post DAC Filter Circuit w PD Rev 4.2 October 2005 70 WM8772EFT – 32 LEAD TQFP Production Data To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below. Figure 60 Output Clamp Circuit When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held ‘on’, NPN transistors Q4 to Q9 of the clamp circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully charged transistors Q10 and Q4 to Q9 are switched off setting the outputs active. When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In turn, transistors Q4 to Q9 of the clamp circuits are switched on holding the outputs of the evaluation board near to GND until the rest of the circuitry on the board has settled. Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure that the clamp is applied before the rest of the circuitry has time to power down. Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS supply drops quicker than any other supply to ensure that the outputs are clamped during the period when ‘pop’ noise may occur. w PD Rev 4.2 October 2005 71 WM8772EFT – 32 LEAD TQFP Production Data PACKAGE DIMENSIONS FT: 32 PIN TQFP (7 x 7 x 1.0 mm) b DM028.A e 24 17 25 16 E1 32 E 9 1 Θ 8 c D1 D L A A2 A1 -Cccc C Symbols A A1 A2 b c D D1 E E1 e L Θ ccc REF: SEATING PLANE Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.30 0.37 0.45 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.80 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.10 JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD Rev 4.2 October 2005 72 Production Data WM8772EFT – 32 LEAD TQFP IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD Rev 4.2 October 2005 73