SIMTEK STK11C68-LF45

STK11C68 (SMD5962–92324)
8Kx8 SoftStore nvSRAM
FEATURES
DESCRIPTION
• 25, 35, 45, and 55 ns Read Access & R/W Cycle
Times
The Simtek STK11C68 is a 64Kb fast static RAM
with a nonvolatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Pin compatible with Industry Standard SRAMs
• Software-initiated Non-Volatile STORE
The SRAM provides the fast access & cycle times,
ease of use, and unlimited read & write endurance
of a normal SRAM.
Data transfers under software control to the non-volatile storage cells (the STORE operation). On
power-up, data is automatically restored to the
SRAM (the RECALL operation). RECALL operations
are also available under software control.
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V + 10% Operation
• Commercial, Industrial, and Military Temperatures
• 28 pin 330 mil SOIC (RoHS-Compatible)
The Simtek nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads.
It is the highest performance, most reliable nonvolatile memory available.
BLOCK DIAGRAM
• 28-pin CDIP and LCC packages
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
ROW DECODER
QUANTUM TRAP
128 x 512
STORE
STATIC RAM
ARRAY
128 X 512
STORE/
RECALL
CONTROL
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INPUT BUFFERS
SOFTWARE
DETECT
A0 – A12
COLUMN I/O
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0007 Rev 0.3
February, 2007
STK11C68 (SMD5962–92324)
PIN CONFIGURATIONS
NC
1
28
VCC
A12
2
27
A7
3
26
W
NC
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
G
A2
8
21
A10
A1
9
20
A0
10
19
E
DQ7
DQ0
11
18
DQ6
DQ1
12
17
DQ5
DQ2
13
16
DQ4
VSS
14
15
DQ3
28-Pin LCC
28-Pin DIP
28-Pin SOIC
PIN NAMES
Pin Name
I/O
Description
A12-A0
Input
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
DQ7-DQ0
I/O
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
E
Input
Chip Enable: The active low E input selects the device
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
VCC
Power Supply
Power: 5.0V, ±10%
VSS
Power Supply
Ground
Document Control #ML0007 Rev 0.3
February, 2007
2
STK11C68 (SMD5962–92324)
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(VCC = 5.0V ± 10%)
DC CHARACTERISTICS
SYMBOL
COMMERCIAL
INDUSTRIAL/
MILITARY
MIN
MIN
PARAMETER
MAX
UNITS
NOTES
MAX
ICC1b
Average VCC Current
90
75
65
N/A
90
75
65
55
mA
mA
mA
mA
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
tAVAV = 55ns
ICC2c
Average VCC Current during STORE
3
3
mA
All Inputs Don’t Care, VCC = max
ICC3b
Average VCC Current at tAVAV = 200ns
5V, 25°C, Typical
10
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS Levels
ISB1d
Average VCC Current
(Standby, Cycling TTL Input Levels)
27
23
20
N/A
28
24
21
20
mA
mA
mA
mA
tAVAV = 25ns, E ≥ VIH
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
tAVAV = 55ns, E ≥ VIH
ISB2d
VCC Standby Current
(Standby, Stable CMOS Input Levels)
750
1500
μA
E ≥ (V CC - 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±5
±5
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.2
VCC + .5
2.2
VIL
Input Logic “0” Voltage
VSS – .5
0.8
VSS – .5 0.8
V
All Inputs
VOH
Output Logic “1” Voltage
2.4
2.4
V
IOUT = – 4mA
VOL
Output Logic “0” Voltage
0.4
V
IOUT = 8mA
TA
Operating Temperature
85
°C
0.4
0
70
–40
VCC + .5 V
All Inputs
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) .
2
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
5.0V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe
SYMBOL
(TA = 25°C, f = 1.0MHz)
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input capacitance
8
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
Note e: These parameters are guaranteed but not tested.
Document Control #ML0007 Rev 0.3
February, 2007
480 Ohms
3
STK11C68 (SMD5962–92324)
SRAM READ CYCLES #1 & #2
(VCC = 5.0V + 10%)
SYMBOLS
NO.
STK11C68-25
STK11C68-35
STK11C68-45
STK11C68-55
PARAMETER
#1, #2
1
tELQV
2
tAVAV
f
3
tAVQVg
4
tGLQV
UNITS
Alt.
MIN
MAX
MIN
MIN
MAX
tRC
Read Cycle Time
tAA
Address Access Time
25
35
45
55
ns
tOE
Output Enable to Data Valid
10
15
20
25
ns
5
tAXQXg
tOH
Output Hold after Address Change
5
5
5
5
ns
6
tELQX
tLZ
Chip Enable to Output Active
5
5
5
5
ns
7
tEHQZh
tHZ
Chip Disable to Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZh
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
10
tELICCH
11
tEHICCLd, e
35
10
0
0
55
15
0
0
15
0
45
SRAM READ CYCLE #1: Address Controlledf, g
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
tAVAV
ADDRESS
1
11
tELQV
tEHICCL
6
tELQX
E
7
tEHQZ
G
9
tGHQZ
4
8
tGLQV
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ICC
ACTIVE
STANDBY
Document Control #ML0007 Rev 0.3
February, 2007
4
ns
ns
55
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
ns
ns
25
0
35
ns
ns
25
0
13
25
55
45
13
10
0
45
MAX
Chip Enable Access Time
25
35
MIN
tACS
e
25
MAX
ns
STK11C68 (SMD5962–92324)
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V + 10%)
SYMBOLS
STK11C68-25
NO.
STK11C68-35
STK11C68-45
STK11C68-55
PARAMETER
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
35
45
55
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
45
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
45
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
30
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
45
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
0
0
ns
20
tWLQZh, i
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
Note i:
Note j:
10
13
5
5
15
5
5
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
15
tDVWH
DATA IN
DATA OUT
16
tWHDX
DATA VALID
20
tWLQZ
HIGH IMPEDANCE
PREVIOUS DATA
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledj
12
tAVAV
ADDRESS
14
tELEH
18
tAVEL
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
DATA IN
DATA OUT
Document Control #ML0007 Rev 0.3
February, 2007
16
tEHDX
DATA VALID
HIGH IMPEDANCE
5
35
ns
ns
STK11C68 (SMD5962–92324)
STORE INHIBIT/POWER-UP RECALL
(VCC = 5.0V + 10%)
SYMBOLS
STK11C68
NO.
PARAMETER
Standard
UNITS NOTES
MIN
22
tRESTORE
Power-up RECALL Duration
23
tSTORE
STORE Cycle Duration
24
VSWITCH
Low Voltage Trigger Level
25
VRESET
Low Voltage Reset Level
4.0
MAX
550
μs
10
ms
4.5
V
3.6
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
VCC
5V
24
VSWITCH
25
VRESET
STORE INHIBIT
POWER-UP RECALL
22
tRESTORE
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Document Control #ML0007 Rev 0.3
February, 2007
6
k
STK11C68 (SMD5962–92324)
SOFTWARE STORE/RECALL MODE SELECTION
E
L
L
Note l:
W
A12 - A0 (hex)
MODE
I/O
NOTES
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE STORE/RECALL CYCLEm, n
NO.
SYMBOLS
(VCC = 5.0V ± 10%)
STK11C68-25
STK11C68-35
STK11C68-45
STK11C68-55
MIN
MIN
MIN
MIN
PARAMETER
UNITS
MAX
MAX
MAX
MAX
26
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
55
ns
27
tAVELm
Address Set-up Time
0
0
0
0
ns
28
tELEHm
Clock Pulse Width
20
25
30
35
ns
29
tELAXm
Address Hold Time
20
20
20
20
ns
30
tRECALL
m
RECALL Duration
20
20
20
20
μs
Note m: The software sequence is clocked with E controlled reads.
Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledn
26
26
tAVAV
ADDRESS
tAVAV
ADDRESS #1
27
tAVEL
ADDRESS #6
28
tELEH
E
29
tELAX
23
tSTORE
DQ (DATA
DATA VALID
DATA VALID
Document Control #ML0007 Rev 0.3
February, 2007
7
30
/ tRECALL
HIGH IMPEDANCE
STK11C68 (SMD5962–92324)
DEVICE OPERATION
The STK11C68 is a versatile memory chip that provides several modes of operation. The STK11C68
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 Nonvolatile Elements shadow to which the
SRAM information can be copied or from which the
SRAM can be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C68 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between Vcc
and Vss, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK11C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for transitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
Document Control #ML0007 Rev 0.3
February, 2007
8
SOFTWARE NONVOLATILE STORE
The STK11C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
STK11C68 (SMD5962–92324)
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK11C68 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC < VSWITCH, software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
100
Average Active Current (mA)
Average Active Current (mA)
100
80
60
40
TTL
20
80
60
TTL
40
CMOS
20
CMOS
0
0
50
100
150
Cycle Time (ns)
50
200
Figure 2: ICC (max) Reads
Document Control #ML0007 Rev 0.3
February, 2007
100
150
Cycle Time (ns)
Figure 3: ICC (max) Writes
9
200
STK11C68 (SMD5962–92324)
Commercial/Industrial Ordering Information
STK11C68 - S F 45 I TR
Temperature Range
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
S = Plastic 28-pin 330 mil SOIC
C = Ceramic 28-pin 300 mil DIP
L = Ceramic 28-pin 350 mil LCC
Document Control #ML0007 Rev 0.3
February, 2007
10
STK11C68 (SMD5962–92324)
Millitary Ordering Information
STK11C68 - 5 C 45 M
Temperature Range
M = Military (–55 to 125°C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
5 = Military (10 years/105cycles)
SMD5962-92324 04 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Device Class Indication—Class M
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
Document Control #ML0007 Rev 0.3
February, 2007
11
STK11C68 (SMD5962–92324)
Ordering Information
Part Number
Description
Temperature
STK11C68-SF25
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-SF35
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-SF45
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-SF25TR
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-SF35TR
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-SF45TR
5V 64K-8b SoftStore nvSRAM SOP28-330
Commercial
STK11C68-L35
5V 64K-8b SoftStore nvSRAM CLCC28
Commercial
STK11C68-L45
5V 64K-8b SoftStore nvSRAM CLCC28
Commercial
STK11C68-C35
5V 64K-8b SoftStore nvSRAM CDIP28-300
Commercial
STK11C68-C45
5V 64K-8b SoftStore nvSRAM CDIP28-300
Commercial
STK11C68-SF25I
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-SF35I
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-SF45I
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-SF25ITR
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-SF35ITR
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-SF45ITR
5V 64K-8b SoftStore nvSRAM SOP28-330
Industrial
STK11C68-L35I
5V 64K-8b SoftStore nvSRAM CLCC28
Industrial
STK11C68-L45I
5V 64K-8b SoftStore nvSRAM CLCC28
Industrial
STK11C68-C35I
5V 64K-8b SoftStore nvSRAM CDIP28-300
Industrial
STK11C68-C45I
5V 64K-8b SoftStore nvSRAM CDIP28-300
Industrial
STK11C68-5L35M
5V 64K-8b SoftStore nvSRAM CLCC28
Military
STK11C68-5L45M
5V 64K-8b SoftStore nvSRAM CLCC28
Military
STK11C68-5L55M
5V 64K-8b SoftStore nvSRAM CLCC28
Military
STK11C68-5C35M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
STK11C68-5C45M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
STK11C68-5C55M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
STK11C68-5K35M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
STK11C68-5K45M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
STK11C68-5K55M
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD5962-9232406MXA
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232405MXA
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232404MXA
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232406MXC
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232405MXC
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232404MXC
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232406MXX
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232405MXX
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232404MXX
5V 64K-8b SoftStore nvSRAM CDIP28-300
Military
SMD 5962-9232406MYA
5V 64K-8b SoftStore nvSRAM CLCC28
Military
SMD 5962-9232405MYA
5V 64K-8b SoftStore nvSRAM CLCC28
Military
SMD 5962-9232404MYA
5V 64K-8b SoftStore nvSRAM CLCC28
Military
SMD 5962-9232406MYX
5V 64K-8b SoftStore nvSRAM CLCC28
Military
SMD 5962-9232405MYX
5V 64K-8b SoftStore nvSRAM CLCC28
Military
SMD 5962-9232404MYX
5V 64K-8b SoftStore nvSRAM CLCC28
Military
Document Control #ML0007 Rev 0.3
February, 2007
12
STK11C68 (SMD5962–92324)
Package Diagrams
28 Pin 330 mil SOIC
0.713
0.733
( 18.11
)
18.62
0.112
(2.845)
0.020
0.014
( 0.508
)
0.356
0.050 (1.270)
0.103
0.093
0.336
0.326
0.004
(0.102)
( 2.616
)
2.362
( 8.534
)
8.280
0.477
0.453
( 12.116
)
11.506
Pin 1
0.014
0.008
10°
0°
( 0.356
)
0.203
0.044
0.028
DIM = INCHES
MIN
)
( MAX
DIM = mm
Document Control #ML0007 Rev 0.3
February, 2007
MIN
MAX
13
( 1.117
)
0.711
STK11C68 (SMD5962–92324)
28 Pin 300 mil SP DIL Sidebraze
1.386
1.414
35.20
(35.92
)
.280
.310
--.060
(7.36
7.87)
PIN
14
--(1.52
)
.124
( 3.15
4.14 ) .162
.040
.060
.125 (3.18)
MIN
.016
.020
.290
.310
(0.41
0.51)
.048
.052
( 7.37
7.87 )
(1.22
1.32)
( )
.090 2.29
.110 2.79
DIM = INCHES
DIM = mm
.009
.012
.300
.320
( 0.23
0.30 )
(7.62
8.13)
Document Control #ML0007 Rev 0.3
February, 2007
14
MIN
MAX
MIN
( MAX
)
(1.02
1.52)
STK11C68 (SMD5962–92324)
28 Pin 350 mil LCC
0.542 13.77
0.558 14.17
(
ο
)
(1.02) 0.040 REF X 45
3 places
(
0.342 8.69
0.358 9.09
)
ο
(0.51) 0.020 REF X 45
1.91
( 2.41
)
0.045 1.14
0.055 ( 1.40 )
0.075
0.095
(0.23) 0.009 REF
28 places
Pad 1
Index
(
0.022
0.028
0.56
0.71
)(
0.006
0.022
0.15
0.56
)
0.045
0.055
( 1.14
1.40 )
(
0.070 1.78
0.090 2.29
(
--0.558
--( 14.17
)
0.015
--0.381
---
)
)
0.062 1.57
0.078 1.98
(
)
DIM = INCHES
DIM = mm
Document Control #ML0007 Rev 0.3
February, 2007
15
MIN
MAX
MIN
( MAX
)
STK11C68 (SMD5962–92324)
Document Revision History
Revision
Date
Summary
0.0
December 2002
Combined commercial, industrial and military data sheets. Removed 20 nsec device.
0.1
September 2003
Added lead-free lead finish
0.2
March 2006
Removed leaded lead finish for all Commercial/Industrial Parts, Removed “P” package.
0.3
February 2007
Add fast power-down slew RSK information
Restore Comm/Ind C & L Package Options
Add Tape Reel Ordering Options
Add Product Ordering Code Listing
Add Package Outline Drawings
Reformat Entire Document
SIMTEK STK11C68 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Document Control #ML0007 Rev 0.3
February, 2007
16