CY24130 HOTLink II™ SMPTE Receiver Training Clock Features Benefits • Integrated phase-locked loop • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system designs • Enables application compatibility • Low-jitter, high-accuracy outputs • 3.3V operation Part Number Outputs Input Frequency Output Frequency Range CY24130-1 2 27 MHz (Driven Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) CY24130-2 2 27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) Logic Block Diagram XIN Q OSC. Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P CLKA PLL REFCLK S0 S1 S2 VDDL VDD AVDD AVSS VSS VSSL Pin Configuration CY24130-1, -2 16-pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD S2 REFCLK VSS 3 14 S0 4 13 AVSS 5 12 N/C VSSL 6 11 VDDL N/C CLKA 7 10 8 9 S1 N/C Cypress Semiconductor Corporation Document #: 38-07711 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 04, 2005 CY24130 Frequency Select Options S2 S1 S0 CLKA REFCLK Units 0 0 0 27 27 MHz 0 0 1 36 27 MHz 0 1 0 54 27 MHz 0 1 1 148.50 27 MHz 1 0 0 74.25 27 MHz 1 0 1 OFF, pulled low 27 MHz 1 1 0 OFF, pulled low 27 MHz 1 1 1 OFF, pulled low 27 MHz Pin Description Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. S0 4 Frequency Select 0. AVSS 5 Analog Ground. VSSL 6 VDDL Ground. N/C 7 No Connect. CLKA 8 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable). N/C 9 No Connect. S1 10 Frequency Select 1. VDDL 11 Voltage Supply. N/C 12 No Connect. VSS 13 Ground. REFCLK 14 Reference Clock Output. S2 15 Frequency Select 2. XOUT 16 Reference Crystal Output. Leave floating for -1. Absolute Maximum Conditions Parameter Description Min. Max. Unit –0.5 7.0 V VDD, AVDD Supply Voltage VDDL I/O Supply Voltage – 7.0 V TJ Junction Temperature – 125 °C AVSS – 0.3 AVDD + 0.3 V 2 – kV Digital Inputs Electro-Static Discharge Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.135 3.3 3.465 V VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 27 – MHz CLNOM Nominal Parallel Crystal Load Capacitance for -2 – 18 – pF Document #: 38-07711 Rev. ** Page 2 of 5 CY24130 DC Electrical Specifications Parameter[1] Name Description Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 – mA IIH Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V – – 10 µA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – V VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 V IVDD Supply Current AVDD/VDD Current – 16 – mA IVDDL Supply Current VDDL Current – 14 – mA AC Electrical Specifications Parameter[1] Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Description 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns t9 Clock Jitter CLKA Peak-Peak Period Jitter – 100 – ps t10 PLL Lock Time – – 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF DUT CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definitions Note: 1. Not 100% tested. Document #: 38-07711 Rev. ** Page 3 of 5 CY24130 t4 t3 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24130ZXC-1 16-Pin TSSOP Commercial 3.3V CY24130ZXC-1T 16-Pin TSSOP – Tape and Reel Commercial 3.3V CY24130ZXC-2 16-Pin TSSOP Commercial 3.3V CY24130ZXC-2T 16-Pin TSSOP – Tape and Reel Commercial 3.3V Lead-free Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07711 Rev. ** Page 4 of 5 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24130 Document History Page Document Title: CY24130 HOTLink II™ SMPTE Receiver Training Clock Document Number: 38-07711 REV. ECN NO. Issue Date Orig. of Change ** 314514 See ECN RGL Document #: 38-07711 Rev. ** Description of Change New Data Sheet Page 5 of 5