ETC CY26113

CY26113
One-PLL General Purpose
Clock Generator
Features
Benefits
• Integrated phase-locked loop
Internal PLL with up to 333 MHz internal operation
• Low skew, low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
• Frequency Select Pin
Dynamic frequency selection
• 3.3V Operation with 2.5V output options
Enables application compatibility
• 16-TSSOP
Industry standard package saves on board space
Part Number
CY26113
Outputs
Input Frequency
Output Frequency Range
4
25 MHz
4 x 40/80 MHz (selectable)
Logic Block Diagram
XIN
Q
OSC.
Pin Configurations
Φ
CY26113
16-pin TSSOP
LCLK1 40/80 MHz
VCO
XOUT
LCLK2 40/80 MHz
P
PLL
LCLK3 40/80 MHz
OUTPUT
MULTIPLEXER
AND
DIVIDERS
LCLK4 40/80 MHz
FS
XIN
VDD
1
16
XOUT
2
15
AVDD
3
14
NC
NC
OE
4
13
VSS
AVSS
5
12
LCLK4
VSSL
6
11
VDDL
LCLK1
7
10
LCLK2
8
9
FS
LCLK3
OE
VSSL
VDD
AVDD
AVSS
VSS
VDDL
Output
Pin
Default Frequency
Unit
LCLK 1
7
40/80 (selectable)
MHz
LCLK 2
8
40/80 (selectable)
MHz
LCLK 3
9
40/80 (selectable)
MHz
LCLK 4
12
40/80 (selectable)
MHz
Cypress Semiconductor Corporation
Document #: 38-07097 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
CY26113
Pin Definitions
Name
Pin Number
Description
XIN
1
Reference Input
VDD
2
Voltage Supply
AVDD
3
Analog Voltage Supply
OE
4
Output Enable, OE = 0 three-state; OE = 1 active
AVSS
5
Analog Ground
VSSL
6
LCLK Ground
LCLK1
7
Clock output 1–40/80 MHz
LCLK2
8
Clock output 2–40/80 MHz
LCLK3
9
Clock output 3–40/80 MHz
FS
10
Frequency Select Pin - FS = 0: 40 MHz. FS = 1: 80 MHz
VDDL
11
LCLK Voltage Supply (2.5V or 3.3V)
LCLK4
12
Clock output 4–40/80 MHz
VSS
13
Ground
NC
14
No Connect - Reserved
NC
15
No Connect - Reserved
16
Reference Output
XOUT
[1]
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
–0.5
7.0
V
VDD
Supply Voltage
VDDL
I/O Supply Voltage
7.0
V
TJ
Junction Temperature
125
°C
Digital Inputs
AVSS – 0.3
AVDD + 0.3
V
Digital Outputs referred to VDD
VSS – 0.3
VDD + 0.3
V
Digital Outputs referred to VDDL
VSS – 0.3
VDDL +0.3
Electro-Static Discharge
2
V
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.0
3.3
3.6
V
VDDL
Operating Voltage
2.375
2.5
2.625
V
TA
Ambient Temperature
70
°C
CLOAD
Max. Load Capacitance
VDD/VDDL=3.3V
0
15
pF
CLOAD
Max. Load Capacitance
VDDL=2.5V
15
pF
fREF
Driven Reference Frequency
tPU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be
monotonic)
25
0.05
MHz
500
ms
Note:
1. Float XOUT if XIN is externally driven
Document #: 38-07097 Rev. *A
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CY26113
DC Electrical Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD/VDDL = 3.3V
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD/VDDL=3.3V
12
24
mA
IOH
Output High Current
VOH = VDDL – 0.5, VDDL=2.5V
8
16
mA
IOL
Output Low Current
VOL = 0.5, VDDL = 2.5V
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
CIN
Input Capacitance
OE and FS Pins
IIZ
Input Leakage Current
OE and FS Pins
0.7
VDD
0.3
7
VDD
pF
µA
5
IVDD
Supply Current
AVDD/VDD Current
22
mA
IVDDL
Supply Current
VDDL Current (VDDL=3.6V)
25
mA
IVDDL
Supply Current
VDDL Current (VDDL=2.625V)
20
mA
AC Electrical Characteristics
Parameter
Name
DC
Description
Min.
Typ.
Max.
Unit
Duty Cycle is defined in Figure 2; t1/t2 @ 50%
of VDD
45
50
55
%
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of
VDD/VDDL = 3.3V
0.8
1.4
V/ns
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of
VDDL = 2.5V
0.6
1.2
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% – 20% of
VDD/VDDL = 3.3V
0.8
1.4
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% – 20% of
VDDL = 2.5V
0.6
1.2
V/ns
t5
Skew
Delay between related outputs at rising edge
250
t9
Clock Jitter
Peak to Peak period jitter
250
ps
t10
PLL Lock Time
3
ms
ps
D
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1.
t3
t4
80%
CLK
20%
Figure 2. Rise and Fall Time Definitions.
Note:
2. Not 100% tested.
Document #: 38-07097 Rev. *A
Page 3 of 5
CY26113
Test Circuit
VDD
CLK out
0.1 µF
CLOAD
OUTPUTS
AVDD
0.1 µF
GND
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26113ZC
Z16
16-Pin TSSOP
Commercial
3.3V
Document #: 38-07097 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26113
Document Title: CY26113 One-PLL General-Purpose Clock Generator
Document Number: 38-07097
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
107332
08/28/01
CKN
New Data Sheet
*A
121866
12/14/02
RBI
Document #: 38-07097 Rev. *A
Power up requirements added to Operating
Conditions Information
Page 5 of 5