FAIRCHILD MM74HC221ASJ

Revised January 2004
MM74HC221A
Dual Non-Retriggerable Monostable Multivibrator
General Description
Features
The MM74HC221A high speed monostable multivibrators
(one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits.
■ Typical propagation delay: 40 ns
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC221A
can be triggered on the positive transition of the clear while
A is held LOW and B is held HIGH.
■ Fanout of 10 LS-TTL loads
The MM74HC221A is a non-retriggerable, and therefore
cannot be retriggered until the output pulse times out.
■ Wide power supply range: 2V–6V
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Simple pulse width formula T = RC
■ Wide pulse range: 400 ns to ∞ (typ)
■ Part to part variation: ±5% (typ)
■ Schmitt Trigger A & B inputs enable infinite signal input
rise or fall times
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where
PW is in seconds, R is in ohms, and C is in farads. All
inputs are protected from damage due to static discharge
by diodes to VCC and ground.
Ordering Code:
Order Number
Package Number
Package Description
MM74HC221AM
(Note 1)
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC221ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC221AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Timing Component
Top View
Note: Pin 6 and Pin 14 must be hard-wired to GND.
© 2004 Fairchild Semiconductor Corporation
DS005325
www.fairchildsemi.com
MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
September 1983
MM74HC221A
Truth Table
Inputs
Outputs
Clear
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
H
L
↑
H
↓
H
↑
L
H
H = HIGH Level
L = LOW Level
↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant
Logic Diagram
www.fairchildsemi.com
2
L
H
Recommended Operating
Conditions
(Note 3)
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5V to VCC+1.5V
DC Output Voltage (VOUT)
−0.5V to VCC+0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
(VIN, VOUT)
Operating Temperature Range (TA)
S.O. Package only
500 mW
Lead Temperature (TL)
V
0
VCC
V
−40
+85
°C
VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Note 2: Maximum Ratings are those values beyond which damage to the
device may occur.
260°C
(Soldering 10 seconds)
Units
6
Time (Clear Input)
Power Dissipation (PD)
600 mW
Max
2
Maximum Input Rise and Fall
−65°C to +150°C
(Note 4)
Min
DC Input or Output Voltage
±50 mA
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Supply Voltage (VCC)
Note 3: Unless otherwise specified all voltages are referenced to ground.
Note 4: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Conditions
(Note 5)
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Minimum HIGH Level
2.0V
1.5
1.5
1.5
Input Voltage
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
Maximum LOW Level
2.0V
0.3
0.3
0.3
Input Voltage
4.5V
0.9
0.9
0.9
6.0V
1.2
1.2
1.2
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
Units
V
V
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
0.4
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
VIN = VCC or GND
6.0V
±0.5
±5.0
±5.0
µA
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum Quiescent Supply VIN = VCC or GND
6.0V
8.0
80
160
µA
V
VIN = VIH or VIL
IIN
Maximum Input Current
(Pins 7, 15)
IIN
Maximum Input Current
(all other pins)
ICC
Current (standby)
ICC
IOUT = 0 µA
Maximum Active Supply
VIN = VCC or GND
2.0V
36
80
110
130
µA
Current (per monostable)
R/CEXT = 0.5VCC
4.5V
0.33
1.0
1.3
1.6
mA
6.0V
0.7
2.0
2.6
3.2
mA
Note 5: For a power supply of 5V ±10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
MM74HC221A
Absolute Maximum Ratings(Note 2)
MM74HC221A
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
tPLH
Parameter
Conditions
Guaranteed
Typ
Maximum Trigger Propagation
Units
Limit
22
36
ns
25
42
ns
ns
Delay A, B or Clear to Q
tPHL
Maximum Trigger Propagation
Delay A, B or Clear to Q
tPHL
Maximum Propagation Delay Clear to Q
20
31
tPLH
Maximum Propagation Delay Clear to Q
22
33
ns
tW
Minimum Pulse Width A, B or Clear
14
26
ns
tREM
Minimum Clear Removal Time
tWQ(MIN)
Minimum Output Pulse Width
CEXT = 28 pF
tWQ
Output Pulse Width
CEXT = 1000 pF
0
ns
400
ns
10
µs
REXT = 2 kΩ
REXT = 10 kΩ
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
tPLH
tPHL
tPHL
tPLH
tW
tREM
Parameter
VCC
Conditions
Units
Guaranteed Limits
2.0V
77
169
194
Delay A, B or Clear to Q
4.5V
26
42
51
57
6.0V
21
32
39
44
Maximum Trigger Propagation
2.0V
88
197
229
250
Delay A, B or Clear to Q
4.5V
29
48
60
67
6.0V
24
38
46
51
Maximum Propagation
2.0V
54
114
132
143
Delay Clear to Q
4.5V
23
34
41
45
6.0V
19
28
33
36
Maximum Propagation
2.0V
56
116
135
147
Delay Clear to Q
4.5V
25
36
42
46
6.0V
20
29
34
37
210
Minimum Pulse Width
2.0V
57
123
144
157
A, B, Clear
4.5V
17
30
37
42
6.0V
12
21
27
30
Minimum Clear
2.0V
0
0
0
Removal Time
4.5V
0
0
0
6.0V
0
0
0
Rise and Fall Time
tWQ
TA = −40 to 85°C TA = −55 to 125°C
Maximum Trigger Propagation
tTLH, tTHL Maximum Output
tWQ(MIN)
TA = 25°C
Typ
2.0V
30
75
95
110
4.5V
8
15
19
22
6.0V
7
13
16
19
ns
ns
ns
ns
ns
ns
ns
Minimum Output
CEXT = 28 pF
2.0V
1.5
Pulse Width
REXT = 2 kΩ
4.5V
450
ns
REXT = 6 kΩ (VCC = 2V)
6.0V
380
ns
CEXT = 0.1 µF
Min
5.0V
1
0.9
0.86
0.85
ms
Max
5.0V
1
1.1
1.14
1.15
ms
Output Pulse Width
µs
REXT = 10 kΩ
CPD
Power Dissipation
87
pF
Capacitance (Note 6)
CIN
Maximum Input
12
20
20
20
pF
6
10
10
10
pF
Capacitance (Pins 7 & 15)
CIN
Maximum Input
Capacitance (Other Inputs)
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD V CCf + ICC.
www.fairchildsemi.com
4
MM74HC221A
Theory of Operation
FIGURE 1.
TRIGGER OPERATION
It should be noted that in the quiescent state CEXTis fully
charged to VCC causing the current through resistor REXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC221 is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of CEXT, REXT, or the duty cycle of the input
waveform.
As shown in Figure 1 and the logic diagram before an input
trigger occurs, the monostable is in the quiescent state with
the Q output LOW, and the timing capacitor CEXT completely charged to VCC. When the trigger input A goes from
VCC to GND (while inputs B and clear are held to VCC) a
valid trigger is recognized, which turns on comparator C1
and N-channel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor CEXT rapidly discharges toward GND until VREF1 is reached. At this
point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor CEXT begins to charge through the timing
resistor, REXT, toward VCC. When the voltage across CEXT
equals VREF2, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
The MM74HC221 is non-retriggerable and will ignore input
transitions on A and B until it has timed out 3 and 4.
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to VCC by turning on transistor Q1 5. When
the voltage on the capacitor reaches VREF2, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held LOW, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear
is at VCC2). The MM74HC221 can also be triggered when
clear goes from GND to VCC (while A is at Gnd and B is at
VCC6).
5
www.fairchildsemi.com
MM74HC221A
Typical Output Pulse Width
vs. Timing Components
Typical 1ms Pulse Width Variation
vs. Supply
Typical Distribution of Output
Pulse Width, Part to Part
Minimum REXT
vs. Supply Voltage
Typical 1 ms Pulse Width Variation
vs. Temperature
Note: R and C are not subjected to temperature. The C is polypropylene.
www.fairchildsemi.com
6
MM74HC221A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
7
www.fairchildsemi.com
MM74HC221A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com
8
MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
9
www.fairchildsemi.com