Revised July 2004 MM74HC595 8-Bit Shift Registers with Output Latches General Description Features The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. ■ Low quiescent current: 80 µA maximum (74HC Series) This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. ■ Cascadable ■ Low input current: 1 µA maximum ■ 8-bit serial-in, parallel-out shift register with storage ■ Wide operating voltage range: 2V–6V ■ Shift register has direct clear ■ Guaranteed shift frequency: DC to 30 MHz The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number MM74HC595M MM74HC595SJ MM74HC595MTC MM74HC595N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SCLR G X X X H QA thru QH = 3-STATE Function X X L L Shift Register cleared Q’H = 0 X ↑ H L Shift Register clocked ↑ X H L Contents of Shift QN = Qn-1, Q0 = SER Register transferred to output latches Top View © 2004 Fairchild Semiconductor Corporation DS005342 www.fairchildsemi.com MM74HC595 8-Bit Shift Registers with Output Latches September 1983 MM74HC595 Logic Diagram (positive logic) www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±35 mA Min Max Units 2 6 V 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) DC VCC or GND Current, Input Rise or Fall Times ±70 mA per pin (ICC) −65°C to +150°C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (TL) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 6.0V 1.8 1.8 1.8 Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA QA thru QH 2.0V 2.0 1.9 1.9 1.9 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 |IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 Units V V V VIN = VIH or VIL V VIN = VIH or VIL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA V 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 |IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 |IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum 3-STATE VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA Output Leakage G = V IH 6.0V 8.0 80 160 µA Q’H QA thru QH IIN (Note 4) Minimum HIGH Level Q’H VOL Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. 260°C (Soldering 10 seconds) Maximum Input V VIN = VIH or VIL V VIN = VIH or VIL V Current IOZ ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC595 Absolute Maximum Ratings(Note 1) MM74HC595 AC Electrical Characteristics VCC = 5V, TA = 25°C, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Limit Units 50 30 MHz CL = 45 pF 12 20 ns CL = 45 pF 18 30 ns Frequency of SCK tPHL, tPLH Maximum Propagation Delay, SCK to Q’H tPHL, tPLH Maximum Propagation Delay, RCK to QA thru QH tPZH, tPZL tPHZ, tPLZ tS Maximum Output Enable RL = 1 kΩ Time from G to QA thru QH CL = 45 pF 17 28 ns Maximum Output Disable RL = kΩ 15 25 ns Time from G to QA thru QH CL = 5 pF 20 ns 20 ns 40 ns 0 ns 16 ns Minimum Setup Time from SER to SCK tS Minimum Setup Time from SCLR to SCK tS Minimum Setup Time from SCK to RCK (Note 5) tH Minimum Hold Time from SER to SCK tW Minimum Pulse Width of SCK or RCK Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register. AC Electrical Characteristics VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Conditions CL = 50 pF Frequency tPHL, tPLH Maximum Propagation Delay from SCK to Q’H tPHL, tPLH Maximum Propagation Guaranteed Limits 2.0V 10 6 4.8 4.5V 45 30 24 20 6.0V 50 35 28 24 2.0V 58 210 265 315 83 294 367 441 CL = 50 pF 4.5V 14 42 53 63 CL = 150 pF 4.5V 17 58 74 88 CL = 50 pF 6.0V 10 36 45 54 CL = 150 pF 6.0V 14 50 63 76 CL = 50 pF Units 4.0 2.0V 2.0V 70 175 220 265 2.0V 105 245 306 368 CL = 50 pF 4.5V 21 35 44 53 CL = 150 pF 4.5V 28 49 61 74 CL = 50 pF 6.0V 18 30 37 45 CL = 150 pF 6.0V 26 42 53 63 2.0V 175 221 261 4.5V 35 44 52 6.0V 30 37 44 Delay from SCLR to Q’H www.fairchildsemi.com TA = −40 to 85°C TA = −55 to 125°C CL = 150 pF tPHL, tPLH Maximum Propagation from G to QA thru QH TA = 25°C Typ CL = 50 pF Delay from RCK to QA thru QH CL = 150 pF tPZH, tPZL Maximum Output Enable VCC MHz ns ns ns ns ns ns ns RL = 1 kΩ CL = 50 pF 2.0V 75 175 220 265 CL = 150 pF 2.0V 100 245 306 368 CL = 50 pF 4.5V 15 35 44 53 CL = 150 pF 4.5V 20 49 61 74 CL = 50 pF 6.0V 13 30 37 45 CL = 150 pF 6.0V 17 42 53 63 4 ns ns ns Symbol Parameter tPHZ, tPLZ Maximum Output Disable Time from G to QA thru QH tS tR tS tH tW tr, tf Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C RL = 1 kΩ 2.0V 75 175 220 265 4.5V 15 35 44 53 6.0V 13 30 37 45 Minimum Setup Time 2.0V 100 125 150 from SER to SCK 4.5V 20 25 30 6.0V 17 21 25 Minimum Removal Time 2.0V 50 63 75 from SCLR to SCK 4.5V 10 13 15 6.0V 9 11 13 Minimum Setup Time 2.0V 100 125 150 from SCK to RCK 4.5V 20 25 30 6.0V 17 21 26 Minimum Hold Time 2.0V 5 5 5 SER to SCK 4.5V 5 5 5 6.0V 5 5 5 Minimum Pulse Width 2.0V 30 80 100 120 of SCK or SCLR 4.5V 9 16 20 24 6.0V 8 14 18 22 1000 Maximum Input Rise and 2.0V 1000 1000 Fall Time, Clock 4.5V 500 500 500 6.0V 400 400 400 90 2.0V 25 60 75 Rise and Fall Time 4.5V 7 12 15 18 QA–QH 6.0V 6 10 13 15 tTHL, tTLH Maximum Output 2.0V 75 95 110 Rise & Fall Time 4.5V 15 19 22 Q'H 6.0V 13 16 19 Power Dissipation G = VCC 90 Capacitance, Outputs G = GND 150 Units Guaranteed Limits CL = 50 pF tTHL, tTLH Maximum Output CPD (Continued) ns ns ns ns ns ns ns ns ns pF Enabled (Note 6) CIN Maximum Input 5 10 10 10 pF 15 20 20 20 pF Capacitance COUT Maximum Output Capacitance Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 5 www.fairchildsemi.com MM74HC595 AC Electrical Characteristics MM74HC595 Timing Diagram www.fairchildsemi.com 6 MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com MM74HC595 8-Bit Shift Registers with Output Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10