LINER RH1128MW

DICE/DWF SPECIFICATION
RH1028M/RH1128M
Ultralow Noise Precision
High Speed Op Amps
PAD FUNCTION
1
2
8
7
3
1.
2.
3.
4.
5.
6.
7.
8.
VOS TRIM
–IN
+IN
V–
OVER-COMP
OUT
V+
VOS TRIM
X = 0 for LT1028B,
1 for LT1128B
DIE CROSS REFERENCE
LTC Finished
Part Number
Order
Part Number
RH1028MW
RH1028MW
RH1028 DICE
RH1028 DWF*
RH1128MW
RH1128MW
RH1128 DICE
RH1128 DWF*
Please refer to LTC standard product data sheet for
other applicable product information.
*DWF = DICE in wafer form.
6
4
5
114mils × 81mils,
Backside (substrate) metal: Alloyed gold layer
Backside potential: Connect to V –
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
DICE/DWF ELECTRICAL TEST LIMITS
SYMBOL
PARAMETER
VOS
Input Offset Voltage (Note 1)
IOS
Input Offset Current
IB
Input Bias Current
VIN
Input Voltage Range
CMRR
Common Mode Rejection Ratio
PSRR
VS = ±15V, TA = 25°C, VCM = 0V, unless otherwise noted.
CONDITIONS
MIN
MAX
UNITS
300
μV
VCM = 0V
150
nA
VCM = 0V
±400
nA
±11
V
VCM = ±11V
VCM = ±10.3V
110
dB
Power Supply Rejection Ratio
VS = ±4V to ±16V
VS = ±4.5V to ±16V
110
dB
A VOL
Large Scale Voltage Gain
RL ≥ 2k, VO = ±10V
RL ≥ 1k, VO = ±10V
RL ≥ 600Ω, VO = ±10V
5
3.5
2
V/μV
V/μV
V/μV
VOUT
Maximum Output Voltage Swing
RL ≥ 2k
RL ≥ 600Ω
±12
±10.5
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
V
V
1
DICE/DWF SPECIFICATION
RH1028M/RH1128M
DICE/DWF ELECTRICAL TEST LIMITS
VS = ±15V, TA = 25°C, VCM = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
SR
Slew Rate
A VCL = –1 (RH1028)
A VCL = –1 (RH1128)
11
4.5
IS
Supply Current
MAX
UNITS
V/μs
V/μs
10.5
mA
Note 1: Input offset voltage measurements are performed by automatic
test equipment approximately 0.5 seconds after application of power.
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-1028
2
Linear Technology Corporation
LT 0908 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008