RICHTEK RT9173

RT9173/A
1.5A/3A Bus Termination Regulator
General Description
Features
The RT9173/A regulator is designed to convert
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voltage supplies ranging from 1.8V to 6V into a
Support Both DDR 1 (1.25VTT) and DDR 2
(0.9VTT) Requirements
desired output voltage which adjusted by two external
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Power TO-263-5 and SOP-8 Packages
resistors, voltage divider. The regulator is capable of
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Capable of Sourcing and Sinking Current
sourcing or sinking up to 1.5A/3A of current while
regulating an output voltage to within 2% or less.
1.5A/3A
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Current-limiting Protection
The RT9173/A, used in conjunction with series
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Thermal Protection
termination resistors, provides an excellent voltage
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Integrated Power MOSFETs
source for active termination schemes of high speed
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Generates Termination Voltages for SSTL-2
transmission lines as those seen in high speed
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High Accuracy Output Voltage at Full-load
memory buses and distributed backplane designs.
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Adjustable VOUT by External Resistors
The voltage output of the regulator can be used as a
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Minimum External Components
termination voltage for DDR SDRAM.
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Shutdown for Standby or Suspend Mode
Operation with High-impedance Output
Current limits in both sourcing and sinking mode, plus
on-chip thermal shutdown make the circuit tolerant of
Pin Configurations
the output fault conditions.
Part Number
Applications
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Computers
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Disk Drives
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CD-ROM
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Supply Splitter
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Graph Card
Pin Configurations
RT9173ACM5
TOP VIEW
(Plastic TO-263-5)
1.
2.
3.
4.
5.
1 2 3 4 5
RT9173CS
Ordering Information
(Plastic SOP-8)
RT9173/A… ……
Package type
M5 : TO-263-5
S : SOP-8
Operating temperature range
C: Commercial standard
VIN
GND
VCNTL (TAB)
REFEN
VOUT
TOP VIEW
VIN 1
8
VCNTL
GND 2
7
VCNTL
REFEN 3
6
VCNTL
VOUT 4
5
VCNTL
Function Block Diagram
3A sink & source
1.5A sink & source
VCNTL
VIN
Current
Limiting Sensor
CNTL
REFEN
VOUT
Thermal
GND
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RT9173/A
Pin Description
Pin Name
Pin Function
VIN
Power Input
GND
Ground
VCNTL
Gate Drive Voltage
REFEN
Reference Voltage Input and Chip Enable
VOUT
Output Voltage
Absolute Maximum Ratings
z
Input Voltage
7V
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Power Dissipation
Internally Limited
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ESD Rating
2KV
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Storage Temperature Range
-65°C to 150°C
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Lead Temperature (Soldering, 5 sec.)
260°C
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Package Thermal Resistance
TO-263,θJC
7.7°C/W
TO-263,θJA
19.4°C/W
SOP-8, θJC
SOP-8, θJA
15.7°C/W
Note
45°C/W
Note: θJA is measured with the component mounted on an evaluation PC board in free air that the required area of
2
copper is 300mm or larger.
Electrical Characteristics
(Limits in standard typeface are for TA = 25°C, unless otherwise specified:
VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10µF (Ceramic))
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
-20
0
20
mV
IL : 0 → 1.5A, Fig.1
--
0.8
2
IL : 0A → -1.5A
--
0.8
2
1.8
2.5
--
Output Offset Voltage
VOS
Fig.1
Load Regulation
∆VLOAD
Input Voltage Range
VIN
Keep VCNTL ≥ VIN on operation
(DDR 1)
VCNTL
power on and power off sequences
--
3.3
6
Current In Shutdown Mode
ISHDN
VREFEN < 0.2V, RL = 180Ω, Fig.2
--
50
90
Fig.3,4
2.1
--
--
Fig.3,4
3.0
--
--
Thermal Shutdown Temperature TSD
3.3V ≤ VCNTL ≤ 5V
125
150
--
°C
Thermal Shutdown Hysteresis
Guaranteed by design
--
50
--
°C
Output = High, Fig.5
0.8
--
--
Output = Low, Fig.5
--
--
0.2
%
V
µA
Short Circuit Protection
Current limit
RT9173
RT9173A
ILIMIT
A
Over Temperature Protection
Shutdown Function
Shutdown Threshold Trigger
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2
V
DS9173/A-06 March 2002
RT9173/A
Typical Application Circuit
VCNTL= 3.3V
VIN = 2.5V
R1
VIN
VCNTL
RT9173/A
REFEN
VOUT
R2
GND
2N7002
EN
RTT
CCNTL
CIN
COUT
CSS
RDUMMY
R1 = R2 = 100KΩ, RTT = 50Ω / 33Ω / 25Ω
COUT,min = 10µF (Ceramic) + 1000µF under the worst case testing condition
RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present
CSS = 1µF, CIN = 470µF (Low ESR), CCNTL = 47µF
Test Circuit
2.5V
3.3V
VIN
1.25V
REFEN
VCNTL
RT9173/A
VOUT
VOUT
GND
IL
V
COUT
Fig.1 Output Voltage Tolerance, ∆VOUT
2.5V
3.3V
A
VIN
1.25V
0.2V
REFEN
VCNTL
1.25V
VOUT
RT9173/A VOUT
GND
V
RL
0V
COUT
RL and COUT
Time delay
Fig.2 Current in Shutdown Mode, ISHCLN
DS9173/A-06 March 2002
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RT9173/A
2.5V
3.3V
VIN
REFEN
1.25V
VCNTL
VOUT
VOUT
RT9173/A
GND
A
V
IL
COUT
Fig.3 Current Limit for High Side, ICLHIGH
Power supply
with current limit
2.5V
3.3V
VIN
1.25V
REFEN
A
IL
VCNTL
RT9173/A
VOUT
VOUT
GND
V
COUT
Fig.4 Current Limit for Low Side, ICLLOW
3.3V
2.5V
VIN
1.25V
VREFEN
REFEN
0.2V
VCNTL
RT9173/A
VOUT
VOUT
GND
RL
V
COUT
1.25V
VOUT
0V
VOUT would be low if VREFEN < 0.2V
VOUT would be high if VREFEN > 0.8V
RL and COUT
Time delay
Fig.5 REFEN Pin Shutdown Threshold, VTRIGGER
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DS9173/A-06 March 2002
RT9173/A
Typical Operating Characteristics
Sinking Current (Peak) vs. Temp.
8.0
7.0
7.0
6.0
6.0
Sinking Current (A)
Sourcing Current (A)
Sourcing Current (Peak) vs. Temp.
8.0
5.0
4.0
3.0
2.0
VCNTL = 3.3V
VIN = 2.5V
VOUT = 1.25V
1.0
0.0
-40
-20
0
20
40
60
80
Temperature ( ° C)
100
5.0
4.0
3.0
2.0
VCNTL = 3.3V
VIN = 2.5V
VOUT = 1.25V
1.0
0.0
120
-40
650
650
600
550
500
-20
0
20
40
60
Temperature ( ° C)
80
40
60
80
100
120
100
600
550
500
450
VCNTL = 3.3V
VIN = 2.5V
-40
20
Turn-On Threshold vs. Temp.
700
Threshold Voltage (mV)
Threshold Voltage (mV)
Turn-On Threshold vs. Temp.
400
0
Temperature ( °C)
700
450
-20
VCNTL = 5.0V
VIN = 2.5V
400
120
-40
-20
0
20
40
60
80
100
120
Temperature ( °C)
VIN = 2.5V
50 VREFEN = 1.25V
12
VCNTL = 3.3V
Swing Frequency = 1KHz
0
-50
2
≈
≈
1
0
8
6
4
2
0
-1
-2
-2
-4
Time (250µS/Div)
DS9173/A-06 March 2002
VIN = 2.5V
VCNTL = 3.3V
VREFEN = 1.25V
10
Output Short Circuit (A)
Output Current (A)
Output Transient
Voltage (mV)
Transient Response
100
Force the output shorted to ground
Time (5mS/Div)
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RT9173/A
Applications Information
Internal parasitic diode
Thermal Consideration
Avoid forward-bias internal parasitic diode, VOUT to
RT9173/A regulators have internal thermal limiting
VCNTL, and VOUT to VIN, the VOUT should not be
circuitry designed to protect the device during
forced some voltage respect to ground on this pin
overload conditions. For continuous normal load
while the VCNTL or VIN is disappeared.
conditions
Consideration while designs the resistance of
however,
the
maximum
junction
temperature rating of 125°C must not be exceeded.
voltage divider
Higher continous currents or ambient temperature
Make sure the sinking current capability of pull-down
require additional heatsinking. Heat sinking to the IC
NMOS if the lower resistance was chosen so that the
package must consider the worst case power
voltage on REFEN is below 0.2V.
dissipation which may occur.
In addition to item 1, the capacitor and voltage divider
It should also be note that with the VCNTL equal to
form the low-pass filter. There are two reasons doing
5V, the point of thermal shutdown will be degraded by
this design; one is for output voltage soft-start while
approx. 20°C compared to the VCNTL equipped with
another is for noise immunity.
3.3V. It is highly recommended that to use the 3.3V
How to reduce power dissipation on Notebook PC
or the dual channel DDR SDRAM application?
In notebook application, using RichTek’s Patent
rail acted as the VCNTL so as to minimize the
thermal concern of the RT9173CS in the SOP-8
package.
“Distributed Bus Terminator Topology” with choosing
Layout Consideration
RichTek’s product is encouraged.
The RT9173CS regulator is packaged in plastic SOP8 package. This small footprint package is unable to
convectively dissipate the heat generated when the
regulator is operating at high current levels. In order
Distributed Bus Terminating Topology
to control die operating temperatures, the PC board
Terminator Resistor
R0
RT9173
VOUT
R1
R2
R3
REFEN
R4
R5
R6
RT9173
VOUT
R7
R8
R9
RN
RN1
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layout should allow for maximum possible copper
area at the VCNTL pins of the RT9173CS.
BUS(0)
BUS(1)
The multiple VCNTL pins on the SOP-8 package are
internally connected, but lowest thermal resistance
BUS(2)
will result if these pins are tightly connected on the
BUS(3)
PC board. This will also aid heat dissipation at high
BUS(4)
power levels.
BUS(5)
If the large copper around the IC is unavailable, a
BUS(6)
buried layer may be used as a heat spreader, Use
BUS(7)
vias to conduct the heat into the buried or backside of
PCB layer. The vias should be small enough to retain
BUS(8)
solder when the board is wave-soldered. (See Fig.6
BUS(9)
shown on next page).
BUS(N+1)
BUS(N)
DS9173/A-06 March 2002
RT9173/A
Use vias to conduct the heat into the
buried or backside of PCB layer .
RT9173CS (SOP-8)
The PCB heat sink copper area should be
solder-painted without masked. This
approaches a “best case” pad heat sink.
Fig. 6 Layout Consideration
To prevent this maximum junction temperature from
being exceeded, the appropriate power plane heat
sink MUST be used. Higher continuous currents or
ambient temperature require additional heatsinking.
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RT9173/A
Package Information
A
D
C
B
MARK
E
L1
L2
b2
b
e
U
V
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
D
9.652
10.668
0.380
0.420
B
1.143
1.676
0.045
0.066
E
8.128
9.652
0.320
0.380
A
4.064
4.826
0.160
0.190
C
1.143
1.397
0.045
0.055
U
6.223 Ref.
0.245 Ref.
V
7.620 Ref.
0.300 Ref.
L1
14.605
15.875
0.575
0.625
L2
2.286
2.794
0.090
0.110
b
0.660
0.914
0.026
0.036
b2
0.305
0.584
0.012
0.023
e
1.524
1.829
0.060
0.072
5-Lead TO-263 Plastic Surface Mount Package
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DS9173/A-06 March 2002
RT9173/A
H
A
M
J B
F
C
D
Symbol
I
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
M
0.406
1.270
0.016
0.050
F
1.194
1.346
0.047
0.053
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
H
0.178
0.254
0.007
0.010
8–Lead SOP Plastic Package
DS9173/A-06 March 2002
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RT9173/A
RICHTEK TECHNOLOGY CORP.
RICHTEK TECHNOLOGY CORP.
Headquarter
Taipei Office (Marketing)
6F, No. 35, Hsintai Road, Chupei City
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5510047 Fax: (8863)5537749
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
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DS9173/A-06 March 2002