CYPRESS CY2303SXCT

CY2303
Phase-Aligned Clock Multiplier
Phase-Aligned Clock Multiplier
Features
Functional Description
■
3-Multiplier configuration (1x, 2x, 4x ref)
■
10 MHz to 166.67 MHz operating range (reference input from
10 MHz to 41.67 MHz)
■
Phase alignment
■
80 ps typical period jitter
■
Output enable pin
■
3.3 V operation
■
5 V tolerant input
■
8-pin 150-mil small-outline integrated circuit (SOIC) package
■
Commercial temperature range
The CY2303 is a 3 output 3.3 V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows user to obtain 1x, 2x, and 4x REFIN output
frequencies on respective output pins.
The CY2303 has an on-chip PLL, which locks to an input clock
presented on the REFIN pin. The PLL feedback is internally
connected to the REF output. The input-to-output is guaranteed
to be less than 200 ps, and output-to-output skew is guaranteed
to be less than 200 ps.
Multiple CY2303 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
Logic Block Diagram
FBK
x1
REF
PLL
REFIN
x2
x4
REFx2
REFx4
OE
Cypress Semiconductor Corporation
Document Number: 38-07249 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 10, 2013
CY2303
Contents
Pin Configurations ........................................................... 3
Pin Description ................................................................. 3
Maximum Ratings ............................................................. 4
Operating Conditions ....................................................... 4
Electrical Characteristics ................................................. 4
Switching Characteristics ................................................ 5
Switching Waveforms ...................................................... 6
Test Circuits ...................................................................... 7
Ordering Information ........................................................ 8
Ordering Code Definitions ........................................... 8
Package Diagram .............................................................. 9
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Document Number: 38-07249 Rev. *F
Reference Documents .................................................... 10
Appendix: Silicon Errata for
the Zero Delay Clock Buffers, CY2303 ......................... 11
Part Numbers Affected .............................................. 11
CY2303 Errata Summary .......................................... 11
CY2303 Qualification Status of fixed silicon .............. 11
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Page 2 of 14
CY2303
Pin Configurations
Figure 1. 8-pin SOIC pinout
REF
GND
REFIN
N/C
1
2
3
4
8
7
6
5
OE
VDD
REFx4
REFx2
Pin Description
Pin
Signal [1]
1
REF
2
GND
3
REFIN
Description
REF output (1x reference input)
Ground
Input reference frequency, 5 V tolerant input
4
N/C
5
REFx2
No connect
6
REFx4
7
VDD
3.3 V supply
8
OE
Output enable (weak pull-up)
2x reference input
4x reference input
Note
1. Weak pull-down on all outputs.
Document Number: 38-07249 Rev. *F
Page 3 of 14
CY2303
Maximum Ratings
Storage temperature ............................... –65 °C to +150 °C
Supply voltage to ground potential ............. –0.5 V to +7.0 V
DC input voltage (except ref) ............. –0.5 V to VDD + 0.5 V
Junction temperature ................................................ 150 °C
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2000 V
DC input voltage REFIN .................................. –0.5 V to 7 V
Operating Conditions
Parameter
Description
Min
Max
Unit
3.0
3.6
V
Operating temperature (ambient temperature)
0
70
°C
Load capacitance, 10 MHz < FOUT < 133.33 MHz
–
18
pF
VDD
Supply voltage
TA
CL
Load capacitance, 133.33 MHz < FOUT < 166.67 MHz
–
12
pF
CIN
Input capacitance
–
7
pF
tPU
Power-up time for all VDD’s to reach minimum specified voltage (power ramps must
be monotonic)
0.05
50
ms
Min
Max
Unit
–
0.8
V
Electrical Characteristics
Parameter
Description
VIL
Input LOW voltage
VIH
Input HIGH voltage
IIL
Input LOW current
IIH
VOL
VOH
Output HIGH voltage
[2]
IDD
Supply current
Test Conditions
2.0
–
V
VIN = 0 V
–
100
A
Input HIGH current
VIN = VDD
–
50
A
Output LOW voltage [2]
IOL = 8 mA
–
0.4
V
2.4
–
V
Unloaded outputs, REFIN = 41.67 MHz
–
45
mA
Unloaded outputs, REFIN = 25 MHz
–
32
mA
Unloaded outputs, REFIN = 10 MHz
–
18
mA
IOH = –8 mA
Note
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
Document Number: 38-07249 Rev. *F
Page 4 of 14
CY2303
Switching Characteristics
Parameter
1/t1
Name
Output frequency
Duty cycle
t3
Rise time
[3]
= t2 t1
[3]
[3]
Test Conditions
Min
Typ
Max
Unit
18-pF load
10
–
133.33
MHz
12-pF load
–
–
166.67
MHz
Measured at VDD/2
40
50
60
%
Measured between 0.8 V and 2.0 V
–
–
1.20
ns
Measured between 0.8 V and 2.0 V
–
–
1.20
ns
All outputs equally loaded
Measured at VDD/2
–
–
200
ps
t4
Fall time
t5
Output to output skew on rising
edges [3]
t6
Delay, REFIN rising edge to REF Measured at VDD/2 from REFIN to
rising edge [3]
any output
–
–
200
ps
t7
Device to device skew [3]
Measured at VDD/2 on the REF pin
of the device (pin 1)
–
–
400
ps
tJ
Period jitter [3]
Measured at FOUT < 133.33 MHz,
loaded outputs, 18-pF load
–
80
175
ps
tLOCK
PLL lock time [3]
Stable power supply, valid clocks
presented on REFIN
–
–
1.0
ms
Note
3. All parameters are specified with loaded outputs.
Document Number: 38-07249 Rev. *F
Page 5 of 14
CY2303
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
VDD/2
Figure 3. All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Figure 4. Output to Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Figure 5. Input to Output Propagation Delay
INPUT
VDD/2
VDD/2
FBK
t6
Figure 6. Device to Device Skew
FBK, Device 1
VDD/2
VDD/2
FBK, Device 2
t7
Document Number: 38-07249 Rev. *F
Page 6 of 14
CY2303
Test Circuits
Figure 7. Test Circuit #1
VDD
0.1 F
OUTPUTS
CLK OUT
C LOAD
GND
Document Number: 38-07249 Rev. *F
Page 7 of 14
CY2303
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY2303SXC
8-pin SOIC (150 Mils)
Commercial (0 to 70 °C)
CY2303SXCT
8-pin SOIC (150 Mils) - Tape and Reel
Commercial (0 to 70 °C)
Ordering Code Definitions
CY 2303 S
X
C
T
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
C = Commercial
X = Pb-free
Package Type: S = 8-pin SOIC
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07249 Rev. *F
Page 8 of 14
CY2303
Package Diagram
Figure 8. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *F
Document Number: 38-07249 Rev. *F
Page 9 of 14
CY2303
Acronyms
Document Conventions
Acronym
Units of Measure
Description
FBK
Feedback
OE
Output Enable
°C
degrees Celsius
PLL
Phase Locked Loop
Hz
hertz
REFIN
Reference Input
kHz
kilohertz
MHz
megahertz
µA
microampere
µF
microfarad
Symbol
Unit of Measure
µs
microsecond
µV
microvolt
mA
milliampere
mm
millimeter
ms
millisecond
mV
millivolt
ns
nanosecond
pA
picoampere
pF
picofarad
ps
picosecond
V
volt
Reference Documents
Reference documents are available through your local Cypress sales representative. You can also direct your requests to
[email protected]
Document Number
NA
Document Title
NA
Document Number: 38-07249 Rev. *F
Description
NA
Page 10 of 14
CY2303
Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2303
This section describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to the
families CY2303. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Table 1. Part Numbers Affected
Part Number
Device Variants
CY2303SXC
All Variants
CY2303SXCT
All Variants
CY2303 Errata Summary
Items
Part Number
Fix Status
Start up lock time issue [CY2303]
All
Silicon fixed. New silicon available from WW 10
of 2013
CY2303 Qualification Status of fixed silicon
Product Status: In production
Qualification report last updated on 11/27/2012
http://www.cypress.com/?rID=72595
1. Start up lock time issue
■
Problem Definition
Output of CY2304 fails to locks within 1 ms upon power up (as per datasheet spec)
■
Parameters Affected
PLL lock time
■
Trigger Condition(s)
Start up
■
Scope of Impact
It can impact the performance of system and its throughput
■
Workaround
Apply reference input (RefClk) before power up (VDD). If RefClk is applied after power up, noise gets coupled on the output and
propagates back to the PLL causing it to take higher time to acquire lock. If reference input is present during power up, noise will
not propagate to the PLL and device will start up normally without problems.
■
Fix Status
This issue is due to design marginality. Two minor design modifications have been made to address this problem.
a. Addition of VCO bias detector block as shown in the following figure keeps comparator power down till VCO bias is present and
thereby eliminating the propagation of noise to feedback.
b. Bias generator enhancement for successful initialization.
Document Number: 38-07249 Rev. *F
Page 11 of 14
CY2303
Document Number: 38-07249 Rev. *F
Page 12 of 14
CY2303
Document History Page
Document Title: CY2303, Phase-Aligned Clock Multiplier
Document Number: 38-07249
Rev.
ECN
Orig. of
Change
Submission
Date
**
110514
SZV
01/07/02
Description of Change
Change from Spec number: 38-01036 to 38-07249
*A
121852
RBI
12/14/02
Power up requirements added to Operating Conditions Information
*B
390413
RGL
08/10/05
Added Lead-free devices
Added typical values for jitter
*C
2568533
AESA
09/23/08
Updated template.
Removed part number CY2303SC and CY2303SI from Selector Guide table.
Removed part number CY2303SC, CY2303SCT, CY2303SI, and CY2303SIT.
*D
2897294
KVM
03/22/10
Removed part numbers CY2303SXI and CY2303SXIT from ordering
information table and related industrial temperature references.
Updated package diagram.
Updated copyright section.
*E
3026183
BASH
09/01/2010
Updated tJ from 80 ps to 80 ps in Switching Characteristics on page 3.
Ordering Code Definitions added on page 6.
Acronyms, Reference Documents and Document Conventions added on page
7.
*F
4018186
CINM
06/10/2013
Updated Package Diagram:
spec 51-85066 – Changed revision from *D to *F.
Added Appendix: Silicon Errata for the Zero Delay Clock Buffers, CY2303.
Document Number: 38-07249 Rev. *F
Page 13 of 14
CY2303
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07249 Rev. *F
Revised June 10, 2013
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