EM78P143 8-Bit Microprocessor with OTP ROM Product Specification DOC. VERSION 1.5 ELAN MICROELECTRONICS CORP. March 2011 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2008~2011 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Hong Kong: USA: No. 12, Innovation 1 Road Hsinchu Science Park Hsinchu, TAIWAN 30076 Tel: +886 3 563-9977 Fax: +886 3 563-9966 [email protected] http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 Elan Information Technology Group (U.S.A.) PO Box 601 Cupertino, CA 95015 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8225 Korea: Shenzhen: Shanghai: Elan Korea Electronics Company, Ltd. Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 301 Dong-A Building 632 Kojan-Dong, Namdong-ku Incheon City, KOREA Tel: +82 32 814-7730 Fax: +82 32 813-7730 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 [email protected] 3F, Building #13 No. 116, Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 [email protected] Headquarters: st Contents Contents 1 General Description .................................................................................................. 1 2 Features ..................................................................................................................... 1 3 Pin Assignment ......................................................................................................... 2 4 Pin Description.......................................................................................................... 3 4.1 EM78P143MS10J/S ........................................................................................... 3 4.2 EM78P143SO14J............................................................................................... 4 5 Block Diagram ........................................................................................................... 5 6 Functional Description ............................................................................................. 6 6.1 Operational Registers......................................................................................... 6 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.2 R0 (Indirect Address Register) ...........................................................................6 R1 (Time Clock/Counter).....................................................................................6 R2 (Program Counter) and Stack........................................................................6 6.1.3.1 Data Memory Configuration .................................................................8 R3 (Status Register)............................................................................................9 R4 (RAM Select Register)...................................................................................9 R5 (Port 5)...........................................................................................................9 R6 (LVD Control Register) ................................................................................10 R7 (MCSR: Miscellaneous Control and Status Register) .................................11 R8 (AISR: ADC Input Select Register)..............................................................12 R9 (ADCON: ADC Control Register).................................................................13 RA (ADOC: ADC Offset Calibration Register)...................................................15 RB (ADDATAH: Converted Value of ADC) ........................................................15 RC (ADDATAL: ADC Converted Value) ............................................................15 RD (TBLP: LSB of Table Pointer Register for Instruction TBRD) .....................16 RE (TBHP: MSB of Table Pointer Register for Instruction TBRD) ....................16 RF (Interrupt Status Register) ...........................................................................16 R10 ~ R3F.........................................................................................................17 Special Purpose Registers ............................................................................... 17 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 A (Accumulator).................................................................................................17 CONT (Control Register)...................................................................................17 IOC50 (I/O Port Control Registe“) .....................................................................18 IOC60 (Pull-high Control Register) ...................................................................18 IOC70 (Pull-down Control Register) .................................................................19 IOC80 (Open-Drain Control Register)...............................................................19 IOC90 (CMPCON: Comparator Control Register) ............................................20 IOCA0 ~ IOCC0: Reserved...............................................................................21 IOCD0 (Option Control Bit I) .............................................................................21 IOCE0 (Option Control Bits II)...........................................................................22 Product Specification (V1.5) 03.15.2011 • iii Contents 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 6.2.22 6.3 TCC/WDT and Prescaler.................................................................................. 29 6.4 I/O Ports ........................................................................................................... 30 6.4.1 6.5 Usage of Port 5 Input Change Wake-up/Interrupt Function..............................33 Reset and Wake-up.......................................................................................... 33 6.5.1 6.5.2 Reset and Wake-up Operation..........................................................................33 6.5.1.1 Summary of Wake-up and Interrupt Modes Operation ......................36 6.5.1.2 Summary of Wake-up and Interrupt Modes Operation ......................37 6.5.1.3 Register Initial Values after Reset ......................................................39 6.5.1.4 Controller Reset Block Diagram.........................................................43 T and P Status under Status Register ...............................................................44 6.6 Interrupt ............................................................................................................ 44 6.7 Analog-to-Digital Converter (ADC) ................................................................... 47 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.8 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ...............................47 6.7.1.1 R8 (AISR: ADC Input Select Register) ...............................................47 6.7.1.2 R9 (ADCON: AD Control Register) ....................................................48 6.7.1.3 RA (ADOC: AD Offset Calibration Register).......................................50 ADC Data Register (ADDATAH/RB, ADDATAL/RC) .........................................51 ADC Sampling Time..........................................................................................51 AD Conversion Time .........................................................................................51 ADC Operation during Sleep Mode ..................................................................52 Programming Process/Considerations .............................................................52 6.7.6.1 Programming Process........................................................................52 6.7.6.2 Sample Demo Progra.........................................................................53 Dual Sets of PWM (Pulse Width Modulation) ................................................... 55 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 iv • IOCF0 (Interrupt Mask Register).......................................................................23 IOC51 (PWMCON: PWM Control Register)......................................................24 IOC61 (TMRCON: Timer Control Register) ......................................................25 IOC71 (PRD1: PWM1 Time Period)..................................................................26 IOC81 (PRD2: PWM2 Time Period)..................................................................26 IOC91 (DT1: PWM1 Duty Cycle) ......................................................................26 IOCA1 (DT2:PWM2 Duty Cycle) .......................................................................26 IOCB1 (TMR1: PWM1 Timer) ...........................................................................26 IOCC1 (TMR2: PWM2 Timer) ...........................................................................26 IOCD1 (Wake-up Control Register) ..................................................................27 IOCE1 (WDT Control Register).........................................................................27 IOCF1: Reserve ................................................................................................28 Overview ...........................................................................................................55 Increment Timer Counter (TMRX: TMR1 or TMR2)..........................................56 PWM Time Period (PRDX: PRD1 or PRD2) .....................................................56 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2).................................57 Comparator X ....................................................................................................57 Product Specification (V1.5) 03.15.2011 Contents 6.8.6 6.8.7 6.9 PWM Programming Process/Steps...................................................................57 PWM Cascade Mode ........................................................................................58 Timer ................................................................................................................ 58 6.9.1 6.9.2 6.9.3 6.9.4 6.9.5 Overview ...........................................................................................................58 Functional Description.......................................................................................59 Programming the Related Registers.................................................................60 Timer Programming Process/Steps ..................................................................60 Timer Cascade Mode ........................................................................................60 6.10 Comparator ...................................................................................................... 61 6.10.1 6.10.2 6.10.3 6.10.4 Comparator Reference Signal...........................................................................61 Comparator Output............................................................................................63 Comparator Interrupt.........................................................................................64 Wake-up from Sleep Mode................................................................................64 6.11 Oscillator .......................................................................................................... 65 6.11.1 6.11.2 6.11.3 6.11.4 Oscillator Modes ...............................................................................................65 Crystal Oscillator/Ceramic Resonators (Crystal) ..............................................65 External RC Oscillator Mode.............................................................................66 Internal RC Oscillator Mode ..............................................................................67 6.12 Power-on Considerations ................................................................................. 68 6.12.1 Programmable WDT Time-out Period ...............................................................68 6.12.2 External Power-on Reset Circuit .......................................................................68 6.12.2 Residual Voltage Protection ..............................................................................69 6.13 Code Option ..................................................................................................... 70 6.13.1 Code Option Register (Word 0).........................................................................70 6.13.2 Code Option Register (Word 1).........................................................................71 6.13.3 Customer ID Register (Word 2).........................................................................72 6.14 Low Voltage Detector ....................................................................................... 72 6.14.1 Low Voltage Reset (LVR) ..................................................................................73 6.14.2 Low Voltage Detector (LVD)..............................................................................73 6.14.2.1 R6 (LVD Control Register)..................................................................73 6.14.3 Programming Process.......................................................................................74 6.15 Instruction Set ...................................................................................................76 7 Absolute Maximum Ratings ................................................................................... 78 8 DC Electrical Characteristics ................................................................................. 78 8.1 AD Converter Characteristics........................................................................... 80 8.2 Comparator Characteristics.............................................................................. 81 9 AC Electrical Characteristics ................................................................................. 82 10 Timing Diagrams ..................................................................................................... 83 Product Specification (V1.5) 03.15.2011 •v Contents APPENDIX A Package Type........................................................................................................... 84 B Packaging Configuration........................................................................................ 84 C How to Use the ICE 143 for EM78P143.................................................................. 86 C.1 Code Option Pin Selection with JP1 and JP2 .................................................. 86 C.2 DIP Switch (S1 and S2) Setting........................................................................ 87 C.3 ICE 143 ICE Cable Connector (JP3) Pin Assignment ...................................... 88 C.4 ICE 143 ICE Cable to Target Pin Assignment .................................................. 89 Specification Revision History Doc. Version Revision Description Date 0.9 Preliminary version 2008/10/25 1.0 Initial released version 2009/03/12 1. Added EM78P143MS10J/S package type. 1.1 2. Modified Section 6.5.1.3 Register Initial Values After Reset. 2009/12/30 3. Deleted IOCB0 and IOCC0 registers. 4. Modified Absolute Maximum Ratings. vi • 1.2 Added EM78P143SO14J/S package type 2010/08/16 1.3 Modified EM78P143SO14J package type 2010/08/30 1.4 Modified EM78P143SO14J pin assignment 2010/11/01 1.5 Added LCALL, LJMP instruction in Section 6.15 2011/03/15 Product Specification (V1.5) 03.15.2011 EM78P143 8-Bit Microprocessor with OTP ROM 1 General Description The EM78P143 is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. It has an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s code. Three Code option words are also available to meet user’s requirements. With its enhanced OTP-ROM feature, the EM78P143 provides a convenient way of developing and verifying user’s programs. Moreover, this MCU offers the advantages of easy and effective program updates with the use of ELAN development and programming tools. User can also avail of ELAN Writer to easily program their development code. 2 Features CPU configuration • 2K×13 bits on-chip ROM • 80×8 bits on-chip registers (SRAM) • 8-level stacks for subroutine nesting • 4 programmable level voltage detector (LVD): 4.5V, 4.0V, 3.3V, 2.2V • 3 programmable level voltage reset (LVR): 4.0V, 3.5V, 2.7V • Less than 1.5 mA at 5V/4MHz • Typical 15 μA, at 3V/32kHz • Typical 2 μA, during Sleep mode I/O port configuration • 1 bidirectional I/O ports • Wake-up port: P5 • 7 Programmable pull-down I/O pins • 7 programmable pull-high I/O pins • 7 programmable open-drain I/O pins • External interrupt: P52 Operating voltage range • Operating voltage: 2.1V~5.5V (Commercial) • Operating temperature: 0°C ~70°C (Commercial) Operating frequency range • Crystal mode: DC~16MHz/2clks @ 4.5V; DC~8MHz/2clks @ 3V DC~4MHz/2clks @ 2.1V • ERC mode: DC~16 MHz/2clks @ 4.5V DC~12 MHz/2clks @ 4V DC~4 MHz/2clks @ 2.1V • IRC mode: Oscillation mode: 4 MHz, 8 MHz, 16 MHz, 455kHz Drift Rate Internal RC Frequency 4 MHz 8 MHz 16 MHz 455kHz Temperature (0°C~70°C) ± 3% ± 3% ± 3% ± 3% Voltage Process (2.3V~5.5V) ± 5% ± 5% ± 5% ± 5% ± 3% ± 3% ± 3% ± 3% Total ± 11% ± 11% ± 11% ± 11% All the four main frequencies can be trimmed by programming with four calibrated bits in the ICE143 Simulator. OTP is auto trimmed by ELAN Writer. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) Peripheral configuration • 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt • 7-channel Analog-to-Digital Converter with 10-bit resolution in Vref mode • Two Pulse Width Modulation (PWM) with 8-bit resolution, each provides 8-bit real time clock/counter function and supports 16-bit cascaded mode from these two independent ones • One pair of comparators (Offset voltage: 5mV, max offset voltage: 10mV) • Power-down (Sleep) mode • High EFT immunity Seven available interrupts: • TCC overflow interrupt • Input-port status changed interrupt (wake-up from Sleep mode) • External interrupt • ADC completion interrupt • PWM period match completion • Comparators status change interrupt • Low voltage detector interrupt Programmable free running Watchdog Timer • Two clocks per instruction cycle • Watchdog timer 16.5ms ± 30% in Vdd=5V at 25°C (WDTPS=1 in Option pin) • Watchdog timer 18ms ± 30% in Vdd=3V at 25°C (WDTPS=1 in Option pin) • Watchdog timer 4.2ms ± 30% in Vdd=5V at 25°C (WDTPS=0 in Option pin) • Watchdog timer 4.5ms ± 30% in Vdd=3V at 25°C (WDTPS=0 in Option pin) Package type: • 10-pin MSOP 118 mil : EM78P143MS10J/S • 14-pin SOP 150 mil : EM78P143SO14J Note: These are all Green products which do not contain hazardous substances. •1 EM78P143 8-Bit Microprocessor with OTP ROM 3 Pin Assignment 1 VSS 2 P56/AD6/PWM2 3 VDD 4 P55/AD5/CO/TCC 5 10 EM78P143 MS10J/S P57/RESET 9 P51/OSCO/AD1/PWM1 P50/OSCI/AD0 8 P52/AD2/INT 7 P53/AD3/CIN+ 6 P54/AD4/CIN-/Vref Figure 3-1 EM78P143MS10J/S Pin Assignment 1 NC 2 P52/AD2/INT 3 P50/OSCI/AD0 4 P51/OSCO/AD1/PWM1 5 P57/RESET 6 VSS 7 EM78P143SO14J NC 14 NC 13 NC 12 P53/AD3/CIN+ 11 P54/AD4/CIN-/Vref 10 P55/AD5/CO/TCC 9 VDD 8 P56/AD6/PWM2 Figure 3-1 EM78P143SO14J Pin Assignment 2• Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 4 Pin Description 4.1 EM78P143MS10J/S Symbol Pin No. Type 5,3,1,10 7,9,8,6 I/O OSCI / ERCin 9 I OSCO/RCOUT 10 O TCC 5 I Real time clock/counter, Schmitt trigger input pin. Must be tied to VDD or VSS if not in use. /RESET 1 I Schmitt trigger input pin. If this pin remains at logic low, the controller is reset. P50~P57 Function Bidirectional 8-bit input/output pins P50~P56 can be used as pull-high, pull-down, and as open-drain by software programming. External clock crystal resonator oscillator input pin External RC oscillator clock input pin Clock output from crystal oscillator Clock output from internal RC oscillator P54 can act as CIN- of a comparator CIN-, CIN+CO 6, 7, 5 I/O P53 can act as CIN+ of a comparator P55 can act as CO of a comparator VREF 6 9,10,8,7 I P54 can be used as external reference for ADC. I/O P50~P56 can be used as 7-channel 10-bit resolution A/D converter 8 I P52 can be used as external interrupt pin triggered by a falling edge. 10, 3 O P51 and P56 can be used as Pulse Width Modulation output VDD 4 – Power supply VSS 2 – Ground ADC0~ADC6 /INT PWM1/PWM2 6,5,3 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) •3 EM78P143 8-Bit Microprocessor with OTP ROM 4.2 EM78P143SO14J Symbol Pin No. Type Function Bidirectional 8-bit input/output pins 4,5,3,12 11,10,8, 6 I/O OSCI / ERCin 4 I OSCO/RCOUT 5 O TCC 10 I Real time clock/counter, Schmitt trigger input pin. Must be tied to VDD or VSS if not in use. /RESET 6 I Schmitt trigger input pin. If this pin remains at logic low, the controller is reset. P50~P57 P50~P56 can be used as pull-high, pull-down, and as open-drain by software programming. External clock crystal resonator oscillator input pin External RC oscillator clock input pin Clock output from crystal oscillator Clock output from internal RC oscillator P54 can act as CIN- of a comparator 11, 12, CIN-, CIN+, CO 10 I/O P53 can act as CIN+ of a comparator P55 can act as CO of a comparator VREF 4,5,3,12 I P54 can be used as external reference for ADC. I/O P50~P56 can be used as 7-channel 10-bit resolution A/D converter 3 I P52 can be used as external interrupt pin triggered by a falling edge. 5, 8 O P51 and P56 can be used as Pulse Width Modulation output VDD 9 – Power supply VSS 7 – Ground - Not used ADC0~ADC6 /INT PWM1/PWM2 NC 4• 11 11,10,8 1, 2, 13 14 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 5 Block Diagram Figure 5-1 EM78P143 Functional Block Diagram Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) •5 EM78P143 8-Bit Microprocessor with OTP ROM 6 Functional Description 6.1 Operational Registers 6.1.1 R0 (Indirect Address Register) R0 is not a physically implemented register. It is used as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4). 6.1.2 R1 (Time Clock/Counter) Incremented by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers The TCC prescaler counter (CONT) is assigned to TCC The contents of the CONT register is cleared − • when a value is written to the TCC register • when a value is written to the TCC prescaler bits (Bits 3, 2, 1, & 0 of the CONT register) • during power-on reset, /RESET, or WDT time out reset 6.1.3 R2 (Program Counter) and Stack A10 Reset Vector A9 ~ A0 Hardware Interrupt Vector 00 : PAGE0 0000~03FF 01 : PAGE1 0400~07FF Stack Level 1 Stack Level 2 Stack Level 3 User Memory Space CALL RET RETL RETI 000H 003H ~ 01BH On-chip Program Memory Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 7FFH Stack Level 8 Figure 6-1 Program Counter Organization 6• R2 and hardware stacks are 11-bit wide. The structure is depicted in the table under Section 6.1.3.1, Data Memory Configuration. The configuration structure generates 2K×13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM The contents of R2 are all set to “0”s when a reset condition occurs. “JMP” instruction allows direct loading of the lower 10 program counter bits. Thus, “JMP” allows the PC to jump to any location within a page. “CALL” instruction loads the lower 10 bits of the PC and PC+1 are pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page. “LJMP” instruction allows direct loading of the 11-bit program counter bit (A0~A10). Therefore, “LJMP” allows PC to jump any location within 2K. “LCALL” instruction loads the program counter bits (A0~A10) and PC+1 are pushed onto the stack. Thus, the subroutine entry address can be located anywhere within 2K. “RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents of the top of stack. “ADD R2, A” allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. “MOV R2, A” allows loading of an address from the “A” register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except “ADD R2,A”) that is written to R2 (e.g., “MOV R2, A”, “BC R2, 6”, etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP” instructions. The “LCALL” and ”LJMP” instructions need two instruction cycles. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) •7 EM78P143 8-Bit Microprocessor with OTP ROM 6.1.3.1 Data Memory Configuration Address IOCX0 PAGE Registers IOCX1 PAGE registers 00 R0 (Indirect Addressing Register) Reserve Reserve 01 R1 (Time Clock Counter) Reserve Reserve 02 R2 (Program Counter) Reserve Reserve 03 R3 (Status Register) Reserve Reserve 04 R4 (RAM Select Register) Reserve Reserve IOC51 05 R5 (Port 5) IOC50 (I/O Port Control Register) 06 R6 (LVD Control Register) IOC60 (Pull-high Control Register) IOC61 07 R7 (MCSR) IOC70 (Pull-down Control Register) IOC71 08 R8 (ADC Input Select Register 09 R9 (ADC Control Register) 0A RA 0B RB 0C RC 0D RD 0E RE 0F RF 10 : 1F 20 : 3F 8• R PAGE registers IOC80 (Open-drain Control Register) IOC90 (Comparator Control Register) (ADC Offset Calibration Register) (The converted value Bit 9~Bit 2 of ADDATAH) (The converted value Bit 1~Bit 0 of ADDATAL) (THLP: LSB of Table Point Register) (TBHP: MSB of Table Point Register) (Interrupt Status Register) IOCF0 (Interrupt Mask Register 1) IOC81 (PWMCON : PWM Control Register) (TMRCON : Timer Control Register) (PRD1 : PWM1 Time Period) (PRD2 : PWM2 Time Period) IOC91 (DT1 : PWM1 Duty Cycle) IOCA0 Reserve IOCA1 (DT2 : PWM2 Duty Cycle) IOCB0 Reserve IOCB1 (TMR1 : PMW1 Timer) IOCC0 Reserve IOCC1 (TMR2 : PWM2 Timer) IOCD0 (Code Option Control Register) IOCE0 (Code Option Control Register) IOCD1 (Wake-up Control Register) IOCE1 (WDT Control Register) Reserve General Registers Bank 0 Bank 1 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RST IOCS - T P Z DC C Bit 7 (RST): Bit of reset type Set to “1” if wake-up from Sleep mode on pin change, comparator status change, or AD conversion completed. Set to “0” if wake-up from other reset types. Bit 6 (IOCS): Select the Segment of IO control register 0: Segment 0 (IOC50 ~ IOCF0) selected 1: Segment 1 (IOC51 ~ IOCF1) selected Bit 5: Not used (reserved) Bit 4 (T): Time-out bit. Set to “1” by the “SLEP” and “WDTC” commands or during power-on and reset to “0” by WDT time-out. For further details see Section 6.5.2, T and P Status under Status Register. Bit 3 (P): Power-down bit. Set to “1” during power-on or by a “WDTC” command and reset to “0” by a “SLEP” command (see Section 6.5.2, T and P status under Status Register for more details). NOTE Bit 4 and Bit 3 (T and P) are read only. Bit 2 (Z): Zero flag. Set to “1” if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 6.1.5 R4 (RAM Select Register) Bit 7: Not used bit. Set to ‘0’ all the time. Bit 6: Used to select Bank 0 or Bank 1 of the register Bits 5~0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing mode (see table under Section 6.1.3.1, Data Memory Configuration). 6.1.6 R5 (Port 5) R5 are I/O registers. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) •9 EM78P143 8-Bit Microprocessor with OTP ROM 6.1.7 R6 (LVD Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ‘0’ LVDIF /LVD LVDIE LVDWE LVDEN LVD1 LVD0 Bit 7: Not used bit. Read as ‘0’ all the time. Bit 6 (LVDIF): Low Voltage Detector interrupt flag. LVDIF is reset to “0” by software. Bit 5 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit is cleared. 0: Low voltage is detected 1: Low voltage is not detected or LVD function is disabled Bit 4 (LVDIE): Low voltage detector interrupt enable bit 0: Disable low voltage detector interrupt 1: Enable low voltage detector interrupt NOTE R6<4> register is both readable and writeable. Individual interrupt is enabled by setting its associated control bit in R6<4> to “1”. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-6b (Interrupt Input Circuit) in Section 6.6 (Interrupt) Bit 3 (LVDWE): Low voltage detector wake-up enable bit 0: Disable Low voltage detect wake-up 1: Enable Low voltage detect wake-up Bit 2 (LVDEN): Low voltage detector enable bit 0: Disable Low voltage detector function 1: Enable Low voltage detector function Bits 1 ~0 (LVD1~LVD0): Low voltage detector level bits 10 • LVDEN LVD1, LVD0 1 11 1 10 1 01 1 00 0 ×× LVD Voltage Interrupt Level /LVD Vdd ≤ 2.2V 0 Vdd > 2.2V 1 Vdd ≤ 3.3V 0 Vdd > 3.3V 1 Vdd ≤ 4.0V 0 Vdd > 4.0V 1 Vdd ≤ 4.5V 0 Vdd > 4.5V 1 N/A 1 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.1.8 R7 (MCSR: Miscellaneous Control and Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” “0” CPUS IDLE EIS TCCSC TMR1SC TMR2SC Bits 7~6: Not used bit. Read as ‘0’ all the time. Bit 5 (CPUS): CPU Oscillator Source Select 0: Sub-oscillator (fs) 1: Main oscillator (fosc) When CPUS=0, the CPU oscillator selects the sub-oscillator and the main oscillator is stopped. Bit 4 (IDLE): Idle Mode Enable Bit. This bit will determine as to which mode to proceed to after SLEP instruction. 0: IDLE=”0”+SLEP instruction Æ Sleep mode 1: IDLE=”1”+SLEP instruction Æ Idle mode CPU Operation Mode Figure 6-2 CPU Operation Mode Bit 3 (EIS): Control bit is used to define the P52 (/INT) pin function 0: P52, normal I/O pin 1: /INT, external interrupt pin. In this case, the I/O control bit of P52 (Bit 2 of IOC50) must be set to "1". NOTE When EIS is ”0," the path of /INT is masked. When EIS “s "1”, the status of the /INT pin can also be read through reading Port 5 (R5). Refer to Figure 6-4c (I/O Port and I/O Control Register Circuit for P52 (/INT)) in Section 6.4 (I/O Ports). EIS is both readable and writable. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 11 EM78P143 8-Bit Microprocessor with OTP ROM Bit 2 (TCCSC): TCC clock source select 0: Fs: Sub-frequency for WDT internal RC time base 1: Fm: Main-oscillator clock Bit 1 (TMR1SC): TMR1 clock source select 0: Fs: Sub frequency for WDT internal RC time base 1: Fm: Main-oscillator clock Bit 0 (TMR2SC): TMR2 clock source select 0: Fs: Sub frequency for WDT internal RC time base 1: Fm: Main-oscillator clock 6.1.9 R8 (AISR: ADC Input Select Register) The AISR register individually defines the Port 5 pins as analog input or as digital I/O. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ”0” ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bit 7: Not used bit. Read as ‘0’ all the time. Bit 6 (ADE6): AD converter enable bit of P56 pin 0: Disable AD6, P56 functions as I/O pin 1: Enable AD6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P55 pin 0: Disable AD5, P55 functions as I/O pin 1: Enable AD5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P54 pin 0: Disable AD4, P54 functions as I/O pin 1: Enable AD4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0: Disable AD3, P53 functions as I/O pin 1: Enable AD3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0: Disable AD2, P52 functions as I/O pin 1: Enable AD2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0: Disable AD1, P51 functions as I/O pin 1: Enable AD1 to function as analog input pin 12 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Bit 0 (ADE0): AD converter enable bit of P50 pin 0: Disable AD0, P50 functions as I/O pin 1: Enable AD0 to function as analog input pin NOTE The TCC, CO and AD5 of the P55/AD5/CO/TCC pins cannot be used at the same time. The P55/AD5/CO/TCC pin priority is as follows: P55/AD5/CO/TCC Priority Highest High Medium Low TCC CO AD5 P55 The P50/AD0/OSCI pin cannot be applied to OSCI and AD0 at the same time. The P50/AD0/OSCI pin priority is as follows: P50/AD0/OSCI 6.1.10 High Medium Low OSCI AD0 P50 R9 (ADCON: ADC Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Bit 7 (VREFS): The input source of the VREFS of the ADC 0: The VREFS of the ADC is connected to Vdd (default value), and the P54/VREFS pin carries out the P54 function. 1: The VREFS of the ADC is connected to P54/VREFS. NOTE The P54/AD4/CIN-/VERFS pin cannot be applied to VERFS, CIN- and AD4 at the same time. The P54/AD4/CIN-/VERFS pin priority is as follows: P54/AD4/CIN-/VREF Pin Priority Highest High Medium Low VREF CIN- AD4 P54 Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of ADC oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 13 EM78P143 8-Bit Microprocessor with OTP ROM CKR1: CKR0 Operation Mode Max. Operation Frequency 00 Fosc/16 4 MHz 01 Fosc/4 1 MHz 10 Fosc/64 16 MHz 11 Fosc/8 2 MHz Bit 4 (ADRUN): ADC starts to RUN 0: Reset upon completion of the conversion. This bit cannot be reset through software. 1: An AD conversion is started. This bit can be set by software. Bit 3 (/ADPD): ADC Power-down mode 0: Switch off the resistor reference to save power even if the CPU is running 1: ADC is running NOTE The ADPD bit must be enabled first before enabling the ADRUN bit. The program process is shown in Section 6.7.6 (Programming Process/Considerations). Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select 000 = ADIN0/P50 001 = ADIN1/P51 010 = ADIN2/P52 011 = ADIN3/P53 100 = ADIN4/P54 101 = ADIN5/P55 110 = ADIN6/P56 111 = not used These bits can only be changed when the ADIF bit (see Section 6.1.16, RF (Interrupt Status Register)) and the ADRUN bit are both Low. 14 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.1.11 RA (ADOC: ADC Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CALI SIGN VOF[2] VOF[1] VOF[0] “0” “0” “0” Bit 7 (CALI): Calibration enable bit for ADC offset 0: Disable Calibration 1: Enable Calibration Bit 6 (SIGN): Polarity bit of offset voltage 0: Negative voltage 1: Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits VOF[2] VOF[1] VOF[0] EM78P143 0 0 0 0 LSB 0 0 1 1 LSB 0 0 1 1 0 1 2 LSB 3 LSB 1 0 0 4 LSB 1 0 1 5 LSB 1 1 0 6 LSB 1 1 1 7 LSB Bit 2 ~ Bit 0: Not used bit. Read as ‘0’ all the time. 6.1.12 RB (ADDATAH: Converted Value of ADC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Bits 7~0 (ADD9~ADD2): AD High 8-Bit Data Buffer for 10-Bit resolution format ADC. When the AD conversion is completed, the result is loaded into the ADDATAH. The ADRUN bit is cleared, and the ADIF is set (see Section 6.1.16, RF (Interrupt Status Register)). RB is read only. 6.1.13 RC (ADDATAL: ADC Converted Value) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” “0” “0” “0” “0” “0” ADD1 ADD0 Bits 1~0 (ADD1~ADD0): AD Low 2-Bit Data Buffer for 10 Bit resolution format ADC. When the AD conversion is completed, the result is loaded into the ADDATAL. The ADRUN bit is cleared and the ADIF is set (see Section 6.1.16, RF (Interrupt Status Register)). RC is read only. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 15 EM78P143 8-Bit Microprocessor with OTP ROM 6.1.14 RD (TBLP: LSB of Table Pointer Register for Instruction TBRD) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBit 7 RBit 6 RBit 5 RBit 4 RBit 3 RBit 2 RBit 1 RBit 0 Bits 7~0: LSB of Table Point Address Bits 7~0 6.1.15 RE (TBHP: MSB of Table Pointer Register for Instruction TBRD) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLB “0” “0” “0” “0” “0” RBit 9 RBit 8 Bit 7 (MLB): Take MSB or LSB at machine code. 0: LSB (default) 1: MSB Bits 6 ~ 3: Not used bit. Read as ‘0’ all the time. Bits 2 ~ 0: MSB of Table Point Address Bits 10~8. 6.1.16 RF (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMPIF ”0” PWM2IF PWM1IF ADIF EXIF ICIF TCIF NOTE “1” means there is an interrupt request. “0” means no interrupt occurs. RF can be cleared by instruction but cannot be set. IOCF0 is the interrupt mask register. Reading RF will result “o "Logic AND" of RF and IOCF0. Bit 7 (CMPIF): interrupt flag. Set when a change occurs in the Comparator output. Reset by software. Bit 6: Not used bit. Read as ‘0’ all the time. Bit 5 (PWM2IF): PWM2 (Pulse Width Modulation) interrupt flag. Set when a selected duration is reached. Reset by software. Bit 4 (PWM1IF): PWM1 (Pulse Width Modulation) interrupt flag. Set when a selected duration is reached. Reset by software. Bit 3 (ADIF): Interrupt flag for analog to digital conversion. Set when AD conversion is completed. Reset by software. Bit 2 (EXIF): External interrupt flag. Set by a falling edge on the /INT pin. Reset by software. 16 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Bit 1 (ICIF): Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software. Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. 6.1.17 R10 ~ R3F These are all 8-bit general-purpose register. 6.2 Special Purpose Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand on hold, usually involves the temporary storage function of the Accumulator, which is not an addressable register. 6.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTE INT TS TE PSTE PST2 PST1 PST0 Bit 7 (INTE): INT signal edge 0: Interrupt occurs at a rising edge of the INT pin 1: Interrupt occurs at a falling edge of the INT pin Bit 6 (INT): Interrupt enable flag 0: Masked by DISI or hardware interrupt 1: Enabled by the ENI/RETI instructions This bit is readable only Bit 5 (TS): TCC signal source 0: Internal instruction cycle clock. If P55 is used as I/O pin, TS must be “0” 1: Transition on the TCC pin NOTE The TCC, CO and AD5 of the P55/AD5/CO/TCC pins cannot be used at the same time. The P55/AD5/CO/TCC pin priority is as follows: P55/AD5/CO/TCC Priority Highest High Medium Low TCC CO AD5 P55 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 17 EM78P143 8-Bit Microprocessor with OTP ROM Bit 4 (TE): TCC signal edge 0: Increment if a transition from low to high takes place on the TCC pin 1: Increment if a transition from high to low takes place on the TCC pin Bit 3 (PSTE): Prescaler enable bit for TCC 0: Prescaler disable bit. TCC rate is 1:1. 1: Prescaler enable bit. TCC rate is set from Bit 2 ~ Bit 0. Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits PST2 PST1 PST0 TCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 NOTE Tcc time-out period [1/Fosc x prescaler x (2–6 - Tcc cnt) x 1 (CLK=2)] Tcc time-out period [1/Fosc x prescaler x (2–6 - Tcc cnt) x 1 (CLK=4)] 6.2.3 IOC50 (I/O Port Control Registe“) "0" Defines the relative I/O pin as output "1" Puts the relative I/O pin into high impedance 6.2.4 IOC60 (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 The IOC60 register is both readable and writable. Bit 7: Not used bit. Read as ‘0’ all the time. Bit 6 (/PH56): Control bit used to enable pull-high of the P56 pin. 0: Enable internal pull-high 1: Disable internal pull-high Bit 5 (/PH55): Control bit used to enable internal pull-high of the P55 pin. Bit 4 (/PH54): Control bit used to enable internal pull-high of the P54 pin. 18 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Bit 3 (/PH53): Control bit used to enable internal pull-high of the P53 pin. Bit 2 (/PH52): Control bit used to enable internal pull-high of the P52 pin. Bit 1 (/PH51): Control bit used to enable internal pull-high of the P51 pin. Bit 0 (/PH50): Control bit used to enable internal pull-high of the P50 pin. 6.2.5 IOC70 (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” /PD56 /PD55 /PD54 /PD53 /PD52 /PD51 /PD50 IOC70 register is both readable and writable Bit 7: Not used bit. Read as “0” all the time. Bit 6 (/PD56): Control bit used to enable P56 pin pull-down 0: Enable internal pull-down 1: Disable internal pull-down Bit 5 (/PD55): Control bit used to enable internal pull-down of P55 pin Bit 4 (/PD54): Control bit used to enable internal pull-down of P54 pin Bit 3 (/PD53): Control bit used to enable internal pull-down of P53 pin Bit 2 (/PD52): Control bit used to enable internal pull-down of P52 pin Bit 1 (/PD51): Control bit used to enable internal pull-down of P51 pin Bit 0 (/PD50): Control bit used to enable internal pull-down of P50 pin 6.2.6 IOC80 (Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” /OD56 /OD55 /OD54 /OD53 /OD52 /OD51 /OD50 IOC80 register is both readable and writable. Bit 7: Not used bit. Read as “0” all the time. Bit 6 (/OD56): Control bit used to enable the open-drain output of P56 pin 0: Enable open-drain output 1: Disable open-drain output Bit 5 (/OD55): Control bit used to enable open-drain output of P55 pin Bit 4 (/OD54): Control bit used to enable open-drain output of P54 pin Bit 3 (/OD53): Control bit used to enable open-drain output of P53 pin Bit 2 (/OD52): Control bit used to enable open-drain output of P52 pin Bit 1 (/OD51): Control bit used to enable open-drain output of P51 pin Bit 0 (/OD50): Control bit used to enable open-drain output of P50 pin Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 19 EM78P143 8-Bit Microprocessor with OTP ROM 6.2.7 IOC90 (CMPCON: Comparator Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /IVRE VRE3 VRE2 VRE1 VRE0 CPOUT COS1 COS0 Bit 7 (/IVRE): Comparator Internal Voltage Reference Enable bit (“0”: default). When the /IVRE bit is set to “0”, CIN- pin is set as normal I/O pin. Bits 6~3 (VRE3~VRE0): Internal Voltage Reference Ratio Control Bits VRE3 VRE2 VRE1 VRE0 Voltage Reference Value 0 0 0 0 0 0 0 0 1 VDD × 1/15 0 0 1 0 VDD × 2/15 0 0 1 1 VDD × 3/15 0 1 0 0 VDD × 4/15 0 1 0 1 VDD × 5/15 0 1 1 0 VDD × 6/15 0 1 1 1 VDD × 7/15 1 0 0 0 VDD × 8/15 1 0 0 1 VDD × 9/15 1 0 1 0 VDD × 10/15 1 0 1 1 VDD × 11/15 1 1 0 0 VDD × 12/15 1 1 0 1 VDD × 13/15 1 1 1 0 VDD × 14/15 1 1 1 1 VDD (default) Bit 2 (CPOUT): Result of the comparator output (register is readable only) Bit 1 ~ Bit 0 (COS1 ~ COS0): Comparator Select bits 20 • COS1 COS0 Function Description 0 0 Comparator is not used. P55 functions as normal I/O pin. 0 1 Comparator is used and P55 functions as normal I/O pin. 1 0 Used as Comparator and P55 funcions as Comparator output pin (CO) 1 1 Unused Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM NOTE The TCC, CO and AD5 of the P55/AD5/CO/TCC pins cannot be used at the same time. The P55/AD5/CO/TCC pin priority is as follows: P55/AD5/CO/TCC Priority Highest High Medium Low TCC CO AD5 P55 The CIN+ & AD3 of the P53/AD3/CIN+ pins cannot be used at the same time. The P53/AD3/CIN+ pin priority is as follows: P53/AD3/CIN+ Priority High Medium Low CIN+ AD3 P53 6.2.8 IOCA0 ~ IOCC0: Reserved 6.2.9 IOCD0 (Option Control Bit I) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EM78P143 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ICE143 ‘0’ ‘0’ ‘0’ C4 C3 C2 C1 C0 The IOCD0 register is both readable and writable. Bits 7~5: Not used bit. Read as “0” all the time. Bits 4~0 (C4~C0): IRC calibration bits in IRC oscillator mode. C4 C3 C2 C1 C0 Frequency (MHz) 0 0 0 0 0 F*(1-48%) 0 0 0 0 1 F*(1-45%) 0 0 0 1 0 F*(1-42%) 0 0 0 1 1 F*(1-39%) 0 0 1 0 0 F*(1-36%) 0 0 1 0 1 F*(1-33%) 0 0 1 1 0 F*(1-30%) 0 0 1 1 1 F*(1-27%) 0 1 0 0 0 F*(1-24%) 0 1 0 0 1 F*(1-21%) 0 1 0 1 0 F*(1-18%) 0 1 0 1 1 F*(1-15%) Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 21 EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) C4 C3 C2 C1 C0 Frequency (MHz) 0 1 1 0 0 F*(1-12%) 0 1 1 0 1 F*(1-9%) 0 1 1 1 0 F*(1-6%) 0 1 1 1 1 F*(1-3%) 1 1 1 1 1 F (default) 1 1 1 1 0 F*(1+3%) 1 1 1 0 1 F*(1+6%) 1 1 1 0 0 F*(1+9%) 1 1 0 1 1 F*(1+12%) 1 1 0 1 0 F*(1+15%) 1 1 0 0 1 F*(1+18%) 1 1 0 0 0 F*(1+21%) 1 0 1 1 1 F*(1+24%) 1 0 1 1 0 F*(1+27%) 1 0 1 0 1 F*(1+30%) 1 0 1 0 0 F*(1+33%) 1 0 0 1 1 F*(1+36%) 1 0 0 1 0 F*(1+39%) 1 0 0 0 1 F*(1+42%) 1 0 0 0 0 F*(1+45%) NOTE 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode. Hence, they are shown for reference only. Definite values are dependent on the actual process. 2. Similar method of calculation is also applicable for low frequency mode. 6.2.10 IOCE0 (Option Control Bits II) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EM78P143 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ICE143 “0” “0” LVR1 LVR0 RCM1 RCM0 ADBS WDTPS IOCE0 register is both readable and writable. Bits 7~6: Not used bit. Read as “0” all the time. 22 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits. LVR1, L VR0 VDD Reset Level 11 VDD Release Level NA (Power-on Reset) 10 2.7V 2.9V 01 3.5V 3.7V 00 4.0V 4.2V Bit 3 and Bit 2 (RCM1 and RCM0): IRC mode select bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 (default) 1 0 16 0 1 8 0 0 455kHz Bit 1(ADBS): AD Bit Select Register, fixed at “0”. Bit 0 (WDTPS): WDT Time-out Period Select bit WDT Time Watchdog Timer 1 18 ms (Default)* 0 4.5 ms* *Theoretical values, for reference only 6.2.11 IOCF0 (Interrupt Mask Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMPIE ”0” PWM2IE PWM1IE ADIE EXIE ICIE TCIE NOTE The IOCF0 register is both readable and writable. Individual interrupt is enabled by setting its associated control bit in the IOCF0 “o ”1." Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-6b (Interrupt Input Circuit) in Section 6.6 (Interrupt). Bit 7 (CMPIE): CMPIF interrupt enable bit 0: Disable CMPIF interrupt 1: Enable CMPIF interrupt When the Comparator output status change is used to enter an interrupt vector or to enter the next instruction, the CMPIE bit must be set to “Enable“. Bit 6: Not used bit. Read as “0” all the time Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 23 EM78P143 8-Bit Microprocessor with OTP ROM Bit 5 (PWM2IE): PWM2IF interrupt enable bit 0: Disable PWM2 interrupt 1: Enable PWM2 interrupt Bit 4 (PWM1IE): PWM1IF interrupt enable bit 0: Disable PWM1 interrupt 1: Enable PWM1 interrupt Bit 3 (ADIE): ADIF interrupt enable bit 0: Disable ADIF interrupt 1: Enable ADIF interrupt When the ADC Complete status is used to enter an interrupt vector or to enter the next instruction, the ADIE bit must be set to “Enable.“ Bit 2 (EXIE): EXIF interrupt enable bit 0: Disable EXIF interrupt 1: Enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0: Disable ICIF interrupt 1: Enable ICIF interrupt If Port 5 Input Status Change Interrupt is used to enter an interrupt vector or to enter next instruction, the ICIE bit must be set to “Enable“. Bit 0 (TCIE): TCIF interrupt enable bit 0: Disable TCIF interrupt 1: Enable TCIF interrupt 6.2.12 IOC51 (PWMCON: PWM Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ”0” “0” “0” “0” “0” PWMCAS PWM2E PWM1E Bits 7~3: Not used bit. Read as “0” all the time Bit 2 (PWMCAS): PWM Cascade Mode 0: Two Independent 8-bit PWM functions (default value). 1: 16-bit PWM Mode (Cascaded from two 8-bit ones) Bit 1 (PWM2E): PWM2 enable bit 0: PWM2 is off (default value), and its related pin carries out the P56 function. 1: PWM2 is on, and its related pin is automatically set to output. 24 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Bit 0 (PWM1E): PWM1 enable bit 0: PWM1 is off (default value), and its related pin carries out the P51 function. 1: PWM1 is on, and its related pin is automatically set to output. NOTE The P56/AD6/PWM2 pin cannot be applied to PWM2 and AD6 at the same time. The P56/AD6/PWM2 pin priority is as follows: P56/AD6/PWM2 High Medium Low PWM2 AD6 P56 The P51/AD1/PWM1/ OSCO pin cannot be applied to AD1, PWM1, and OSCO at the same time. The P51/AD1 /PWM1/OSCO pin priority is as follows: P51/AD1/PWM1/OSCO Priority Highest High Medium Low OSCO PWM1 AD1 P51 6.2.13 IOC61 (TMRCON: Timer Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T2EN T1EN T2P2 T2P1 T2P0 T1P2 T1P1 T1P0 Bit 7 (T2EN): TMR2 enable bit 0: TMR2 is off (default value) 1: TMR2 is on Bit 6 (T1EN): TMR1 enable bit 0: TMR1 is off (default value) 1: TMR1 is on Bit 5 ~ Bit 3 (T2P2 ~ T2P0): TMR2 clock prescaler option bits T2P2 T2P1 T2P0 Prescale 0 0 0 1:1 (default) 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 25 EM78P143 8-Bit Microprocessor with OTP ROM Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescale option bits T1P2 T1P1 T1P0 Prescale 0 0 0 1:1 (default) 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.14 IOC71 (PRD1: PWM1 Time Period) The content of IOC71 is the time period (time base) of PWM1. The frequency of PWM1 is the reverse of the period. 6.2.15 IOC81 (PRD2: PWM2 Time Period) The content of IOC81 is the time period (time base) of PWM2. The frequency of PWM2 is the reverse of the period. 6.2.16 IOC91 (DT1: PWM1 Duty Cycle) A specified value keeps the output of PWM1 to remain high until the value matches with TMR1. 6.2.17 IOCA1 (DT2:PWM2 Duty Cycle) A specified value keeps the output of PWM2 to remain high until the value matches with TMR2. 6.2.18 IOCB1 (TMR1: PWM1 Timer) The content of IOCB1 is read-only. 6.2.19 IOCC1 (TMR2: PWM2 Timer) The content of IOCC1 is read-only. 26 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.2.20 IOCD1 (Wake-up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” “0” “0” “0” “0” ADWE CMPWE ICWE Bits 7~3: Not used bit. Read as “0” all the time. Bit 2 (ADWE): ADC wake-up enable bit 0: Disable ADC wake-up 1: Enable ADC wake-up When the ADC Complete status is used to enter the interrupt vector or to wake-up the EM78P143 from Sleep mode with the AD conversion running, the ADWE bit must be set to “Enable“. Bit 1 (CMPWE): Comparator wake-up enable bit 0: Disable Comparator wake up 1: Enable Comparator wake up When the Comparator output status change is used to enter the interrupt vector or to wake-up the EM78P143 from Sleep mode, the CMPWE bit must be set to “Enable“. Bit 0 (ICWE): Port 5 input change to wake-up status enable bit 0: Disable Port 5 input change to wake-up status 1: Enable Port 5 input change wake-up status When the Port 5 Input Status Change is used to enter an interrupt vector or to wake-up the EM78P143 from Sleep mode, the ICWE bit must be set to “Enable“. 6.2.21 IOCE1 (WDT Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE ”0” “0” “0” PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE): Control bit is used to enable the Watchdog Timer 0: Disable WDT 1: Enable WDT The WDTE is both readable and writable Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 27 EM78P143 8-Bit Microprocessor with OTP ROM Bits 6~4: Not used bit. Read as “0” all the time. NOTE The P52/AD2/INT pin cannot be applied to INT and AD2 at the same time. The P52/AD2/INT pin priority is as follows: P52/AD2/INT High Medium Low INT AD2 P52 Bit 3 (PSWE): Prescaler enable bit for WDT 0: Prescaler disable bit. WDT rate is 1:1 1: Prescaler enable bit. WDT rate is set at Bit 2~Bit 0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits PSW2 PSW1 PSW0 WDT Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.22 IOCF1: Reserve 28 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.3 TCC/WDT and Prescaler Registers for the TCC/WDT Circuit PAGE Addr. NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - CONT INTE INT TS TE PSTE PST2 PST1 PST0 R_PAGE 0X0F ISR CMPIF “0” PWM2IF PWM1IF ADIF EXIF ICIF TCIF IOCF0 0X0F IMR CMPIE ”0” PWM2IE PWM1IE ADIE EXIE ICIE TCIE IOCE1 0X0E WDTCR WDTE ”0” “0” “0” PSWE PSW2 PSW1 PSW0 Two 8-bit counters are available as prescalers for the TCC and WDT respectively. The PST0 ~ PST2 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PSW0 ~ PSW2 bits of the IOCE1 register are used to determine the prescaler of WDT. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure below depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or external signal input (edge selectable from the TCC pin). If TCC signal source is from internal clock, TCC Will increase by 1 at main oscillator (without prescaler). Referring to Figure 6-3, If TCC signal source is from the external clock input, TCC will increase by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low level) must be greater than 1CLK. NOTE The internal TCC will stop running when Sleep mode occurs. However, during AD conversion, when TCC is set to “SLEP” instruction, with the ADWE bit of IOCD1 register enabled, the TCC will keep on running. The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in Sleep mode). During normal operation or in Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during normal mode through software programming. Refer to WDTE bit of IOCE1 register (Section 6.2.23 WDT Control Register). With no prescaler, the WDT time-out duration is approximately 18ms 1 or 4.5ms 2 . 1 VDD=5V, Setup time period = 16.5ms ± 30% VDD=3V, Setup time period = 18ms ± 30% 2 VDD=5V, Setup time period = 4.2ms ± 30% VDD=3V, Setup time period = 4.5ms ± 30% Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 29 EM78P143 8-Bit Microprocessor with OTP ROM Fosc 0 TCC Pin 1 Data Bus 8-Bit Counter MUX 8 to 1 MUX TE (CONT) TCC (R1) Prescaler TS (CONT) WDT TCC overflow interrupt PST2~0 (CONT) 8-Bit counter 8 to 1 MUX Prescaler WDTE (IOCE1) PSW2~0 (IOCE1) WDT Time out Figure 6-3 TCC and WDT Block Diagram 6.4 I/O Ports Registers for the I/O Circuit Page Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC50 0×05 IOCR IOC7 ICO6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOC60 0×06 PHCR “0” /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 IOC70 0×07 PDCR “0” /PD56 /PD55 /PD54 /PD53 /PD52 /PD51 /PD50 IOC80 0×08 ODCR “0” /OD56 /OD55 /OD54 /OD53 /OD52 /OD51 /OD50 The I/O registers (Port 5) are bidirectional tri-state I/O ports. The pull-high, pull-down, and open-drain functions can be set internally by IOC60, IOC70, and IOC80, respectively. Port 5 features an input status change interrupt (or wake-up) function. Each I/O pin can be defined “s "in”ut" “r "out”ut" pin by the I/O control registers (IOC50). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 are illustrated in the following Figures 6-4a, 6-4b, and 6-4c respectively. Port 5 with Input Change Interrupt/Wake-up is shown in Figure 6-4d. 30 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM PCRD PORT Q P R _ Q C L P R Q _ Q C L D PCWR CLK IOD D PDWR CLK PDRD 0 M U X 1 Note: Pull-high and Open-drain are not shown in the figure Figure 6-4a I/O Port and I/O Control Register Circuit for Port 5 PCRD Q P R D _ CLK Q C L PCWR P50 ~ P57 Q PORT 0 P R IO D D _ CLK Q C L PDWR M U X 1 PDRD TI n D P R CLK C L Q _ Q Note: Pull-high/down and Open-drain are not shown in the figure Figure 6-4b I/O Port and I/O Control Register Circuit for Port 5 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 31 EM78P143 8-Bit Microprocessor with OTP ROM PCRD P Q R D _ CLK Q C L Q P R D _ CLK Q C L PORT Bit 3 of R7 P R Q CLK _ C Q L D 0 1 PCWR IOD PDWR M U X PDRD INT Note: Pull-high and Open-drain are not shown in the figure Figure 6-4c I/O Port and I/O Control Register Circuit for P52 (/INT) I O C F 0 .1 R F.1 TI 0 TI 1 …. TI 8 Figure 6-4d Port 5 with Input Change Interrupt/Wake-up 32 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function 1. Wake-up 2 Wake-up and Interrupt a) Before Sleep a) Before Sleep 1) Disable WDT 1) Disable WDT 2) Read I/O Port 5 (MOV R5,R5) 2) Read I/O Port 5 (MOV R5,R5) 3) Execu“e "”NI" “r "D”SI" 3) Execu“e "”NI" “r "D”SI" 4) Enable wake-up bit (Set IOCD1 ICWE =1) 4) Enable wake-up bit (Set IOCD1 ICWE =1) 5) Execu“e "S”EP" instruction 5) Enable interrupt (Set IOCF0 ICIE =1) b) After wake-up → Next instruction 6) Execu“e "S”EP" instruction b) After Wake-up 1) “F "”NI" → Interrupt vector (006H) 2) “F "D”SI" → Next instruction 3. Interrupt a) Before Port 5 pin change 1) Read I/O Port 5 (MOV R5,R5) 2) Execu“e "”NI" “r "D”SI" 3) Enable interrupt (Set IOCF0 ICIE =1) b) After Port 5 pin changed (interrupt) 1) “F "”NI" → Interrupt vector (006H) 2) “F "D”SI" → Next instruction 6.5 Reset and Wake-up 6.5.1 Reset and Wake-up Operation A reset is initiated by one of the following events: 1) Power-on reset 2) /RESET pin inp“t "”ow" 3) WDT time-out (if enabled) The device is kept in reset condition for a period of approximately 18ms 3 (except in LXT mode) after the reset is detected. When in LXT2 mode, the reset time is 2~3s. Two choices (18ms3 or 4.5ms 4 ) are available for WDT-time out period. Once a RESET occurs, the following functions are performed (the initial Address is 000h): The oscillator continues running, or will be started (if in Sleep mode) 3 4 VDD=5V, WDT Time-out period = 16.5ms ± 30%. VDD=3V, WDT Time-out period = 18ms ± 30%. VDD=5V, WDT Time-out period = 4.2ms ± 30%. VDD=3V, WDT Time-out period = 4.5ms ± 30%. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 33 EM78P143 8-Bit Microprocessor with OTP ROM The Program Counter (R2) is set to all "0" All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper two bits of R3 and upper two bits of R4 are cleared The CONT register bits are set to all "0" except for Bit 6 (INT flag) The IOC60 register bits are set to all "1" The IOC70 register bits are set to all "1" The IOC80 register bits are set to all "1" RF register and IOCF0 register are cleared Executing the “SLEP” instruction will assert the Sleep (power down) mode. While going into Sleep mode, the Oscillator, TCC, Timer 1 and Timer 2 are stopped. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened by any of the following events: 1) External reset input on /RESET pin 2) WDT time-out (if enabled) 3) Port 5 input status changes (if ICWE is enabled) 4) Comparator output status changes (if CMPWE is enabled) 5) AD conversion completed (if ADWE is enabled) 6) Low voltage Detector (if LVDWE is enabled) The first two events (1 and 2) will cause the EM78P143 to reset. The T and P flags of R3 can be used to determine the source of the reset (Wake-up). Events 3, 4, 5, and 6 are considered the continuation of program execution and the global interrupt (”INI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from Address 0x06 (Event 3), 0x0F (Event 4), and 0x0C (Event 5) and 0x18 (Event 6) after Wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP immediately after waking-up. Only one of Events 2 to 6 can be enabled before entering into Sleep mode. That is: a) If WDT is enabled before SLEP, the entire IOCD1 bit is disabled. Hence, the EM78P143 can be awakened only under Event 1 or Event 2 condition. Refer to Section 6.6, Interrupt, for further details. b) If Port 5 Input Status Change is used to wake up the EM78P143 and the ICWE bit of the IOCD1 register is enabled before SLEP, the WDT must be disabled. Hence, the EM78P143 can be awakened only under Event 3 condition. 34 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Wake-up time is subject to the following existing oscillator modes: In RC mode, wake-up time is 32 clocks (for stable oscillators). In Crystal mode, wake-up time is 1.5ms (XT, 4 MHz). In low Crystal mode, wake-up time is 2s ~ 3c)If Comparator output status change is used to wake up the EM78P143 and the CMPWE bit of the IOCD1 register is enabled before SLEP, the WDT must be disabled by software. Hence, the EM78P143 can be awakened only under Event 4 condition. Wake-up time is subject to existing oscillator mode: In RC mode, wake-up time is 32 clocks (for stable oscillators). In Crystal mode, wake-up time is 1.5ms (XT, 4 MHz). In low Crystal mode, wake-up time is 2s~3s. d) If AD conversion completed status is used to wake up the EM78P143 and ADWE bit of the IOCD1 register is enabled before SLEP, the WDT must be disabled by software. Hence, the EM78P143 can be awakened only under Event 5 condition. The wake-up time is 15 TAD (ADC clock period). e) If Low voltage detector is used to wake up the EM78P143 and LVDWE bit of R6 register is enabled before SLEP, the WDT must be disabled by software. Hence, the EM78P143 can be awakened only under Event 6 condition. If Port 5 Input Status Change Interrupt is used to wake up the EM78P143 (as in Event b above), the following instructions must be executed before SLEP: BS R3, 6 MOV A, @00001110b IOW IOCE1 WDTC MOV R5, R5 ENI (or DISI) MOV A, @00000XX1b IOW IOCD1 BC R3, 6 MOV A, @00000x1xb IOW IOCF0 SLEP Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) ; Select Segment 1 ; Select WDT prescaler and Disable WDT ; ; ; ; Clear WDT and prescaler Read Port 5 Enable (or disable) global interrupt Enable Port 5 input change wake-up bit ; Select Segment 0 ; Enable Port 5 input change interrupt ; SLEEP • 35 EM78P143 8-Bit Microprocessor with OTP ROM Similarly, if the Comparator Interrupt is used to wake up the EM78P143 (as in Event c above), the following instructions must be executed before SLEP: BC MOV R3, 6 A, @xxxxxx10b IOW IOC90 BS R3, 6 MOV A, @00001110b IOW IOCE1 WDTC ENI (or DISI) MOV A, @00000X1Xb IOW BC IOCD1 R3,6 A,@10XXXXXXb MOV MOV SLEP 6.5.1.1 ; Select Segment 0 ; Select an comparator and P55 act as CO ; pin ; Select Segment 1 ; Select WDT prescaler and Disable WDT ; Clear WDT and prescaler ; Enable (or disable) global interrupt ; Enable comparator output status change ; wake-up bit ; Select Segment 0 ; Enable comparator output status change ; Interrupt IOCF0 ; Sleep Summary of Wake-up and Interrupt Modes Operation All categories in Wake-up and Interrupt modes are summarized below. Wake-up Signal Sleep Mode External interrupt × Port 5 pin change TCC overflow interrupt AD conversion complete interrupt Comparator interrupt 36 • If enable ICWE bit Wake-up + interrupt (if interrupt enable) + next instruction × If enable ADWE bit Wake-up + interrupt (if interrupt enable) + next instruction Fs & Fm don’t stop If enable CMPWE bit Wake-up + interrupt (if interrupt enable) + next instruction Idle Mode Green Mode Normal Mode Wake-up + interrupt (if interrupt enable) + next instruction If enable ICWE bit Wake-up + interrupt (if interrupt enable) + next instruction Wake-up + interrupt (if interrupt enable) + next instruction If enable ADWE bit Wake-up + interrupt (if interrupt enable) + next instruction Fs & Fm don’t stop If enable CMPWE bit Wake-up+ interrupt (if interrupt enable) + next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction × Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Wake-up Signal Sleep Mode Idle Mode PWMX Green Mode Normal Mode × Wake-up + interrupt (if interrupt enable) + next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction If Enable LVDWE bit Wake-up + interrupt (if interrupt enable) + next instruction If Enable LVDWE bit Wake-up + interrupt (if interrupt enable) + next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction WDT Time out RESET RESET RESET RESET Low Voltage Reset RESET RESET RESET RESET (PWM1 and PWM2) (When TimerX matches PRDX) Low Voltage Detector interrupt NOTE After wake up: 1. If interrupt enable Æ interrupt + next instruction 2. If interrupt disable Æ next instruction 6.5.1.2 Signal Summary of Wake-up and Interrupt Modes Operation Sleep Mode Normal Mode DISI + IOCF0 (EXIE) Bit 2 = 1 INT Pin NA Next Instruction+ Set RF (EXIF) = 1 ENI + IOCF0 (EXIE) Bit 2 = 1 Interrupt Vector (0x03 )+ Set RF (EXIF)=1 Port 5 Input Status Change IOCD1 (ICWE) Bit1=0, IOCF0 (ICIE) Bit1=0 IOCF0 (ICIE) Bit 1 = 0 Oscillator, TCC and TIMERX are stopped. Port 5 input status change wake up is invalid. Port 5 input status change interrupt is invalid IOCD1 (ICWE) Bit1=0, IOCF0 (ICIE) Bit1=1 NA Set RF (ICIF) = 1, Oscillator, TCC and TIMERX are stopped. Port 5 input status change wake up is invalid. NA IOCD1 (ICWE) Bit 0 = 1, IOCF0 (ICIE) Bit 1 = 0 NA Wake-up+ Next Instruction Oscillator, TCC and TIMERX are stopped. NA IOCD1 (ICWE) Bit 0 = 1, DISI + IOCF0 (ICIE) Bit 1 = 1 DISI + IOCF0 (ICIE) Bit 1 = 1 Wake-up+ Next Instruction+ Set RF (ICIF) = 1 Oscillator, TCC and TIMERX are stopped. Next Instruction+ Set RF (ICIF) = 1 IOCD1 (ICWE) Bit 0=1, ENI + IOCF0 (ICIE) Bit 1 = 1 ENI + IOCF0 (ICIE) Bit 1 = 1 Wake-up+ Interrupt Vector (0x06 )+ Set RF (ICIF) = 1 Oscillator, TCC and TIMERX are stopped. Interrupt Vector (0x06 )+ Set RF (ICIF)=1 DISI + IOCF0 (TCIE) Bit 0=1 TCC Overflow NA Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) Bit 0=1 Interrupt Vector (009H) + Set RF (TCIF)=1 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 37 EM78P143 8-Bit Microprocessor with OTP ROM Signal AD Conversion Sleep Mode Normal Mode IOCD1 (ADWE) Bit 2=0, IOCF0 (ADIE) Bit 3 = 0 IOCF0 (ADIE) Bit 3=0 Clear R9 (ADRUN) = 0, ADC is stopped, AD conversion wake up is invalid. Oscillator, TCC and TIMERX are stopped. AD conversion interrupt is invalid IOCD1 (ADWE) Bit 2 = 0, IOCF0 (ADIE) Bit 3 = 1 NA Set RF (ADIF) = 1, R9 (ADRUN) = 0, ADC is stopped, AD conversion wake up is invalid. Oscillator, TCC and TIMERX are stopped. NA IOCD1 (ADWE) Bit 2 = 1, IOCF0 (ADIE) Bit 3 = 0 NA Wake-up+ Next Instruction, Oscillator, TCC and TIMERX keep on running. Wake up when AD conversion is completed. NA IOCD1 (ADWE) Bit 2 = 1, DISI + IOCF0 (ADIE) Bit 3 = 1 DISI + IOCF0 (ADIE) Bit 3=1 Wake-up+ Next Instruction+ RF (ADIF) = 1, Oscillator, TCC and TIMERX keep on running. Wake up when AD conversion is completed. Next Instruction + RF (ADIF)=1 IOCD1 (ADWE) Bit 2 = 1, ENI + IOCF0 (ADIE) Bit 3 = 1 ENI + IOCF0 (ADIE) Bit 3=1 Wake-up+ Interrupt Vector (0x0C )+ RF (ADIF) = 1, Oscillator, TCC and TIMERX keep on running. Wake-up when AD conversion is completed. Interrupt Vector (00CH) + Set RF (ADIF)=1 IOCD1 (CMPWE) Bit 1 = 0, IOCF0 (CMPIE) Bit 7 = 0 IOCF0 (CMPIE) Bit 7 = 0 Comparator output status change wake-up is invalid. Oscillator, TCC and TIMERX are stopped. Comparator output status change interrupt is invalid. IOCD1 (CMPWE) Bit 1 = 0, IOCF0 (CMPIE) Bit 7 = 1 NA Set RF (CMPIF) = 1, Comparator output status change wake up is invalid. Oscillator, TCC and TIMERX are stopped. NA Comparator IOCD1 (CMPWE) Bit 1 = 1, IOCF0 (CMPIE) Bit 7 = 0 (Comparator Output Status Wake-up+ Next Instruction, Oscillator, TCC and TIMERX are stopped. Change) IOCD1 (CMPWE) Bit 1=1, DISI + IOCF0 (CMPIE) Bit 7 = 1 NA NA DISI + IOCF0 (CMPIE) Bit 7 = 1 Wake-up+ Next Instruction+ Set RF (CMPIF) = 1, Next Instruction+ Set RF (CMPIF) = 1 Oscillator, TCC and TIMERX are stopped. 38 • IOCD1 (CMPWE) Bit 1 = 1, ENI + IOCF0 (CMPIE) Bit 7 = 1 ENI + IOCF0 (CMPIE) Bit 7 = 1 Wake-up+ Interrupt Vector (0x0F)+ Set RF (CMPIF) = 1, Oscillator, TCC and TIMERX are stopped. Interrupt Vector (0x0F)+ Set RF (CMPIF) = 1 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Signal Low Voltage Detector Sleep Mode Normal Mode R6 (LVDWE) Bit 3 = 0, R6 (LVDIE) Bit 4 = 0 R6 (LVDIE) Bit 4 = 0 Low voltage detector is invalid. Oscillator, TCC and TIMERX are stopped. Low voltage detector is invalid. R6 (LVDWE) Bit 3 = 0, R6 (LVDIE) Bit 4 = 1 NA Set R6 (LVDIF) Bit 6 =1, Low voltage detector is invalid. Oscillator, TCC and TIMERX are stopped. NA R6 (LVDWE) Bit 3 = 1, R6 (LVDIE) Bit 4 = 0 NA Wake-up+ Next Instruction, Oscillator, TCC and TIMERX are stopped. NA R6 (LVDWE) Bit 3 = 1, DISI+ R6 (LVDIE) Bit 4 = 1 DISI + R6 (LVDIE) Bit 4 = 1 Wake-up+ Next Instruction+ Set R6 (LVDIF) Bit 3 Next Instruction+ Set R6 (LVDIF) = 1, Oscillator, TCC and TIMERX are stopped. Bit 3 = 1 R6 (LVDWE) Bit 3 = 1,ENI+ R6 (LVDIE) Bit 4 = 1 ENI + R6 (LVDIE) Bit 4 =1 Wake-up+ Interrupt Vector (0x18)+ Set R6 (LVDIF) Bit 3 = 1,Oscillator, TCC and TIMERX are stopped. Interrupt Vector (0x18)+ Set R6 (LVDIF) Bit 3 = 1 WDT Timeout IOCE1 Wake-up+ Reset (Address 0x00) (WDTE) Bit 7 = 1 6.5.1.3 Reset (Address 0x00) Register Initial Values after Reset The following summarizes the initialized values for registers. Addr. N/A N/A N/A N/A Name IOC50 IOC60 IOC70 IOC80 Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name C57 C56 C55 C54 C53 C52 C51 C50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P /PH51 /PH50 1 1 Bit Name - Power-on 0 /PH56 /PH55 1 1 /PH55 1 /PH53 /PH52 1 1 /RESET and WDT 0 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P /PD51 /PD50 1 1 Bit Name - Power-on 0 /PD56 /PD55 1 1 /PD54 1 /PD53 /PD52 1 1 /RESET and WDT 0 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name - Power-on 0 1 1 1 1 1 1 1 /RESET and WDT 0 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P /OD56 /OD55 /OD54 /OD53 /OD52 /OD51 /OD50 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 39 EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Addr. N/A N/A N/A N/A N/A N/A N/A N/A N/A Name IOC90 IOCA0 IOCB0 IOCC0 IOCD0 Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Bit Name /IVRE VRE3 VRE2 VRE1 VRE0 CPOUT COS1 COS0 Power-on 0 1 1 1 1 0 0 0 /RESET and WDT 0 1 1 1 1 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P IOCE0 Power-on (Code /RESET and WDT Option II) Wake-up from Pin Change IOCF0 P P Bit Name CMPIE - Power-on 0 0 0 0 /RESET and WDT 0 0 0 Wake-up from Pin Change P P Bit Name - - 0 IOC51 Power-on PWMCO /RESET and WDT N Wake-up from Pin Change IOC71 Power-on (PRD1) /RESET and WDT Wake-up from Pin Change 40 • P P P EXIE ICIE TCIE 0 0 0 0 0 0 0 0 0 P P P P P P - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P T1EN T2P2 T2P1 T2P0 T1P2 T1P1 T1P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P Bit Name T2EN IOC61 Power-on 0 TMRCO /RESET and WDT 0 N Wake-up from Pin Change P Bit Name N/A Bit 2 PWM2IE PWM1IE ADIE PWMCAS PWM2E PWM1E PRD1 [7] PRD1 [6] PRD1 [5] PRD1 [4] PRD1 [3] PRD1 [2] PRD1 [1] PRD1 [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Addr. Name Reset Type Bit Name N/A IOC81 Power-on (PRD2) /RESET and WDT Wake-up from Pin Change Bit Name N/A IOC91 (DT1) 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P DT1[7] DT1[6] DT1[5] DT1[4] DT1[3] DT1[2] DT1[1] DT1[0] 0 0 0 0 0 0 0 0 P P P P P P P P Power-on DT2[7] DT2[6] DT2[5] DT2[4] DT2[3] DT2[2] DT2[1] DT2[0] 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P TMR1[7] TMR1[6] TMR1[5] TMR1[4] TMR1[3] TMR1[2] TMR1[1] TMR1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P TMR2[7] TMR2[6] TMR2[5] TMR2[4] TMR2[3] TMR2[2] TMR2[1] TMR2[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − − − − 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P IOCC1 (TMR2) /RESET and WDT IOCD1 Power-on (WUCR) /RESET and WDT IOCE1 Power-on (WDTC) /RESET and WDT R1 (TCC) 0 0 0 Wake-up from Pin Change 0×01 0 0 Power-on 0×00 R0 (IAR) PRD2 [7] PRD2 [6] PRD2 [5] PRD2 [4] PRD2 [3] PRD2 [2] PRD2 [1] PRD2 [0] 0 IOCB1 Power-on (TMR1) /RESET and WDT CONT Bit 0 0 Bit Name N/A Bit 1 0 Wake-up from Pin Change N/A Bit 2 0 Bit Name N/A Bit 3 0 Wake-up from Pin Change N/A Bit 4 0 Bit Name N/A Bit 5 /RESET and WDT Wake-up from Pin Change IOCA1 (DT2) Bit 6 Power-on Bit Name N/A Bit 7 ADWE CMPWE ICWE P P P P WDTE − − − 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSWE PSW2 PSW1 PSW0 P P P P P P P P Bit Name INTE INT TS TE PSTE PST2 PST1 PST0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 41 EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Addr. Name 0×02 R2 (PC) 0×03 R3 (SR) 0×04 0×05 0×06 R4 (RSR) R5 Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change Jump to Address 0×06 or continue to execute next instruction Bit Name RST IOCS - T P Z DC C Power-on 0 0 0 1 1 U U U /RESET and WDT 0 0 0 t t P P P Wake-up from Pin Change P P P t t P P P Bit Name − BS6 − − − − − − Power-on 0 0 U U U U U U /RESET and WDT 0 0 P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Power-on U U U U U U U U /RESET and WDT U U U U U U U U Wake-up from Pin Change P P P P P P P Bit Name − LVDIF /LVD 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 P P P P P P P P − - CPUS IDLE EIS 0 0 1 1 0 R6 Power-on (LVDCR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on R7 0×07 (MCSR) /RESET and WDT 0×08 0 0 0 1 1 0 0 0 0 P P P P P P Bit Name - ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Power-on R9 (ADCON) /RESET and WDT Wake-up from Pin Change Power-on RA (ADOC) /RESET and WDT Wake-up from Pin Change Bit Name Power-on RB 0×0B ADDATAH /RESET and WDT Wake-up from Pin Change 42 • 0 P Bit Name 0×0A TCCSC TMR1SC TMR2SC 0 Bit Name 0×09 P LVD0 P Wake-up from Pin Change R8 (AISR) LVDIE LVDWE LVDEN LVD1 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P − − − P P CALI SIGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 U U U U U U U U U U U U U U U U P P P P P P P P VOF[2] VOF[1] VOF[0] Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Addr. Name Reset Type Bit 7 Bit Name Power-on RC 0×0C ADDATAL /RESET and WDT 0×0E RE (TBHP) RF (ISR) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − − − ADD1 ADD0 0 0 0 0 0 0 U U 0 0 0 0 0 0 U U P P P P P P P Bit Name RBit 7 RBit 6 RBit 5 RBit 4 RBit 3 RBit 2 RBit 1 RBit 0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name MLB - - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 P P P Wake-up from Pin Change 0×0F Bit 5 P Wake-up from Pin Change RD 0×0D (TBLP) Bit 6 P P Bit Name CMPIF - PWM2IF PWM1IF ADIF RBit 10 RBit 9 RBit 8 P P P EXIF ICIF TCIF Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Legend: ×: Not used U: Unknown or don’t care P: Previous value before reset 6.5.1.4 t: Check table under Section 6.5.2 Controller Reset Block Diagram VDD D Oscillator Q CLK CLK CLR Power-on Reset Voltage Detector ENWDTB WDT Timeout WDT Setup time Reset /RESET Figure 6-5 Controller Reset Block Diagram Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 43 EM78P143 8-Bit Microprocessor with OTP ROM 6.5.2 T and P Status under Status Register A reset condition is initiated by one of the following events: 1) Power-on reset 2) /RESET pin inp“t "”ow" 3) WDT time-out (if enabled) The values of T and P as listed in the table below, are used to check how the processor wakes up. Reset Type T P Power-on 1 1 /RESET during Operating mode *P *P /RESET wake-up during Sleep mode 1 0 LVR during Operating mode *P *P LVR wake-up during Sleep mode 1 0 WDT during Operating mode 0 1 WDT wake-up during Sleep mode 0 0 Wake-up on pin change during Sleep mode 1 0 *P: Previous status before reset The following shows the events that may affect the status of T and P. Event T P Power-on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-up on pin change during Sleep mode 1 0 *P: Previous value before reset 6.6 Interrupt The EM78P143 has seven interrupts as listed below: 1) TCC overflow interrupt 2) Port 5 Input Status Change Interrupt 3) External interrupt [(P52, /INT) pin] 4) Analog to Digital conversion completed 5) When TMR1/TMR2 matches with PRD1/PRD2 respectively in PWM 6) When the comparators output changes 7) Low voltage detector interrupt 44 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g“, "MOV R5,”R5") is necessary. Each Port 5 pin will have this feature if its status changes. The Port 5 Input Status Change Interrupt will wake up the EM78P143 from Sleep mode if it is enabled prior to going into Sleep mode by executing SLEP instruction. When wake up occurs, the controller will continue to execute the succeeding program if the global interrupt is disabled. If enabled, it will branch out to the Interrupt Vector 006H. External interrupt equipped with digital noise rejection circuit (input pulse less than system clocks time) is eliminated as noise. However, under Low Crystal oscillator (LXT) mode the noise rejection circuit will be disabled. Edge selection is possible with INTE of CONT. When an interrupt is generated by the External interrupt (when enabled), the next instruction will be fetched from Address 003H. Refer to the Word 0 Bits 4 (Section 6.13.1, Code Option Register (Word 0)) for digital noise rejection definition. RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction will be fetched from interrupt vector address. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set regardless of ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution). When an interrupt is generated by the Timer clock/counter (when enabled), the next instruction will be fetched from Address 009, 012, 015 (TCC, Timer 1 and Timer 2, respectively). When an interrupt is generated by the AD conversion completed status (when enabled), the next instruction will be fetched from Address 00CH. When an interrupt is generated by the Comparators (when enabled), the next instruction will be fetched from Address 00FH (Comparator interrupt). When an interrupt is generated during a Low Voltage Detect status (when enabled), the next instruction will be fetched from Address 018H (Low Voltage Detector interrupt). Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After the interrupt service routine is completed, the ACC, R3, and R4 registers are restored. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 45 EM78P143 8-Bit Microprocessor with OTP ROM Interrupt sources ACC Interrupt occurs STACKACC ENI/DISI R3 RETI R4 STACKR3 STACKR4 Figure 6-6a Interrupt Backup Diagram In EM78P143, each individual interrupt source has its own interrupt vector as depicted in the table below. Interrupt Vector Interrupt Status Priority 003H External interrupt 2 006H Port 5 pin change 3 009H TCC overflow interrupt 4 00CH AD conversion complete interrupt 5 00FH Comparator interrupt 6 012H Timer 1 (PWM1) overflow interrupt 7 015H Timer 2 (PWM2) overflow interrupt 8* 018H Low Voltage Detector interrupt 1* * Priority: 8 = lowest, 1 = highest Figure 6-6b Interrupt Input Circuit 46 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.7 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consist of an 8-bit analog multiplexer (7-channels); three control registers (AISR/R8, ADCON/R9, and ADOC/RA), two data registers (ADDATAH/RB, ADDATAL/RC), and an ADC with 10-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins. Connecting to the external VREF is more accurate than connecting to the internal VDD. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDATAH and ADDATAL. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS2, ADIS1 and ADIS0. Vref 7-1 Analog Switch ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Power-Down Start to Convert ADC ( successive approximation ) Fsco 4-1 MUX Internal RC 6 ~ 0 AISR 2 1 0 ADCON 6 3 5 ADCON IOCF0 9 8 7 6 5 ADDATAH 4 3 2 1 4 0 3 ADCON ADDATAL DATA BUS Figure 6-7 Analog-to-Digital Conversion Functional Block Diagram 6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) 6.7.1.1 R8 (AISR: ADC Input Select Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 The AISR register individually defines the Port 5 pins as analog input or as digital I/O. Bit 7: Not used bit. Read as “0” all the time Bit 6 (ADE6): AD converter enable bit of P56 pin 0: Disable ADC6, P56 functions as I/O pin 1: Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P55 pin 0: Disable ADC5, P55 functions as I/O pin 1: Enable ADC5 to function as analog input pin Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 47 EM78P143 8-Bit Microprocessor with OTP ROM Bit 4 (ADE4): AD converter enable bit of P54 pin 0: Disable ADC4, P54 functions as I/O pin 1: Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0: Disable ADC3, P53 functions as I/O pin 1: Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0: Disable ADC2, P52 acts as I/O pin 1: Enable ADC2 to act as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0: Disable ADC1, P51 acts as I/O pin 1: Enable ADC1 to act as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0: Disable ADC0, P50 acts as I/O pin 1: Enable ADC0 to act as analog input pin NOTE The TCC, CO and AD5 of the P55/AD5/CO/TCC pins cannot be used at the same time. The P55/AD5/CO/TCC pin priority is as follows: P55/AD5/CO/TCC Priority 6.7.1.2 Highest High Medium Low TCC CO AD5 P55 R9 (ADCON: AD Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 The ADCON register controls the operation of the AD conversion and determines which pin should be currently active. Bit 7(VREFS): Input source of the ADC Vref 0: The ADC Vref is connected to Vdd (default value), and the P54/AD4/CIN-/VREF pin carries out the P54 function 1: The ADC Vref is connected to P54/VREF 48 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. The P54/TCC/VREF pin priority is as follows: P54/TCC/VREF Pin Priority High Medium Low VREF TCC P54 Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The ADC prescaler oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8 CKR1: CKR0 Operation Mode Max. Operating Frequency 00 Fosc/16 4 MHz 01 Fosc/4 1 MHz 10 Fosc/64 16 MHz 11 Fosc/8 2 MHz Bit 4 (ADRUN): ADC starts to RUN. 0: Reset upon completion of the conversion. This bit cannot be reset by software. 1: AD conversion is started. This bit can be set by software. Bit 3 (ADPD): ADC Power-down mode 0: Switch off the resistor reference to save power even while the CPU is operating. 1: ADC is operating NOTE The ADPD bit must be enabled before enabling the ADRUN bit. The program process is shown in Section 6.7.6 (Programming Process/Considerations). Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 49 EM78P143 8-Bit Microprocessor with OTP ROM Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select 111 = unused 110 = ADIN1/P56 101 = ADIN5/P55 100 = ADIN4/P54 011 = ADIN3/P53 010 = ADIN2/P52 001 = ADIN1/P51 000 = ADIN0/P50 These bits can only be changed when the ADIF bit and the ADRUN bit are both Low. 6.7.1.3 RA (ADOC: AD Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CALI SIGN VOF[2] VOF[1] VOF[0] – – – Bit 7 (CALI): Calibration enable bit for ADC offset 0: Calibration disabled 1: Calibration enabled Bit 6 (SIGN): Polarity bit of offset voltage 0: Negative voltage 1: Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits VOF[2] VOF[1] VOF[0] EM78P143 0 0 0 0 LSB 0 0 1 1 LSB 0 1 0 2 LSB 0 1 1 3 LSB 1 0 0 4 LSB 1 0 1 5 LSB 1 1 0 6 LSB 1 1 1 7 LSB Bit 2 ~ Bit 0: Not used bit. Read as “0” all the time 50 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.7.2 ADC Data Register (ADDATAH/RB, ADDATAL/RC) When the AD conversion is completed, the result is loaded into the ADDATAH and ADDATAL registers. The ADRUN bit is cleared, and the ADIF is set. 6.7.3 ADC Sampling Time The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2 μs for each KΩ of the analog source impedance; and at least 2 μs for the low- impedance source. The maximum recommended impedance for the analog source is 10 KΩ at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started. 6.7.4 AD Conversion Time CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at a maximum frequency without sacrificing the AD conversion accuracy. For the EM78P143, the conversion time per bit is about 4 μs. The table below shows the relationship between Tct and the maximum operating frequencies. CKR1:CKR0 Operation Max. Operation Max. Conversion Mode Frequency Rate/Bit Max. Conversion Rate 00 Fosc/16 4 MHz 250kHz (4 μs) 15×4 μs = 60 μs (16.7kHz) 01 Fosc/4 1 MHz 250kHz (4 μs) 15×4 μs = 60 μs (16.7kHz) 10 Fosc/64 16 MHz 250kHz ( 4 μs) 15×4 μs = 60 μs (16.7kHz) 11 Fosc/8 2 MHz 250kHz ( 4 μs) 15×4 μs = 60 μs (16.7kHz) NOTE Pin that is not used as an analog input pin can be used as a regular input or output pin. During conversion, do not perform output instruction. This is to maintain ADC value precision for all the pins. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 51 EM78P143 8-Bit Microprocessor with OTP ROM 6.7.5 ADC Operation during Sleep Mode In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during Sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillators, TCC, Timer 1, Timer 2, and AD conversion. The AD Conversion is considered completed as determined by following factors: 1) ADRUN bit of R9 register is cleared (“0” value). 2) ADIF bit of RF register is set to “1”. 3) ADWE bit of the IOCD1 register is set to “1.” Wake-up from ADC conversion (where it remains in operation during Sleep mode). 4) Wake-up and executes the next instruction if ADIE bit of IOCF0 is enabled and the “DISI” instruction is executed. 5) Wake-up and enters into Interrupt vector (Address 0x0C) if ADIE bit of IOCF0 is enabled and the “ENI” instruction is executed. 6) Enters into Interrupt vector (Address 0x0C) if ADIE bit of IOCF0 is enabled and “ENI” instruction is executed. The results are fed into the ADDATAH and ADDATAL registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion is shut off, no matter what the status of ADPD bit is. 6.7.6 Programming Process/Considerations 6.7.6.1 Programming Process Follow these steps to obtain data from the ADC: 1. Write to the seven bits (ADE6:ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin). 2. Write to the R9/ADCON register to configure the AD module: a) Select the ADC input channel (ADIS2~ADIS0) b) Define the AD conversion clock rate (CKR1:CKR0) c) Select the VREFS input source of the ADC d) Set the ADPD bit to 1 to begin sampling 3. Set the ADWE bit if the wake-up function is employed 4. Set the ADIE bit if the interrupt function is employed 5. Write “ENI” instruction if the interrupt function is employed 6. Set the ADRUN bit to “1” 52 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 7. Write “SLEP” instruction or Polling 8. Wait for wake-up, ADRUN bit is cleared (“0” value) 9. Read the ADDATAH and ADDATAL conversion data registers. If the ADC input channel changes at this time, the ADDATAH and ADDATAL values can be cleared to “0”. 10. Clear the interrupt flag bit (ADIF) 11. For the next conversion, repeat Step 1 or Step 2 as required. At least 2 Tct is required before the next acquisition starts. NOTE In order to obtain accurate values, it is necessary to avoid any data transition on the I/O pins during AD conversion. 6.7.6.2 Sample Demo Program Define a General Register R_0 == 0 PSW == 3 PORT5 == 5 IOCD1== 0XD ; Indirect addressing register ; Status register RF == 0XF ; Interrupt status register ; Wake-up control register Define a Control Register IOC50 == 0X5 ; Control Register of Port 5 IOCF0== 0XF ; Interrupt Control Register ADC Control Register ADDATAH == 0xB ; The contents are ADDATAL == 0XC ; The contents are AISR == 0x08 ; ADC input select ADCON == 0x9 ; 7 6 5 ; VREFS CKR1 CKR0 the results of ADC the results of ADC register 4 3 2 1 0 ADRUN ADPD ADIS2 ADIS1 ADI Define Bits in ADCON ADRUN == 0x4 ADPD == 0x3 ; ADC is executed as the bit is set ; Power Mode of ADC Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 53 EM78P143 8-Bit Microprocessor with OTP ROM Program Starts ORG 0 JMP INITIAL ; Initial address ORG 0x0C ; Interrupt vector ; ; ;(User’s program section) ; ; CLR RF ; To clear the ADIF bit BS ADCON, ADRUN ; To start to execute the next AD conversion ; if necessary RETI INITIAL: MOV A,@0B00000001 ; To define P50 as an analog input MOV AISR,A MOV A,@0B00001000 ; To select P50 as an analog input channel, and ; AD power on MOV ADCON,A ; To define P50 as an input pin and set ; clock rate at fosc/16 En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others IOW PORT5 ; are dependent on applications BS ; Select Segment 1 R3,6 MOV A, @0BXXXXX1XX ; Enable the ADWE wake-up function of ADC, “X” ; by application IOW IOCD1 BC R3,6 ; Select Segment 0 MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC, ; “X” by application IOW IOCF0 54 • ENI ; Enable the interrupt function BS ADCON, ADRUN ; Start to run the ADC Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM ; If the interrupt function is employed, the following three lines may be ignored POLLING: JBC ADCON, ADRUN ; To check the ADRUN bit continuously; JMP POLLING ; ADRUN bit will be reset as the AD conversion ; is completed ; ; ;(User’s program section) 6.8 Dual Sets of PWM (Pulse Width Modulation) Register for the PWM Circuit Page Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC51 0X05 PWMCON “0” “0” “0” “0” “0” IOC61 0X06 TMRCON T2EN T1EN T2P2 T2P1 T2P0 IOC71 0X07 PRD1 PRD1 [7] PRD1 [6] PRD1 [5] PRD1 [4] PRD1 [3] PRD1 [2] PRD1 [1] PRD1 [0] IOC81 0X08 PRD2 PRD2 [7] PRD2 [6] PRD2 [5] PRD2 [4] PRD2 [3] PRD2 [2] PRD2 [1] PRD2 [0] IOC91 0X09 DT1 DT1[7] DT1[6] DT1[5] DT1[4] DT1[3] DT1[2] DT1[1] DT1[0] IOCA1 0X0A DT2 DT2[7] DT2[6] DT2[5] DT2[4] DT2[3] DT2[2] DT2[1] DT2[0] R PAGE 0X0F ISR CMPIF ”0” PWM2IF PWM1IF ADIF EXIF ICIF TCIF IOCF0 0X0F IMR CMPIE ”0” PWM2IE PWM1IE ADIE EXIE ICIE TCIE PWMCAS PWM2E PWM1E T1P2 T1P1 T1P0 6.8.1 Overview In PWM mode, PWM1 and PWM2 pins produce up to 8-bit resolution PWM output (see the functional block diagram in Figure 6-8b next page). A PWM output consists of a time period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the time period. Figure below depicts the relationships between a time period and a duty cycle. Period Duty Cycle PRD1 = TMR1 DT1 = TMR1 Figure 6-8a PWM Output Timing Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 55 EM78P143 8-Bit Microprocessor with OTP ROM Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 latch DL1 DT1 PWM1IF Duty Cycle Match Comparator MUX PWM1 R Q TMR1 S reset IOC51,0 Comparator T1P2 T1P1 T1P0 T1EN Period Match PRD1 Data Bus Data Bus DL2 latch PWM2IF DT2 T2P2 T2P1 T2P0 T2EN Comparator PWM2 Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 Duty Cycle Match TMR2 MUX R Q reset Comparator S IOC51.1 Period Match PRD2 Figure 6-8b Two PWMs Functional Block Diagram 6.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2) TMRX are 8-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. If employed, they can be turned off for power saving by setting the T1EN bit [IOC61<6>] or T2EN bit [IOC61<7>] to “0”. TMR1 and TMR2 are internal designs and cannot be read. 6.8.3 PWM Time Period (PRDX: PRD1 or PRD2) The PWM time period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: 1) TMR is cleared 2) The PWMX pin is set to “1” 3) The PWM duty cycle is latched from DT1/DT2 to DL1/DL2 NOTE The PWM output will not be set, if the duty cycle is “0”) The PWMXIF pin is set to “1” 56 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM The following formula describes how to calculate the PWM time period: ⎛ 1 ⎞ Period = (PRDX + 1)× ⎜ ⎟ × (TMRX prescale value ) ⎝ FOSC ⎠ Example: PRDX =49; Fosc=4 then MHz; TMRX (0, 0, 0) = 1:1, ⎛ 1 ⎞ Period = (49 + 1) × ⎜ ⎟ × 1 = 12.5 µS ⎝ 4M ⎠ 6.8.4 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2) The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded anytime. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: ⎛ 1 Duty Cycle = (DTX ) × ⎜⎜ ⎝ FOSC ⎞ ⎟⎟ × (TMRX prescale value ) ⎠ Example: DTX =10; Fosc=4 then MHz; TMRX (0, 0, 0) = 1:1, ⎛ 1 ⎞ Duty Cycle = 10 × ⎜ ⎟ × 1 = 2.5 µS M 4 ⎝ ⎠ 6.8.5 Comparator X Changing the output status while a match occurs will simultaneously set the PWMXIF (TMRXIF) flag. 6.8.6 PWM Programming Process/Steps Load PRDX with the PWM time period. 1. Load DTX with the PWM Duty Cycle. 2. Enable interrupt function by writing IOCF0, if required. 3. Set PWMX pin to be output by writing a desired value to IOC51. 4. Load a desired value to IOC61 with TMRX prescaler value and enable both PWMx and TMRX Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 57 EM78P143 8-Bit Microprocessor with OTP ROM 6.8.7 PWM Cascade Mode The PWM Cascade Mode merges two 8-bit PWM function into one 16-bit. In this mode, the necessary parameters are redefined as shown on the table below: Paramete DT (Duty) PRD (Period) TMR (Timer) MSB (15~8) DT2 PRD2 TMR2 LSB (7~0) DT1 PRD1 TMR1 16-bit PWM The prescaler of this 16-bit PWM uses the prescaler of the TMR1. The MSB of TMR is counted when LSB carry and the PWM1IF bit/PWM1 pins are redefined as the PWMIF bit/PWM pin (or PWM1 pin). To PWMIF (PWM1IF) latch DL Fosc DT 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 Duty Cycle Match 16-bit Comparator MUX PWM (PWM1) R TMR reset Q S IOC51,2 16-bit Comparator T1P2 T1P1T1P0 T1EN Period Match PRD Data Bus Data Bus Figure 6-9 16-Bit PWM Functional Block Diagram (Merged from Two 8 Bit 6.9 Timer Register for the TIMER Circuit PAGE Addr. NAME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCB1 0X0B TMR1 TMR1[7] TMR1[6] TMR1[5] TMR1[4] TMR1[3] TMR1[2] TMR1[1] TMR1[0] IOCC1 0X0C TMR2 TMR2[7] TMR2[6] TMR2[5] TMR2[4] TMR2[3] TMR2[2] TMR2[1] TMR2[0] 6.9.1 Overview Timer 1 (TMR1) and Timer 2 (TMR2) (TMRX) are 8-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read only. The Timer 1 and Timer 2 will stop running when sleep mode occurs with AD conversion not running. However, if AD conversion is running when sleep mode occurs, the Timer 1 and Timer 2 will keep on running 58 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.9.2 Functional Description The following figure shows the TMRX block diagram followed by descriptions of its signals and blocks. Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 To TMR1IF(PWM1IF) MUX TMR1 reset Period Match Comparator T1P2 T1P1 T1P0 T1EN PRD1 Data Bus Data Bus PRD2 T2P2 T2P1 T2P0 T2EN Comparator TMR2 Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 reset Period Match MUX To TMR2IF(PWM2IF) Figure 6-10 TMRX Block Diagram Where: Fosc: Input clock. Prescaler (T1P2, T1P1 and T1P0 / T2P2, T2P1 and T2P0): The options 1:1, 1:2, 1:4, 1:8, 1:16, 1:64, 1:128, and 1:256 are defined by TMRX. It is cleared when any type of reset occurs. TMR1 and TMR2: Timer X register. TMRX is increased until it matches with PRDX, and then is reset to “0” (default value). PRDX (PRD1, PRD2): PWM time period register Comparator X (Comparator 1 and Comparator 2): Reset TMRX while a match occurs. The TMRXIF (PWMXIF) flag is set at the same time. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 59 EM78P143 8-Bit Microprocessor with OTP ROM 6.9.3 Programming the Related Registers When defining TMRX, refer to the operation of its related registers as shown in the following table. It must be noted that the PWMX bits must be disabled if their related TMRXs are utilized. That is, Bit 7 ~ Bit 3 of the PWMCON register must be set to “0” Related Control Registers of TMR1 and TMR2 Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IOC51 PWMCON/IOC51 ”0” “0” “0” “0” “0” IOC61 TMRCON/IOC61 T2EN T1EN T2P2 T2P1 T2P0 Bit 2 Bit 1 Bit 0 PWMCAS PWM2E PWM1E T1P2 T1P1 T1P0 6.9.4 Timer Programming Process/Steps 1. Load PRDX with the Timer duration 2. Enable interrupt function by writing IOCF0, if required 3. Load a desired value for the TMRX prescaler and enable TMRX and disable PWMX 6.9.5 Timer Cascade Mode The Timer Cascade Mode merges two 8-bit Timer functions into one 16-bit. In this mode, the necessary parameters are redefined as shown in the table below. Parameter PRD (Period) TMR (Timer) MSB(15~8) PD2 TMR2 LSB (7~0) PD1 TMR1 16-bit Timer The prescaler of the 6-bit Timer uses the prescaler of the TMR1. The MSB of TMR is counted when LSB carry and the PWM1IF bit/PWM1 pin are redefined as the PWMIF bit/PWM pin (or PWM1 pin). Figure 6-11 16-Bit Timer Functional Block Diagram (Merged from Two 8-Bit Timer 60 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.10 Comparator Register for the Comparator Circuit PAGE Addr. IOC90 Name 0X09 CMPCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 /IVRE VRE3 VRE2 VRE1 VRE0 CPOUT Bit 1 Bit 0 COS1 COS0 R PAGE 0X0F ISR CMPIF “0” PWM2IF PWM1IF ADIF EXIF ICIF TCIF IOCF0 0X0F IMR CMPIE ”0” PWM2IE PWM1IE ADIE EXIE ICIE TCIE IOCD1 0X0D WUCR “0” “0” ADWE CMPWE ICWE “0” “0” “0” The EM78P143 has one comparator which has two analog inputs and one output. The comparator can be employed to wake up the system from Sleep/Idle mode. The comparator circuit diagram is depicted in the following figure. Cin - CO CMP Cin+ + 5mV Cin5mV Cin+ Output Figure 6-12 Comparator Circuit Diagram and Operating Mode 6.10.1 Comparator Reference Signal The analog signal that is presented at Cin– is compared to the signal at Cin+, and the digital output (CO) of the comparator is adjusted accordingly by taking the following notes into consideration The reference signal must be located between Vss and Vdd The reference voltage can be applied to either pin of the comparator. Furthermore, the Cin− signal path can be set using the internal reference voltage through /IVRE bit, and with the VRE3 ~ VRE0 bits as the reference voltage ratio. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 61 EM78P143 8-Bit Microprocessor with OTP ROM VDD IVRE 1111 1110 MUX Internal Reference Voltage 0000 VRE3:VRE0 Figure 6-13 Comparator Trim Equivalent Circuit 62 • VRE3 ~ VRE0 bits reference voltage ratio: VRE3 VRE2 VRE1 VRE0 Voltage Reference Value 0 0 0 0 0 0 0 0 1 VDD × 1/15 0 0 1 0 VDD × 2/15 0 0 1 1 VDD × 3/15 0 1 0 0 VDD × 4/15 0 1 0 1 VDD × 5/15 0 1 1 0 VDD × 6/15 0 1 1 1 VDD × 7/15 1 0 0 0 VDD × 8/15 1 0 0 1 VDD × 9/15 1 0 1 0 VDD × 10/15 1 0 1 1 VDD × 11/15 1 1 0 0 VDD × 12/15 1 1 0 1 VDD × 13/15 1 1 1 0 VDD × 14/15 1 1 1 1 VDD (default) Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM NOTE The P54/AD4/CIN-/VREFS pin cannot be applied to VREFS, CIN- and AD4 at the same time. The P54/AD4/CIN-/VREFS pin priority is as follows: P54/AD4/CIN-/VREF Pin Priority Highest High Medium Low VREF CIN- AD4 P54 The P53/AD3/CIN+ pin cannot be applied to CIN+ and AD3 at the same time. The P53/AD3/CIN+ pin priority is asP53/AD3/CIN+ follows: High Medium Low CIN+ AD3 P53 6.10.2 Comparator Output The compared result is stored in the CMPOUT of IOC90. The comparator output are sent to CO (P55) by programming Bit 1, Bit 0<COS1, COS0> of the IOC90 register to <1, 0>. See Section 6.2.7, IOC90 (CMPCON: Comparator Control Register) for Comparator select bits function description. NOTE The TCC, CO and AD5 of the P55/AD5/CO/TCC pins cannot be used at the same time. The P55/AD5/CO/TCC pin priority is as follows: P55/AD5/CO/TCC Priority Highest High Medium Low TCC CO AD5 P55 Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 63 EM78P143 8-Bit Microprocessor with OTP ROM The following figure shows the Comparator Output block diagram. To C0 F ro m O P I/O CMRD EN Q EN D Q D To CMPOUT RESET T o C P IF CMRD F r o m o th e r c o m p a r a to r Figure 6-14 Comparator Output Configuration 6.10.3 Comparator Interrupt CMPIE (IOCF0.7) must be enabled for the “ENI” instruction to take effect. Interrupt is triggered whenever a change occurs on the comparator output pin. The actual change on the pin can be determined by reading the Bit CMPOUT, IOC90 <2>. CMPIF (RF.7), the comparator interrupt flag, can only be cleared by software. 6.10.4 Wake-up from Sleep Mode If enabled, the comparator remains active and the interrupt remains functional even while in Sleep mode. If a mismatch occurs, the interrupt will wake up the device from Sleep mode. The power consumption should be taken into consideration for the benefit of energy conservation. If the function is not employed during Sleep mode, turn off the comparator before going into Sleep mode. 64 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.11 Oscillator 6.11.1 Oscillator Modes The EM78P143 can be operated in four different oscillator modes, such a High Crystal oscillator mode (HXT), Low Crystal oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC) You can select one of these modes by programming the OSC3, OSC2, OCS1, and OSC0 in the Code Option register as shown below. OSC3 OSC2 OSC1 OSC0 1 Oscillator Mode 0 0 0 0 1 0 0 0 1 IRC (Internal RC oscillator mode); P51/OSCO act P51 0 0 1 0 IRC2 (Internal RC oscillator mode); P51/OSCO act OSCO 0 0 1 1 LXT1 (Frequency range of LXT1 mode is 100kHz~1 MHz) 0 1 0 0 HXT1 (Frequency range of HXT1 mode is 12 MHz~16 MHz) 0 1 0 1 LXT2 (Frequency LXT2 mode is 32kHz) 0 1 1 0 HXT2 (Frequency range of HXT2 mode is 6 MHz~12 MHz) 0 1 1 1 XT (Frequency range of XT mode is 1 MHz~6 MHz) (default) 1 1 1 1 ERC (External RC oscillator mode); P51/OSCO act P51 ERC (External RC oscillator mode); P51/OSCO act OSCO 2 1 In 2 In ERC mode, P50 is OSCI pin. P51 is defined by Code Option Word 1 Bit 4~Bit 1. IRC mode, P50 is normal I/O pin. P51 is defined by Code Option Word 1 Bit 4~Bit 1. The maximum operating frequency limit of crystal/resonator at different VDDs, are as follows: Conditions Two clocks VDD Max. Freq. (MHz) 2.1 4 4.5 16 6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78P143 can be driven by an external clock signal through the OSCI pin as illustrated at the right diagram. OSCI OSCO Figure 6-15a External Clock Input Circuit Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 65 EM78P143 8-Bit Microprocessor with OTP ROM In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Figure at right depicts such a circuit. The same applies to the HXT mode and the LXT mode. C1 OSCI Crystal OSCO RS C2 Figure 6-15b Crystal/Resonator Circuit The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, you should refer to the resonator specifications for the appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency mode Capacitor selection guide for crystal oscillator or ceramic resonators: Oscillator Type Ceramic Resonators Frequency Mode HXT LXT Crystal Oscillator HXT Frequency C1 (pF) C2 (pF) 455kHz 100~150 100~150 2.0 MHz 20~40 20~40 4.0 MHz 10~30 10~30 32.768kHz 33~68 33~68 100kHz 25 25 200kHz 25 25 455kHz 20~40 20~150 1.0 MHz 15~30 15~30 2.0 MHz 15 15 4.0 MHz 15 15 6.11.3 External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (figure at right) could offer you with effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to manufacturing process variation. 66 • Vcc Rext OSCI Cext Figure 6-16 External RC Oscillator Mode Circuit Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM In order to maintain a stable system frequency, the values of the Cext should be no less than 20pF, and that of Rext should be no greater than 1 MΩ. If the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become unstable because the NMOS cannot discharge the capacitance current correctly. Based on the above logic, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, have certain effect on the system frequency. The RC Oscillator frequencies: Cext 20 pF 100 pF 300 pF Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C 3.3k 3.5 MHz 3.0 MHz 5.1k 2.4 MHz 2.2 MHz 10k 1.27 MHz 1.24 MHz 100k 140 KHz 143 kHz 3.3k 1.21 MHz 1.18 MHz 5.1k 805 kHz 790 kHz 10k 420 kHz 418 kHz 100k 45 kHz 46 kHz 3.3k 550 kHz 526 kHz 5.1k 364 kHz 350 kHz 10k 188 kHz 185 kHz 100k 20 kHz 20 kHz NOTE The values are for design reference onl The frequency drift is ± 30%. 6.11.4 Internal RC Oscillator Mode The EM78P143 offers a versatile internal RC mode with default frequency value of 4 MHz. Other available frequencies, i.e., 4 MHz, 16 MHz, 8 MHz, and 455kHz; can be set through Code Option (Word 1), RCM1, and RCM0. The next table describes the EM78P143 internal RC drift with voltage, temperature, and process variation Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 67 EM78P143 8-Bit Microprocessor with OTP ROM Internal RC Drift Rate (Ta=25°C, VDD=5V ± 5%, VSS=0V) Internal RC Frequency 4 MHz Drift Rate Temperature (0°C ~ +70°C) Voltage (2.3V~5.5V) Process Total ± 3% ± 5% ± 3% ± 11% 16 MHz ± 3% ± 5% ± 3% ± 11% 8 MHz ± 3% ± 5% ± 3% ± 11% 455kHz ± 3% ± 5% ± 3% ± 11% NOTE These are theoretical values provided for reference only. Actual values may vary depending on the actual process. 6.12 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply stabilizes to a steady state. The EM78P143 has a built-in Power-on Voltage Detector (POVD) with detection level range of 1.7V ~ 1.9V. The circuitry eliminates the extra external reset circuit. It will work well if Vdd rises fast enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems. 6.12.1 Programmable WDT Time-out Period The Option word (WDTPS) is used to define the WDT time-out period (18 ms 5 or 4.5 ms 6 ). Theoretically, the range is from 4.5 ms or 18 ms. For most crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time. 6.12.2 External Power-on Reset Circuit The circuits shown in the following figure implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough to allow Vdd to achieve the minimum operating voltage. This circuit is applicable when the power supply has a slow power rise time. Since the current leakage from the /RESET pin is about ±5μA, it is recommended that R should not be greater than 40K. This way, the voltage at Pin /RESET is held at below 0.2V. The diode (D) acts as a short circuit at power-down. The “C” capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET. 68 • 5 VDD=5V, WDT time-out period = 16.5 ms ± 30%. VDD=3V, WDT time-out period = 18 ms ± 30%. 6 VDD=5V, WDT time-out period = 4.2 ms ± 30%. VDD=3V, WDT time-out period = 4.5 ms ± 30%. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Vdd R D /RESET Rin C Figure 6-17 External Power-on Reset Circuit 6.12.2 Residual Voltage Protection When the battery is replaced, device power (Vdd) is removed but the residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. The following two figures show how to create a protection circuit against residual voltage. Vdd Vdd 33K Q1 10K /RESET 100K 1N4684 Figure 6-18a Residual Voltage Protection Circuit 1 Vdd Vdd R1 Q1 /RESET R3 R2 Figure 6-18b Residual Voltage Protection Circuit Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 69 EM78P143 8-Bit Microprocessor with OTP ROM 6.13 Code Option EM78P143 has two Code Option Words and one Customer ID word that are not part of the normal program memory. Word 0 Word 1 Word 2 Bit 12 ~ Bit 0 Bit 12 ~ Bit 0 Bit 12 ~ Bit 0 6.13.1 Code Option Register (Word 0) Word 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Bit Bit 12 Bit 11 Bit 10 – – CLKS Bit 9 – LVR1 LVR0 RESETENB ENWDTB NRHL Bit 8 Bit 7 Bit 6 Bit 5 NRE Protect 1 – – 4clocks – High High P57 Disable 32/fc Enable Disable 0 – – 2clocks – Low Low /RESET Enable 8/fc Enable Disable Bits 12~11: Not used (reserved). This bit is set to “1” all the time. Bit 10 (CLKS): Instruction period option bit 0: Two oscillator periods 1: Four oscillator periods (default) Refer to Section 6.15 for Instruction Set Bit 9: Not used (reserved). This bit is set to “1” all the time. Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset enable bits LVR1, LVR0 VDD Reset Level 11 VDD Release Level NA (Power-on Reset) (Default) 10 2.7V 2.9V 01 3.5V 3.7V 00 4.0V 4.2V Bit 6 (RESETENB): RESET/P57 Pin Select Bit 0: P57 set to /RESET pin 1: P57 is general purpose input pin or open-drain for output port (default) Bit 5 (ENWDTB): Watchdog timer enable bit 0: Enable 1: Disable (default) Bit 4 (NRHL): Noise rejection high/low pulses defined bit. INT pin is a falling edge or rising edge trigger 0: Pulses equal to 8/fc [s] is regarded as signal 1: Pulses equal to 32/fc [s] is regarded as signal (default) 70 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM NOTE The noise rejection function is turned off in LXT2 and Sleep mode. Bit 3 (NRE): Noise rejection enable 0: Disable noise rejection 1: Enable noise rejection (default) However, under Low Crystal oscillator (LXT2) mode, Green mode, and Idle mode, the noise rejection circuit is always disabled. Bits 2~0 (PR2~PR0): Protect Bit 0: Enable 1: Disable 6.13.2 Code Option Register (Word 1) Word 1 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCM1 RCM0 OSC3 OSC2 OSC1 OSC0 Bit 0 Mnemonic HLP C4 C3 C2 C1 C0 RCOUT 1 High High High High High High High High High High High High System_clk 0 Low Low Low Low Low Low Low Low Low Low Low Low Open-drain Bit 12 (HLP): Power consumption selection. 0: Low power consumption mode, applies to operating frequency at 32kHz or below 32kHz 1: High power consumption mode, applies to operating frequency above 32kHz (default) Bits 11~7 (C4, C3, C2, C1 and C0): Calibrator of internal RC mode. These bits must be set to “1” only (auto calibration) Bit 6 and Bit 5 (RCM1 and RCM0): RC mode select bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 (default) 1 0 16 0 1 8 0 0 455kHz Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 71 EM78P143 8-Bit Microprocessor with OTP ROM Bits 4~1 (OSC3~OSC0): Oscillator mode select bits OSC3 OSC2 OSC1 OSC0 1 Oscillator Mode 0 0 0 0 1 ERC (External RC oscillator mode) ; P51/OSCO act P51 0 0 0 1 2 0 0 1 0 2 IRC (Internal RC oscillator mode) ; P51/OSCO act OSCO 0 0 1 1 LXT1 (Frequency range of LXT1 mode is 100kHz~1 MHz) 0 1 0 0 HXT1 (Frequency range of HXT1 mode is 12 MHz~16 MHz) 0 1 0 1 LXT2 (Frequency LXT2 mode is 32kHz) 0 1 1 0 HXT2 (Frequency range of HXT2 mode is 6 MHz~12 MHz) 0 1 1 1 XT (Frequency range of XT mode is 1 MHz~6 MHz) (default) 1 1 1 1 ERC (External RC oscillator mode) ; P51/OSCO act OSCO IRC (Internal RC oscillator mode) ; P51/OSCO act P51 1 In 2 In ERC mode, P50 is OSCI pin, P51 is defined by Code Option Word 1 Bit 4~Bit 1. IRC mode, P50 is normal I/O pin, P51 is defined by Code Option Word 1 Bit 4~Bit 1. Bit 0 (RCOUT): System Clock Output Enable Bit in IRC or ERC mode 0: OSCO pin is open drain 1: OSCO output system clock (default) 6.13.3 Customer ID Register (Word 2) Word 2 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic - - - - WDTPS - ID6 ID5 ID4 ID3 ID2 ID1 ID0 1 - - - - 18ms - High High High High High High High 0 - - - - 4.5ms - Low Low Low Low Low Low Low Bits 12~ 9: Fixed to “1” Bit 8 (WDTPS): WDT Time-out Period Selection bit WDT Time Watchdog Timer 1 18 ms (Default)* 0 4.5 ms* * Theoretical values, for reference only Bit 7: Fixed to “0” Bits 6 ~ 0: Customer’s ID code 6.14 Low Voltage Detector When an unstable power source condition occurs, such as external power noise interference or EMS test condition, a violent power vibration is generated. At the same time, the Vdd becomes unstable as it could be operating below working voltage. When the system supply voltage (Vdd) is below the operating voltage, the IC kernel will automatically keep all register status. 72 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 6.14.1 Low Voltage Reset (LVR) LVR property is set at Bits 8 and 7 of Code Option Word 0. Detailed operation mode is as follows: Word 0 Bit 12 Bit 11 Bit 10 Bit 9 - - CLKS - Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LVR1 LVR0 RESETENB ENWDTB NRHL NRE Bit 1 Bit 0 Protect Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset enable bits LVR1, LVR0 VDD Reset Level 11 VDD Release Level N/A (Power-on Reset) 10 2.7V 2.9V 01 3.5V 3.7V 00 4.0V 4.2V 6.14.2 Low Voltage Detector (LVD) LVD property is set at Registers R6. Detailed operation mode is explained below. 6.14.2.1 R6 (LVD Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - LVDIF /LVD LVDIE LVDWE LVDEN LVD1 LVD0 NOTE The R6 <4> register is both readable and writable. Individual interrupt is enabled by setting its associated control bit in the R6<4> “o ”1." Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-6b (Interrupt Input Circuit) in Section 6.6 (Interrupt). Bit 6 (LVDIF): Low Voltage Detector Interrupt Flag LVDIF is reset to “0” by software or hardware Bit 5 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than the LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0: Low voltage is detected. 1: Low voltage is not detected or LVD function is disabled. Bit 4 of R6: “1” means there’s interrupt request, and “0” means no interrupt occurs. Bit 4 (LVDIE): Low voltage Detector interrupt enable bit 0: Disable Low Voltage Detector interrupt 1: Enable Low Voltage Detector interrupt When a detect low level voltage state is used to enter an interrupt vector or enter the next instruction, the LVDIE bit must be set to “Enable.” Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 73 EM78P143 8-Bit Microprocessor with OTP ROM Bit 3 (LVDWE): Low Voltage Detect wake-up enable bit 0: Disable Low Voltage Detect wake-up 1: Enable Low Voltage Detect wake-up When the Low Voltage Detect is used to enter interrupt vector or to wake-up IC from Sleep/Idle mode with the Low Voltage Detect running, the LVDWE bit must be set to “Enable.“ Bit 2 (LVDEN): Low Voltage Detector enable bit 0: Low voltage detector disable 1: Low voltage detector enable. Bits 1~0 (LVD1:0): Low Voltage Detector level bits LVDEN LVD1, LVD0 1 11 1 10 1 01 1 00 0 ×× LVD Voltage Interrupt Level /LVD Vdd ≤ 2.2V 0 Vdd > 2.2V 1 Vdd ≤ 3.3V 0 Vdd > 3.3V 1 Vdd ≤ 4.0V 0 Vdd > 4.0V 1 Vdd ≤ 4.5V 0 Vdd > 4.5V 1 NA 1 6.14.3 Programming Process Follow these steps to obtain data from the LVD: 1. Write to the two bits (LVD1: LVD0) on the R6 (LVDCR) register to define the LVD level 2. Set the LVDWE bit if the wake-up function is in use. 3. Set the LVDIE bit if the interrupt function is in use. 4. Write “ENI” instruction if the interrupt function is in use. 5. Set LVDEN bit to “1” 6. Write “SLEP” instruction or Polling /LVD bit 7. Clear the interrupt flag bit (LVDIF) when Low Voltage Detect occurs. 74 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM NOTE The internal LVD module uses the internal circuit, and when the code option is set to enable the LVD module, the current consumption will increase to about 5 µ During Sleep mode, the LVD module continues to operate. If the device voltage drops slowly and crosses the detection point, the LVDIF bit will be set and the device will wake up from Sleep mode. The LVD interrupt flag will remain set at priority status When the system resets, the LVD flag is cleared. The following figure shows the LVD module detection point in an external voltage condition. LVDIF is cleared by software Vdd VLVD VRESET LVDIF Internal Reset 18ms <LVR Voltage drop >LVR Voltage drop Vdd < Vreset not longer than 80us, the system still keeps on operating System occur reset Figure 6-19 LVD/LVR Waveform with the Detection Point in an External Voltage Condition When the Vdd drops, but above VLVD, the LVDIF is kept at “0”. When Vdd drops below VLVD, the LVDIF is set to “1”. If global ENI is enabled, the LVDIF is also set to “1” and the next instruction will branch to an interrupt vector. The LVD interrupt flag is cleared to “0” by software. When Vdds drops below VRESET at less than 80µs, the system will keep all the registers’ status and halts it operation, but with the oscillation remaining active. When Vdd drops below VRESET at more than 80µs, a system reset will occur. Refer to Section 6.5.1, Reset and Wake-up Operation; for the detailed Reset description Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 75 EM78P143 8-Bit Microprocessor with OTP ROM 6.15 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instructio“s "MOV R”,A“; "ADD R”,A"; or by instructions of arithmetic or logic operation on R2 (e.g“, "SUB R”,A“; I(C” R“,6"; "”LR R2"; etc.). In addition, the instruction set has the following features: 1) Every bit of any register can be set, cleared, or tested directly. 2) The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers. EM78P143 Instruction Set Table In the following Instruction Set table, the following symbols are “s”d: "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruct“o”. "b" represents a bit field designator that selects the value for the bit which is located in the reg“s”er "R", and affects operati“n” "k" represents an 8 or 10-bit constant or literal value. Binary Instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 76 • 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 0100 rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R Operation Status Affected No Operation None Decimal Adjust A C A → CONT None 0 → WDT, Stop oscillator T, P 0 → WDT T, P 1 A → IOCR None Enable Interrupt None Disable Interrupt None [Top of Stack] → PC None [Top of Stack] → PC, Enable Interrupt None CONT → A None 1 IOCR → A None A→R None 0→A Z 0→R Z R-A → A Z, C, DC R-A → R Z, C, DC R-1 → A Z R-1 → R Z A ∨ VR → A Z A ∨ VR → R Z A&R→A Z A&R→R Z A⊕R→A Z This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Binary Instruction 0 0 0 0 0 0 0 0 0 0 0 0 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 0 0110 01rr rrrr 06rr 0 0110 10rr rrrr 06rr 0 0110 11rr rrrr 06rr 0 0111 00rr rrrr 07rr 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1Fkk 1EAk 1EBk 1Err 2 3 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 0111 0111 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1111 1110 1110 1110 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr HEX 01rr rrrr 10rr rrrr 11rr rrrr bbrr rrrr bbrr rrrr bbrr rrrr bbrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1010 kkkk 1011 kkkk 11rr rrrr Mnemonic Operation A⊕R→R A+R→A A+R→R R→A R→R /R → A /R → R R+1 → A R+1 → R R-1 → A, skip if zero R-1 → R, skip if zero R(n) → A(n-1), R(0) → C, C → A(7) R(n) → R(n-1), R(0) → C, RRC R C → R(7) R(n) → A(n+1), R(7) → C, RLCA R C → A(0) R(n) → R(n+1), R(7) → C, RLC R C → R(0) R(0-3) → A(4-7), SWAPA R R(4-7) → A(0-3) SWAP R R(0-3) ↔ R(4-7) JZA R R+1 → A, skip if zero JZ R R+1 → R, skip if zero BC R,b 0 → R(b) BS R,b 1 → R(b) JBC R,b if R(b)=0, skip JBS R,b if R(b)=1, skip CALL k PC+1 → [SP], (Page, k) → PC JMP k (Page, k) → PC MOV A,k k → A OR A,k A∨k→A AND A,k A&k→A XOR A,k A⊕k→A RETL k k → A, [Top of Stack] → PC SUB A,k k-A → A ADD A,k K+A → A LCALL k PC+1Æ [SP], kÆPC LJMP k kÆPC TBRD R See section 6.1.14 and 6.1.15 XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R Status Affected Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None 2 None 3 None None None None None None Z Z Z None Z, C, DC Z, C, DC None None None This instruction is not recommended for RF operation. This instruction cannot operate under RF. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 77 EM78P143 8-Bit Microprocessor with OTP ROM 7 Absolute Maximum Ratings Items 8 Temperature under bias 0°C to 70°C Storage temperature -65°C to 150°C Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.3V to Vdd+0.5V Working Voltage 2.1V to 5.5V Working Frequency DC to 16 MHz DC Electrical Characteristics Ta= 25°C, VDD= 5.0V, VSS= 0V Symbol 78 • Rating Parameter Condition Min. Typ. Max. Unit FXT Crystal: VDD to 5V Two cycles with two clocks 32.768k 4 16 MHz ERC ERC: VDD to 5V R: 3.3KΩ, C: 100 pF 0.847 1.21 1.573 MHz VIHRC Input High Threshold OSCI in RC mode Voltage (Schmitt Trigger) 3.9 4 4.1 V IERC1 Sink current 21 22 23 mA VILRC Input Low Threshold OSCI in RC mode Voltage (Schmitt Trigger) 1.7 1.8 1.9 V IERC2 Sink current VI from high to low, VI=2V 16 17 18 mA IIL Input Leakage Current for input pins VIN = VDD, VSS -1 0 1 μA VIH1 Input High Voltage (Schmitt Trigger) Port 5 0.7Vdd − Vdd+0.3V V VIL1 Input Low Voltage (Schmitt Trigger ) Port 5 -0.3V − 0.3Vdd VIHT1 Input High Threshold /RESET Voltage (Schmitt Trigger) 0.7Vdd − Vdd+0.3V V VILT1 Input Low Threshold /RESET Voltage (Schmitt trigger) -0.3v − 0.3Vdd VIHT2 Input High Threshold TCC, INT Voltage (Schmitt Trigger) 0.7Vdd − Vdd+0.3V V VILT2 Input Low Threshold TCC, INT Voltage (Schmitt Trigger) -0.3V − 0.3Vdd V VIHX1 Clock Input High Voltage OSCI in crystal mode 2.9 3.0 3.1 V VILX1 Clock Input Low Voltage OSCI in crystal mode 1.7 1.8 1.9 V IOH1 Output High Voltage (Port 5) VOH = 0.9VDD − -9 − mA IOL1 Output Low Voltage (Port 5) VOL = 0.3VDD − 70 − mA IOL2 Output Low Voltage (Port 5) VOL = 0.1VDD − 25 − mA VI from low to high, VI=5V V V Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Symbol Parameter Condition Min. Typ. Max. Unit IPH Pull-high current Pull-high active, input pin at VSS -60 − -80 μA IPL Pull-low current Pull-low active, input pin at Vdd 40 − 60 μA ISB1 Power down current All input and I/O pins at VDD, Output pin floating, WDT disabled LVR disabled, LVD disabled − − 2.0 μA ISB2 Power down current All input and I/O pins at VDD, Output pin floating, WDT enabled LVR disabled, LVD disabled − − 8 μA ISB3 Power down current All input and I/O pins at VDD, Output pin floating, WDT disabled LVR enable, LVD disabled − − 2.5 μA ISB4 Power down current All input and I/O pins at VDD, Output pin floating, WDT enabled LVR enabled, LVD disabled − − 10 μA ICC1 Operating supply current at two clocks /R‘SET=’'High', Fosc=32kHz, (Crystal type,”C”KS="0"), Output pin floating, WDT disabled LVR disabled, LVD disabled − − 35 μA ICC2 Operating supply current at two clocks /R‘SET=’'High', Fosc=32kHz (Crystal type”C”KS="0"), Output pin floating, WDT enabled LVR disabled, LVD disabled − − 35 μA ICC3 Operating supply current at two clocks /R‘SET=’'High', Fosc=4 MHz (Crystal type,”C”KS="0"), Output pin floating, WDT enabled LVR disabled, LVD disabled − − 2.5 mA ICC4 Operating supply current at two clocks /R‘SET=’'High', Fosc=10 MHz (Crystal type,”C”KS="0"), Output pin floating, WDT enabled LVR disabled, LVD disabled − − 4.5 mA NOTE These parameters are hypothetical (not tested) and are provided for design reference use only. Data under Minimum, Typical, and Maximum (Min., Typ., and Max.) columns are based on hypothetical results at 25°C. These data are for design reference only. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 79 EM78P143 8-Bit Microprocessor with OTP ROM Internal RC Electrical Characteristics (Ta=25°C, VDD=5 V, VSS=0V) Drift Rate Internal RC Temperature Voltage Min. Typ. Max. 4 MHz 25°C 5V 3.84 MHz 4 MHz 4.16 MHz 16 MHz 25°C 5V 15.36 MHz 16 MHz 16.64 MHz 8 MHz 25°C 5V 7.76 MHz 8 MHz 8.24 MHz 455kHz 25°C 5V 436.8kHz 455kHz 473.z Internal RC Electrical Characteristics (Ta= 0 ~70°C, VDD=2.2V~5.5V, VSS=0V) Drift Rate Internal RC Temperature Voltage Min. Typ. Max. 4 MHz 0 ~ 70°C 2.2V~5.5V 3.44 MHz 4 MHz 4.56 MHz 16 MHz 0 ~ 70°C 2.2V~5.5V 13.76 MHz 16MHz 18.24 MHz 8 MHz 0 ~ 70°C 2.2V~5.5V 6.96 MHz 8 MHz 9.04 MHz 455kHz 0 ~ 70°C 2.2V~5.5V 391.3kHz 455kHz − 8.1 AD Converter Characteristics Symbol VAREF Vdd=2.5V to 5.5V, Vss=0V, Ta= 0 to 70°C, 10-bit AD Parameter Analog reference voltage VASS VAI Min. Typ. Max. Unit 2.5 − Vdd V Vss − Vss V VASS − VAREF V VDD=VAREF=5.0V, VASS = 0.0V (V reference from Vdd) 1100 1200 1400 µA -10 0 +10 µA VDD=VAREF=5.0V, VASS = 0.0V (V reference from VREF) 500 600 820 µA 550 600 650 µA 9 10 − Bits –AREF - VASS ≥ 2.5V − Analog input voltage Ivdd IAI1 Analog supply current Ivref Ivdd IAI2 Analog supply current Ivref 80 • Condition ADREF=0, Internal VDD RN Resolution LN Linearity error VDD=VAREF=5.0V, VASS = 0.0V 0 ±1 ±2 LSB DNL Differential nonlinear error VDD=VAREF=5.0V, VASS = 0.0V 0 ±0.5 ±0.9 LSB FSE Full scale error VDD=VAREF=5.0V, VASS = 0.0V ±0 ±1 ±2 LSB OE Offset error VDD=VAREF=5.0V, VASS = 0.0V ±0 ±1 ±2 LSB ZAI Recommended impedance of analog voltage source − 0 8 10 KΩ TAD ADC clock duration VDD=VAREF=5.0V, VASS = 0.0V 4 − − µs VDD=5.0V, VSS = 0.0V Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM (Continuation) Symbol Parameter Condition Min. Typ. Max. Unit − 15 TAD V TCN AD conversion time VDD=VAREF=5.0V, VASS = 0.0V ADIV ADC OP input voltage range VDD=VAREF=5.0V, VASS = 0.0V 0 − VAREF ADOV ADC OP output voltage swing VDD=VAREF=5.0V, VASS =0.0V, RL=10KΩ 0 0.2 0.3 4.7 4.8 5 ADSR ADC OP slew rate VDD=VAREF=5.0V, VASS = 0.0V 0.1 0.3 − V/µs PSR Power Supply Rejection VDD=5.0V±0.5V ±0 − ±2 LSB V NOTE 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. There is no current consumption when ADC is off other than minor leakage current. 3. AD conversion result will not decrease when an increase of input voltage and no missing code will result. 4. These parameters are subject to change without further notice. 8.2 Comparator Characteristics Vdd = 5.0V, Vss=0V, Ta= 0 to 70°C Symbol Parameter Condition Min. Typ. Max. Unit – 0.1 0.2 – V/µs SR Slew rate Vos Input offset voltage RL=5.1K, (Note 1) 1 5 10 mV IVR Input voltage range Vdd =5.0V, VSS = 0.0V 0 − 5 V 0.2 0.3 Output voltage swing Vd =5.0V, VSS = 0.0V, RL=10 KΩ 0 OVS 4.7 4.8 5 Ico Supply current of Comparator – – 300 – µA Vs Operating range – 2.5 − 5.5 V V NOTE 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. These parameters are subject to change without further notice. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 81 EM78P143 8-Bit Microprocessor with OTP ROM 9 AC Electrical Characteristics Ta= 0 to 70°C, VDD=5V ± 5%, VSS=0V Symbol Parameter Conditions Typ. Input CLK duty cycle Tins Instruction cycle time ”C”KS="0") Ttcc TCC input time period Tdrh Device reset hold time Ta = 25°C 11.3 16.2 /RESET pulse width Ta = 25°C 2000 – Trst 2 – Min Dclk 45 50 Crystal type 100 RC type 500 1 – (Tins+20)/N Max Unit 55 % – DC ns – DC – ns – 21.6 ns ms – ns Watchdog timer period Ta = 25°C 16.5-30% 16.5 16.5+30% ms Twdt2 Watchdog timer period Ta = 25°C 4.2-30% 4.2 4.2+30% ms Tset Input pin setup time – ns Thold Input pin hold time Tdelay Output pin delay time Tdrc ERC delay time Twdt1 3 1 2 3 – – – 0 15 20 25 ns ClOAd=20pF 45 Ta = 25°C 1 50 55 ns 3 5 ns N: Selected prescaler ratio Twdt1: The Option Word 2 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as the set-up time (18 ms). Twdt2: The Option Word 2 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as the set-up time (4.5ms). NOTE 1. These parameters are hypothetical (not tested) and are provided for design reference only. 2. Data under Minimum, Typical, and Maximum (Min., Typ., and Max.) columns are based on hypothetical results at 25°C. These data are for design reference only. 3. The Watchdog timer duration is determined by Code Option Word 2 (WDTPS). 82 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM 10 Timing Diagrams AC Test Input/Output Waveform VDD-0.5V 0.75VDD 0.75VDD 0.25VDD 0.25VDD TEST POINTS GND+0.5V AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc Figure 10-1 EM78P143 Timing Diagrams Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 83 EM78P143 8-Bit Microprocessor with OTP ROM APPENDIX A Package Type OTP MCU EM78P143MS10J/S EM78P143SO14J Package Type Pin Count Package Size MSOP 10 118 mil SOP 14 150 mil Green products do not contain hazardous substances. B Packaging Configuration Figure B-1 EM78P143MS10J/S 10-Pin MSOP Package Type 84 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM Figure B-2 EM78P143SO14J 14-Pin SOP Package Type Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 85 EM78P143 8-Bit Microprocessor with OTP ROM C How to Use the ICE 143 for EM78P143 C.1 Code Option Pin Selection with JP1 and JP2 Figure C-1 ICE 143 Indicating JP1 & JP2 Location W1 Code Option Pin Selection VCC MCEN GND JP1 is fixed to VCC (default) VCC ERS GND JP2 is fixed to VCC (default) 86 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM C.2 DIP Switch (S1 and S2) Setting Figure C-2 ICE 143 Indicating DIP Switch Location Switch Switch # Symbol Pin No. 8 1 7~6 SELE_ OPT LVR0, LVR1 C4, C3, 5~1 4~3 C2, C1, C0 RCM0, RCM1 Type Function Option bits controlled by pins or registers. 20 I 0: Option bit is controlled by pins. 1: Option bit is controlled by registers. Low Voltage Reset enable bits. 93, 94 I 26, 25, 24, 23, 22 I 95, 96 I These bits are controlled either by pins or registers depending on the SELE_OPT pin. Refer to Section 6.2.10. Calibrator of internal RC mode. These bits are controlled either by pins or registers depending on the SELE_OPT pin. Refer to Section 6.2.9. IRC mode frequency selection bits These bits are controlled either by pins or registers depending on SELE_OPT pin. Refer to Section 6.2.10. Programmable WDT time 2 2 WDTPS 31 I “0” for 4.5ms; “1” for 18ms This bit is controlled either by pins or registers depending on SELE_OPT pin. Refer to Section 6.2.10. AD Bit Select Register 1 ADBS 21 I This bit is fixed at “0”. This bit is controlled either by pins or registers depending on the SELE_OPT pin. Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 87 EM78P143 8-Bit Microprocessor with OTP ROM C.3 ICE 143 ICE Cable Connector (JP3) Pin Assignment Figure C-3a ICE 143 with its ICE Cable Connector Indicated 1 VSS 2 P56/AD6/PWM2 3 VDD 4 P55/AD5/CO/TCC 5 10 EM78P141 MS10J/S P57/RESET P51/OSCO/AD1/PWM1 9 P50/OSCI/AD0 8 P52/AD2/INT 7 P53/AD3/CIN+ 6 P54/AD4/CIN-/Vref Figure C-3b ICE 143 ICE Cable Connector Pin Assignment 88 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) EM78P143 8-Bit Microprocessor with OTP ROM C.4 ICE 143 ICE Cable to Target Pin Assignment 1 5 P57 P51 G ND P50 P56 P52 VCC P53 P55 P54 10 6 Figure C-4 ICE 143 ICE Cable to Target Pin Assignment Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice) • 89 EM78P143 8-Bit Microprocessor with OTP ROM 90 • Product Specification (V1.5) 03.15.2011 (This specification is subject to change without further notice)