TI CC2540

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TI德州仪器无线链接产品数据手册
CC2540
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信驰达简介
信驰达科技（RF-star）是一家集合方案设计功能和核心器件供应的专业本地电子元器件分销商，专注低功
耗射频 LPRF 和低功耗 MCU 领域，公司成立于 2010年，作为中国区唯一具有美国 TI 公司授予的 LPRF
Product Reseller 和 Third Party 双重资质的公司，一直引领着 LPRF 技术在国内的推广和应用，是国内唯一
一家可提供 LPRF 软硬件产品、技术支持、解决方案和核心元器件供应一条龙服务的专业化公司；
公司在美国新泽西州、中国深圳、上海、北京、天津、无锡、长沙、成都、重庆设有研发中心和办事处，
拥有资深的技术研发团队和销售团队以及 SMT 生产工厂。
无线射频器件用于低于1GHz 和2.4GHz 频段、ANT、蓝牙(Bluetooth)、低功耗蓝牙、射频识别（RFID）、
PurePath 无线音频、ZigBee、IEEE802.15.4、Zigbee RF4CE、6LoWPAN、Wi-Fi 的射频集成电路( RF IC )
和专有协议。
产品市场应用：ZigBee 无线传感网络，各种数据采集及遥测监控 (含数据, 语音,图像等),可应用于安防、
医疗、能源、水力、电力、交通监控、防盗，无线自动抄表；仪器仪表远程数据遥测、工业无线遥控；消防安
全自动报警、煤矿安全监控及人员定位；汽车防盗、胎压检测，四轮定位；无线键盘、鼠标、打印机、游戏
杆、遥控玩具、机器人等广泛的领域。适用于合乎全世界免费频段 315MHz、433 MHz、470MHz、868
MHz、915 MHz、2.4GHz，符合 FCC、CE、SGS、RoHs 认证规范,产品和信誉受到国内外顾客的一致好
评。
RF-star 将一如既往，为客户提供更多、更好的产品，更具优势的技术服务，良好的商务服务，和更完善
的物流服务。RF-star 将跨上一个新的平台，获得更大的发展空间。 RF-star 将继续本着“务实、诚信、学习、
创新”的专业精神，团结一致、奋勇开拓、锐意进取，为成为全球 无线射频技术绝对第一之产品、服务及解决
方案提供者，把科技与客户联系在一起，为供应链注入动力，并提供卓越的投资回报而不懈努力。
如果您在产品开发过程中发现技术难题以及高频困扰，竭诚欢迎来电洽询。我们将为您提供技术支持和解
决方案，让您能更快把产品推向市场。
我们深信射频技术将会得到迅速的发展与普及，我们愿意分享多年来在射频行业积累的经验与教训，为无
线的明天做出贡献。专业源于专注，科技铸就未来。
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重要特性：
● 真正的低功耗蓝牙片上系统解决方案：
● 外围设备
— 含 8 个通道和可配置分辨率的 12 位数模转
CC2540 集合低功耗蓝牙协议栈，包括外设
换
接口和广泛的传感器等。
— 集成高性能比较器
● 封装 6mm *6mm
— 通用定时器 16 字节，2 个 8 字节）
● RF 部分
— 21 个多功能 I/O 口（19*4mA.2*20mA）
— 蓝牙低功耗兼容技术
— 32kHz 休眠定时器
— 出色的链路预算（高达 97dB）,支持无外部
— 2 个串口
前段的远程应用
— 全速 USB 接口
— 精确的数据接收信号强度检测（RSSI）
— 红外发生电路
— 适用于针对世界范围内的无线电频率调节系
— 功能强大的 5 个通道直接内存访问（DMA）
统 ， 规 则 ： ETSI EN 300 328 ,EN 300 440 2 类
— AES 安全协处理器
（ 欧 洲 ）， FCC CFR47 15 部 分 ( 美 国 ),ARIB
— 电池监控和温度传感器
STD-T66(日本)
— 每个 CC2540 内涵一个唯一的 48 位 IEEE 地
● 布局
址。
— 很少外部元件
— 提供参考设计
应用：
— 6mm*6mm QFN-40 封装：
2.4G 低功耗蓝牙系统
● 低功耗
移动配件
— 接收模式低至 19.6mA
运动和健身设备
— 发送模式（-6dBm）:24mA
消费电子
— 功率模式 1（3-us 唤醒）：235uA
人机接口器件
— 功率模式 2（睡眠计时器开启）：0.9uA
USB 软件狗
— 功率模式 3:（外部中断）:0.4uA
健康和医疗
— 供电范围：2V-3.6V
— 在所有电源模式下都有 RAM 和寄存器存储
●微控制处理器
— 高性能，低功耗的 2051 内核
— 系统可编程闪存 56KB
— 静态随机存储器 8KB
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描述：
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CC2540 是一款高性价比，低功耗的正在片上系统（Soc）解决方案，适合蓝牙低耗能应用，它使低总体
物料清单成本建立强健的网络节点成为可能。CC2540 包含一个出色的工业标准的 8051 内核的 RF 收发
器，系统编程闪存记忆，8KB RAM 和其他功能强大的配套特征以及外设。 CC2540 适用于低功耗系统，
超低的睡眠模式，以及运行模式的超低功耗的转换进一步实现了超低功耗。 CC2540 有 2 中不同的版
本 :CC2540F128/F256 ， 分 别 拥 有 128 和 256KB 闪 存 记 忆 。 与 TI 的 蓝 牙 低 功 耗 协 议 栈 相 连 接 ，
CC2540F128/256 形成市场上最灵活，高性价比的单模式蓝牙低耗能解决方案。
Shenzhen RF-star Technology Co.,Ltd.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage
MIN
MAX
–0.3
3.9
V
–0.3
VDD + 0.3,
≤ 3.9
V
10
dBm
–40
85
°C
All pads, according to human-body model, JEDEC STD 22, method
A114
2
kV
According to charged-device model, JEDEC STD 22, method C101
500
V
All supply pins must have the same voltage
Voltage on any digital pin
Input RF level
Storage temperature range
ESD (2)
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CAUTION: ESD sensitive device. Precautions should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
MIN
Operating ambient temperature range, TA
MAX
UNIT
–40
85
°C
2
3.6
V
Operating supply voltage
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
Icore
Iperi
Core current consumption
Peripheral current consumption
(Adds to core current Icore for each
peripheral unit activated)
TEST CONDITIONS
MIN
TYP MAX UNIT
Power mode 1. Digital regulator on; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD
and sleep timer active; RAM and register retention
235
Power mode 2. Digital regulator off; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and
sleep timer active; RAM and register retention
0.9
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.4
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. No flash access, no RAM access.
6.7
µA
mA
Timer 1. Timer running, 32-MHz XOSC used
90
mA
Timer 2. Timer running, 32-MHz XOSC used
90
mA
Timer 3. Timer running, 32-MHz XOSC used
60
mA
Timer 4. Timer running, 32-MHz XOSC used
70
mA
Sleep timer, including 32.753-kHz RCOSC
0.6
mA
ADC, when converting
1.2
mA
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GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Power mode 1 → Active
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
4
ms
Power mode 2 or 3 → Active
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
120
ms
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
410
ms
Active → TX or RX
With 32-MHz XOSC initially on
RX/TX turnaround
160
ms
150
ms
RADIO PART
RF frequency range
Programmable in 2-MHz steps
Data rate and modulation format
1 Mbps, GFSK, 250 kHz deviation
2402
2480
MHz
TYP MAX
UNIT
RF RECEIVE SECTION
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER (1)
PARAMETER
TEST CONDITIONS
MIN
(2)
High-gain mode
–93
dBm
Receiver sensitivity (2)
Standard mode
–87
dBm
6
dBm
Receiver sensitivity
Saturation (3)
Co-channel rejection
(3)
–5
dB
Adjacent-channel rejection (3)
±1 MHz
5
dB
Alternate-channel rejection (3)
±2 MHz
30
dB
–30
dBm
Blocking (3)
Frequency error tolerance (4)
Including both initial tolerance and drift
Symbol rate error tolerance (5)
Conducted measurement with a 50-Ω single-ended load.
Spurious emission. Only largest spurious
Complies with EN 300 328, EN 300 440 class 2, FCC CFR47,
emission stated within each band.
Part 15 and ARIB STD-T-66
Current consumption
(1)
(2)
(3)
(4)
(5)
–250
250
kHz
–80
80
ppm
–75
RX mode, standard mode, no peripherals active, low MCU
activity, MCU at 250 kHz
19.6
RX mode, high-gain mode, no peripherals active, low MCU
activity, MCU at 250 kHz
22.1
dBm
mA
0.1% BER maps to 30.8% PER
The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
Results based on standard gain mode
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
Output power
Programmable output power
range
Spurious emissions
Current consumption
Optimum load impedance
(1)
TEST CONDITIONS
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
Delivered to a single-ended 50-Ω load through a balun using minimum
recommended output power setting
Delivered to a single-ended 50 Ω load through a balun
MIN
TYP
MAX
UNIT
4
dBm
–20
24
dB
Conducted measurement with a 50-Ω single-ended load. Complies
with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB
STD-T-66 (1)
–41
dBm
TX mode, –23-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
21.1
TX mode, –6-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
23.8
mA
TX mode, 0-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
27
TX mode, 4-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
31.6
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
70 + j30
Ω
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC resonator in front of the
antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect both from the signal trace to a good RF ground.
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32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32
Crystal frequency accuracy
requirement (1)
UNIT
MHz
–40
40
ppm
ESR
Equivalent series resistance
6
60
Ω
C0
Crystal shunt capacitance
1
7
pF
CL
Crystal load capacitance
10
Start-up time
Power-down guard time
(1)
16
0.25
The crystal oscillator must be in power down for a
guard time before it is used again. This
requirement is valid for all modes of operation. The
need for power-down guard time can vary with
crystal type and load.
pF
ms
3
ms
Including aging and temperature dependency, as specified by [1]
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
TYP
MAX
32.768
Crystal frequency accuracy
requirement (1)
–40
UNIT
kHz
40
ppm
ESR
Equivalent series resistance
40
130
kΩ
C0
Crystal shunt capacitance
0.9
2
pF
Crystal load capacitance
12
16
pF
Start-up time
0.4
CL
(1)
s
Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with Tw = 25°C and VDD = 3 V.
PARAMETER
Calibrated frequency
(1)
Temperature coefficient (2)
(3)
Calibration time (4)
(1)
(2)
(3)
(4)
MIN
TYP
32.753
Frequency accuracy after calibration
Supply-voltage coefficient
TEST CONDITIONS
MAX
UNIT
kHz
±0.2%
0.4
%/°C
3
%/V
2
ms
The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
Frequency drift when temperature changes after calibration
Frequency drift when supply voltage changes after calibration
When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
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16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
Frequency (1)
TYP
MAX
16
Uncalibrated frequency accuracy
±18%
Calibrated frequency accuracy
±0.6%
UNIT
MHz
Start-up time
10
ms
Initial calibration time (2)
50
ms
(1)
(2)
The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
Useful RSSI range (1)
Absolute uncalibrated RSSI accuracy (1)
MIN
MAX
UNIT
High-gain mode
–99 to –44
Standard mode
–90 to –35
High-gain mode
±4
dB
1
dB
Step size (LSB value)
(1)
TYP
dBm
Assuming CC2540 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
Phase noise, unmodulated
carrier
TEST CONDITIONS
MIN
TYP
At ±1-MHz offset from carrier
–109
At ±3-MHz offset from carrier
–112
At ±5-MHz offset from carrier
–119
MAX
UNIT
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
Output
Temperature coefficient
Voltage coefficient
Initial accuracy without calibration
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
MIN
TYP
MAX
UNIT
1480
12-bit
4.5
mv/°C
1
/ 0.1 V
±10
°C
Accuracy using 1-point calibration
±5
°C
Current consumption when enabled
0.5
mA
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OP-AMP CHARACTERISTICS
TA = 25°C, VDD = 3 V, . All measurement results are obtained using the CC2540 reference designs post-calibration.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x03, OPAMPC = 0x01
Output maximum voltage
VDD – 0.07
Output minimum voltage
0.07
V
Open-loop gain
108
dB
Gain-bandwidth product
Slew rate
CMRR
V
2
MHz
107
V/ms
Input maximum voltage
VDD + 0.13
Intput minimum voltage
–55
mV
V
mV
Input offset voltage
40
Common-mode rejection ratio
90
dB
Supply current
0.4
mA
Input noise voltage
f = 0.01 Hz to 1 Hz
1.1
f = 0.1 Hz to 10 Hz
1.7
nV/√(Hz)
Non-Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x00, OPAMPC = 0x01
Output maximum voltage
VDD – 0.07
Output minimum voltage
0.07
V
Open-loop gain
108
dB
Gain-bandwidth product
Slew rate
CMRR
V
2
MHz
107
V/ms
Input maximum voltage
VDD + 0.13
Intput minimum voltage
–55
mV
Input offset voltage
0.8
mV
Common-mode rejection ratio
90
dB
Supply current
0.4
mA
Input noise voltage
f = 0.01 Hz to 1 Hz
60
f = 0.1 Hz to 10 Hz
65
V
nV/√(Hz)
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2540 reference designs, post-calibration.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Common-mode maximum voltage
VDD
Common-mode minimum voltage
–0.3
Input offset voltage
Offset vs temperature
Offset vs operating voltage
UNIT
V
1
mV
16
µV/°C
4
mV/V
Supply current
230
nA
Hysteresis
0.15
mV
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ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
Input voltage
ENOB (1)
0
VDD
V
VDD
V
Input resistance, signal
Simulated using 4-MHz clock speed
197
kΩ
Full-scale signal (1)
Peak-to-peak, defines 0 dBFS
2.97
V
Effective number of bits
Single-ended input, 7-bit setting
5.7
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
9.3
Single-ended input, 12-bit setting
10.3
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
10-bit setting, clocked by RCOSC
9.7
12-bit setting, clocked by RCOSC
10.9
bits
7-bit setting, both single and differential
0–20
Single ended input, 12-bit setting, –6
dBFS (1)
–75.2
Differential input, 12-bit setting, –6
dBFS (1)
–86.6
Single-ended input, 12-bit setting (1)
70.2
Differential input, 12-bit setting (1)
79.3
Single-ended input, 12-bit setting, –6
dBFS (1)
78.8
Differential input, 12-bit setting, –6
dBFS (1)
88.9
Common-mode rejection ratio
Differential input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
>84
dB
Crosstalk
Single ended input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
>84
dB
Offset
Midscale
–3
mV
Total harmonic distortion
Differential nonlinearity
Signal-to-noise-and-distortion
kHz
dB
dB
0.68%
12-bit setting, mean (1)
0.05
12-bit setting, maximum (1)
0.9
13.3
12-bit setting, mean, clocked by RCOSC
10
LSB
29
Single ended input, 7-bit setting (1)
35.4
Single ended input, 9-bit setting (1)
46.8
Single ended input, 10-bit setting (1)
57.5
Single ended input, 12-bit setting (1)
66.6
(1)
40.7
Differential input, 9-bit setting (1)
51.6
Differential input, 10-bit setting (1)
61.8
Differential input, 12-bit setting (1)
70.8
Differential input, 7-bit setting
LSB
4.6
12-bit setting, maximum (1)
12-bit setting, max, clocked by RCOSC
(1)
V
0
Integral nonlinearity
SINAD
(–THD+N)
UNIT
VDD
VDD is voltage on AVDD5 pin
12-bit setting, mean (1)
INL
MAX
VDD is voltage on AVDD5 pin
Gain error
DNL
TYP
0
External reference voltage
Signal to nonharmonic ratio
CMRR
MIN
External reference voltage differential
Useful power bandwidth
THD
TEST CONDITIONS
VDD is voltage on AVDD5 pin
dB
Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
7-bit setting
Conversion time
MAX
UNIT
20
9-bit setting
36
10-bit setting
68
12-bit setting
132
Power consumption
ms
1.2
Internal reference VDD coefficient
mA
4
Internal reference temperature coefficient
Internal reference voltage
mV/V
0.4
mV/10°C
1.15
V
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
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SPI AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
t1
TEST CONDITIONS
SCK period
SCK duty cycle
MIN
Master, RX and TX
250
Slave, RX and TX
250
Master
TYP MAX
UNIT
ns
50%
Master
63
Slave
63
t2
SSN low to SCK
t3
SCK to SSN high
t4
MOSI early out
Master, load = 10 pF
t5
MOSI late out
Master, load = 10 pF
t6
MISO setup
Master
90
ns
t7
MISO hold
Master
10
ns
Master
63
Slave
63
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
t11
MOSI hold
Slave
10
t9
MISO late out
Slave, load = 10 pF
Operating frequency
ns
ns
7
ns
10
ns
50%
ns
ns
ns
95
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
ns
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
X
t5
X
D1
t7
D0
X
T0478-01
Figure 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
X
t9
D1
t11
D0
X
T0479-01
Figure 3. SPI Slave AC Characteristics
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DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
fclk_dbg
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
Debug clock frequency (see Figure 4)
t1
Allowed high pulse on clock (see Figure 4)
35
ns
t2
Allowed low pulse on clock (see Figure 4)
35
ns
t3
EXT_RESET_N low to first falling edge on debug
clock (see Figure 6)
167
ns
t4
Falling edge on clock to EXT_RESET_N high (see
Figure 6)
83
ns
t5
EXT_RESET_N high to first debug command (see
Figure 6)
83
ns
ns
t6
Debug data setup (see Figure 5)
2
t7
Debug data hold (see Figure 5)
4
t8
Clock-to-data delay (see Figure 5)
ns
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4. Debug Clock – Basic Timing
Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 5. Debug Enable Timing
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Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2540)
P2_1
DEBUG_DATA
(from CC2540)
P2_1
t6
t8
t7
T0438-02
Figure 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
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MIN
1.5
TYP
MAX
UNIT
tSYSCLK
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DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Logic-0 input voltage
Logic-1 input voltage
MAX
V
50
nA
2.5
Logic-0 input current
Input equals 0 V
–50
Logic-1 input current
Input equals VDD
–50
I/O-pin pullup and pulldown resistors
V
50
20
Logic-0 output voltage, 4- mA pins
Output load 4 mA
Logic-1 output voltage, 4-mA pins
Output load 4 mA
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nA
kΩ
0.5
2.4
UNIT
0.5
V
V
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DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2540 pinout is shown in Figure 7 and a short description of the pins follows.
DVDD1
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3 / XOSC32K_Q2
P2_4 / XOSC32K_Q1
40
39
38
37
36
35
34
33
32
AVDD6
DCOUPL
CC2540
RHA Package
(Top View)
31
30
R_BIAS
2
29
AVDD4
3
28
AVDD1
DVDD_USB
4
27
AVDD2
P1_5
5
26
RF_N
P1_4
6
25
RF_P
P1_3
7
24
AVDD3
P1_2
8
23
XOSC_Q2
P1_1
9
22
XOSC_Q1
12
13
14
15
16
17
18
19
P0_3
P0_2
P0_1
P0_0
21
20
AVDD5
RESET_N
10
11
P0_4
DVDD2
AGND
Ground Pad
P0_5
USB_N
P0_6
USB_P
P1_0
1
P0_7
DGND_USB
P0076-05
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 7. Pinout Top View
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PIN DESCRIPTIONS
PIN NAME
PIN
PIN TYPE
DESCRIPTION
AVDD1
28
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD2
27
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD3
24
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD4
29
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD5
21
Power (analog)
2-V–3.6-V analog power-supply connection
AVDD6
31
Power (analog)
2-V–3.6-V analog power-supply connection
DCOUPL
40
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DGND_USB
1
Ground pin
Connect to GND
DVDD_USB
4
Power (digital)
2-V–3.6-V digital power-supply connection
DVDD1
39
Power (digital)
2-V–3.6-V digital power-supply connection
DVDD2
10
Power (digital)
2-V–3.6-V digital power-supply connection
GND
—
Ground
The ground pad must be connected to a solid ground plane.
P0_0
19
Digital I/O
Port 0.0
P0_1
18
Digital I/O
Port 0.1
P0_2
17
Digital I/O
Port 0.2
P0_3
16
Digital I/O
Port 0.3
P0_4
15
Digital I/O
Port 0.4
P0_5
14
Digital I/O
Port 0.5
P0_6
13
Digital I/O
Port 0.6
P0_7
12
Digital I/O
Port 0.7
P1_0
11
Digital I/O
Port 1.0 – 20-mA drive capability
P1_1
9
Digital I/O
Port 1.1 – 20-mA drive capability
P1_2
8
Digital I/O
Port 1.2
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
Digital I/O
Port 1.6
P1_7
37
Digital I/O
Port 1.7
P2_0
36
Digital I/O
Port 2.0
P2_1
35
Digital I/O
Port 2.1
P2_2
34
Digital I/O
Port 2.2
P2_3/
XOSC32K_Q2
33
Digital I/O,
Analog I/O
Port 2.3/32.768 kHz XOSC
P2_4/
XOSC32K_Q1
32
Digital I/O,
Analog I/O
Port 2.4/32.768 kHz XOSC
RBIAS
30
Analog I/O
External precision bias resistor for reference current
RESET_N
20
Digital input
Reset, active-low
RF_N
26
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
25
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
USB_N
3
Digital I/O
USB N
USB_P
2
Digital I/O
USB P
XOSC_Q1
22
Analog I/O
32-MHz crystal oscillator pin 1 or external-clock input
XOSC_Q2
23
Analog I/O
32-MHz crystal oscillator pin 2
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BLOCK DIAGRAM
A block diagram of the CC2540 is shown in Figure 8. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
XOSC_Q2
32-MHz
CRYSTAL OSC
XOSC_Q1
P2_4
32.768-kHz
CRYSTAL OSC
P2_3
P2_2
HIGHSPEED
RC-OSC
DEBUG
INTERFACE
P2_1
DCOUPL
POWER-ON RESET
BROWN OUT
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
WATCHDOG
TIMER
RESET_N
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_0
PDATA
P1_7
P1_6
XRAM
8051 CPU
CORE
P1_5
IRAM
P1_4
SFR
RAM
SRAM
FLASH
FLASH
MEMORY
ARBITRATOR
P1_3
P1_2
DMA
P1_1
UNIFIED
P1_0
IRQ CTRL
FLASH CTRL
P0_7
P0_6
1 KB SRAM
FIFOCTRL
ANALOG COMPARATOR
P0_5
Radio Arbiter
P0_4
OP-AMP
P0_2
AES
ENCRYPTION
AND
DECRYPTION
DS
ADC
AUDIO/DC
RADIO REGISTERS
Link Layer Engine
SFR Bus
P0_0
I/O CONTROLLER
P0_1
SRAM
DEMODULATOR
SYNTH
P0_3
MODULATOR
USB_N
USB_P
USB
RECEIVE
USART 1
FREQUENCY
SYNTHESIZER
USART 0
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
DIGITAL
ANALOG
TIMER 4 (8-Bit)
MIXED
B0301-05
Figure 8. CC2540 Block Diagram
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BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 8 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power modes 2 and
3).
The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2540 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth
specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2540 back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform
in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power modes 1
or 2.
A built-in watchdog timer allows the CC2540 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer used by the Bluetooth low energy stack. It has a 16-bit counter with a configurable timer
period and a 24-bit overflow counter that can be used to keep track of the number of periods that have
transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is
received/transmitted or the exact time at which transmission ends. There are two 16-bit timer-compare registers
and two 24-bit overflow-compare registers that can be used to give exact timing for start of RX or TX to the radio
or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a
single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC. Both inputs as well as
the output are available on pins, so the feedback network is fully customizable. A chopper-stabilized mode is
available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
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TYPICAL CHARACTERISTICS
RX CURRENT IN WAIT FOR SYNC
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
32.5
20.5
32
Current (mA)
20
Current (mA)
TX Power Setting = 4 dBm
VCC = 3 V
Gain = Standard Setting
Input = -70 dBm
VCC = 3 V
19.5
31.5
31
19
18.5
-40
-20
0
20
40
Temperature (°C)
60
30.5
-40
80
-20
0
G001
20
40
Temperature (°C)
Figure 9.
Figure 10.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
60
80
G002
7
-83
Gain = Standard Setting
VCC = 3 V
-84
TX Power Setting = 4 dBm
VCC = 3 V
6
-85
5
Level (dBm)
Level (dBm)
-86
-87
-88
-89
4
3
2
-90
1
-91
-92
-40
-20
0
20
40
Temperature (°C)
60
0
-40
80
0
20
40
Temperature (°C)
Figure 11.
Figure 12.
RX CURRENT IN WAIT FOR SYNC
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
19.7
60
80
G004
32
Gain = Standard Setting
Input = -70 dBm
T A = 25°C
19.68
19.66
T A = 25°C
TX Power Setting = 4 dBm
31.9
31.8
19.64
31.7
Current (mA)
Current (mA)
-20
G003
19.62
19.6
19.58
31.6
31.5
31.4
19.56
31.3
19.54
31.2
19.52
31.1
19.5
31
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
Figure 13.
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3.2
3.4
3.6
G005
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
G006
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
SUPPLY VOLTAGE
TX POWER
vs
SUPPLY VOLTAGE
5
-87
Gain = Standard Setting
T A = 25°C
-87.4
4.6
-87.6
4.4
-87.8
-88
-88.2
4.2
4
3.8
-88.4
3.6
-88.6
3.4
-88.8
3.2
3
-89
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
2
3.6
-87.4
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
Figure 15.
Figure 16.
RX SENSITIVITY
vs
FREQUENCY
RX INTERFERER REJECTION (SELECTIVITY)
vs
INTERFERER FREQUENCY
G008
60
Gain = Standard Setting
T A = 25°C
VCC = 3 V
50
40
Rejection (dB)
-87.6
Level (dBm)
2.2
G007
-87
-87.2
T A = 25°C
TX Power Setting = 4 dBm
4.8
Level (dBm)
Level (dBm)
-87.2
-87.8
-88
-88.2
30
20
-88.4
Gain = Standard Setting
T A = 25°C
VCC = 3 V
Wanted Signal at 2426 MHz
with -67 dBm Level
10
-88.6
0
-88.8
-89
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
-10
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G009
Figure 17.
G010
Figure 18.
TX POWER
vs
FREQUENCY
5
4.8
4.6
T A = 25°C
TX Power Setting = 4 dBm
VCC = 3 V
Level (dBm)
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G011
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Table 1. Output Power and Current Consumption (1) (2)
(1)
(2)
Typical Output Power (dBm)
Typical Current Consumption (mA)
4
32
0
27
–6
24
–23
21
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz.
The transmitter output power setting is programmable using a TI BLE stack vendor-specific API command. The default value is 0 dBm.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2540. A typical application circuit is shown in
Figure 20.
Optional 32-kHz Crystal
(1)
C331
2-V to 3.6-V Power Supply
XTAL2
C401
2
USB_P
3
USB_N
4
DVDD_USB
5
P1_5
6
P1_4
8
P1_2
9
P2_2 34
P2_1 35
P2_0 36
P1_7 37
P1_6 38
AVDD6 31
R301
RBIAS 30
L251
AVDD4 29
AVDD1 28
C251
Antenna
(50 W)
C252
AVDD2 27
L252
RF_N 26
L253
CC2540
RF_P 25
DIE ATTACH PAD
C261
L261
AVDD3 24
XOSC_Q2 23
C262
C253
XOSC_Q1 22
P1_1
19 P0_0
17 P0_2
18 P0_1
16 P0_3
15 P0_4
14 P0_5
13 P0_6
12 P0_7
11 P1_0
10 DVDD2
20 RESET_N
7
P1_3
P2_4/XOSC32K_Q1 32
DGND_USB
P2_3/XOSC32K_Q2 33
1
DVDD1 39
DCOUPL 40
C321
AVDD5
21
XTAL1
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
C221
C231
S0383-03
(1) 32-kHz crystal is mandatory when running the chip in low-power modes, except if the link layer is in the standby
state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 20. CC2540 Application Circuit
Table 2. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
Description
Value
C221
32-MHz xtal loading capacitor
12 pF
C231
32-MHz xtal loading capacitor
12 pF
C251
Part of the RF matching network
18 pF
C252
Part of the RF matching network
1 pF
C253
Part of the RF matching network
1 pF
C261
Part of the RF matching network
18 pF
C262
Part of the RF matching network
1 pF
C321
32-kHz xtal loading capacitor
15 pF
C331
32-kHz xtal loading capacitor
15 pF
C401
Decoupling capacitor for the internal digital regulator
1 µF
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Table 2. Overview of External Components (Excluding Supply Decoupling Capacitors) (continued)
Component
Description
Value
L251
Part of the RF matching network
2 nH
L252
Part of the RF matching network
1 nH
L253
Part of the RF matching network
3 nH
L261
Part of the RF matching network
2 nH
R301
Resistor used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shown
consists of C262, L261, C252, and L252.
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. Bluetooth® Core Technical Specification document, version 4.0
http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2540
System-on-Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and
standard-based wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
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In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and university
programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance
to interact with fellow engineers from all over the world.
With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas
Instruments offers the broadest low-power RF portfolio. We make RF easy!
The following subsections point to where to find more information.
Texas Instruments Low-Power RF Web Site
•
•
•
Forums, videos, and blogs
RF design help
E2E interaction
Join us today at www.ti.com/lprf-forum.
Texas Instruments Low-Power RF Developer Network
Texas Instruments has launched an extensive network of low-power RF development partners to help customers
speed up their application development. The network consists of recommended companies, RF consultants, and
independent design houses that provide a series of hardware module products and design services, including:
• RF circuit, low-power RF, and ZigBee® design services
• Low-power RF and ZigBee module solutions and development tools
• RF certification services and RF circuit manufacturing
Need help with modules, engineering services or development tools?
Search the Low-Power RF Developer Network tool to find a suitable partner.
www.ti.com/lprfnetwork
Low-Power RF eNewsletter
The Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, and
other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles
include links to get more online information.
Sign up today on
www.ti.com/lprfnewsletter
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CC2540F128RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
CC2540F128RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
CC2540F256RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
CC2540F256RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CC2540F128RHAR
VQFN
RHA
40
CC2540F128RHAT
VQFN
RHA
CC2540F256RHAR
VQFN
RHA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
40
250
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2540F128RHAR
VQFN
RHA
40
2500
333.2
345.9
28.6
CC2540F128RHAT
VQFN
RHA
40
250
333.2
345.9
28.6
CC2540F256RHAR
VQFN
RHA
40
2500
333.2
345.9
28.6
Pack Materials-Page 2
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重要声明
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可访问以下URL 地址以获取有关其它TI 产品和应用解决方案的信息：
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
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www.ti.com.cn/amplifiers
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www.ti.com.cn/computer
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www.ti.com.cn/dataconverters
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www.dlp.com
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www.ti.com/energy
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www.ti.com.cn/dsp
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www.ti.com.cn/industrial
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www.ti.com.cn/clockandtimers
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www.ti.com.cn/medical
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www.ti.com.cn/interface
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www.ti.com.cn/security
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www.ti.com.cn/logic
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www.ti.com.cn/automotive
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www.ti.com.cn/power
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www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
www.deyisupport.com
IMPORTANT NOTICE
OMAP 机动性处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
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