INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT594 8-bit shift register with output register Product specification File under Integrated Circuits, IC06 December 1991 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 FEATURES DESCRIPTION • Synchronous serial input and output The 74HC/HCT594 are high-speed, Si-gate CMOS devices, and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC/HCT594 contain an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clears are provided on both the shift and storage registers. A serial output (Q7’) is provided for cascading purposes. • 8-bit parallel output • Shift and storage register have independent direct clear and clocks • 100 MHz (typ.) • Output capability: – parallel outputs: bus driver – serial outputs: standard • ICC category: MSI Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. APPLICATIONS • Serial-to parallel data conversion • Remote control holding register QUICK REFERENCE DATA GND = 0 V: Tamb = 250 C; tr = tf = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/tPLH propagation delay HCT CL = 15 pF; VCC = 5 V SHCP to Q7’ 13 15 ns STCP to Qn 13 15 ns SHR to Qn 11 14 ns STR to Qn 11 14 ns 100 100 MHz 3.5 3.5 pF 84 89 pF fmax maximum clock frequency SHCP, STCP CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo), where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of the outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 2. For HC, the condition is VI = GND to VCC; for HCT, the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION PACKAGES EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE PC74HC/HCT594P 16 DIL plastic SOT38C, P PC74HC/HCT594T 16 SO plastic SOT109A December 1991 2 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 PINNING SYMBOL PIN DESCRIPTION Q0 to Q7 15 & 1 to 7 parallel data outputs GND 8 ground (0 V) Q7’ 9 serial data output SHR 10 shift register reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input STR 13 storage register reset active (LOW) Ds 14 serial data input VCC 16 supply voltage 11 12 halfpage ge SH CP ST CP Q7' 14 DS ST R ge 9 Q1 1 16 V CC 15 Q 0 Q0 15 Q2 2 Q1 1 Q3 3 14 D S Q2 2 Q4 4 13 ST R Q3 3 Q4 4 Q5 5 Q6 6 11 SH CP Q6 6 Q7 10 SH R Q7 7 SH R ST R 10 13 Q5 5 594 ST CP SH R SH CP DS 13 R2 12 10 11 14 C2 R 1 SRG8 C1/ 1D 2D 12 ST CP 7 GND 8 9 Q7' MBC318 MBC319 Fig.1 Logic symbol. December 1991 MBC322 - 1 Fig.2 Pin configuration. 3 Fig.3 IEC logic symbol. 15 Q 0 1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 9 Q7' Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 handbook, halfpage 14 D S SHCP 11 8-STAGE SHIFT REGISTER 10 SH R Q7' 9 ST CP 12 8-BIT STORAGE REGISTER 13 ST R Q 0 Q1 Q 2 Q 3 Q4 Q 5 Q 6 Q 7 15 1 2 3 4 5 6 7 MBC320 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS FUNCTION SHCP STCP SHR STR DS Q7’ Qn X X L X X L NC a LOW level on SHR only affects the shift registers. X X X L X NC L a LOW level on STR only affects the storage registers. X ↑ L H X L L empty shift register loaded into storage register. ↑ X H X H Q6’ NC logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’). X ↑ H H X NC Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages. ↑ ↑ H H X Q6n Qn’ contents of shift register shifted through. Previous contents of shift register transferred to the storage register and the parallel output stages. Note 1. H = HIGH voltage level L = LOW voltage level ↑ = LOW-to-HIGH transition NC = no change X = don’t care. December 1991 4 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 handbook, full pagewidth STAGE 0 DS D STAGE 7 STAGES 1 TO 6 Q D Q FFSH 0 D Q7' Q FFSH 7 CP CP R R SHCP SH R D D Q FFST 0 Q FFST 7 CP CP R R ST CP ST R Q0 Q 1 Q 2 Q3 Q 4 Q 5 Q6 Q7 MBC321 - 1 Fig.5 Logic diagram. handbook, SHfull CPpagewidth DS ST CP SH R ST R Q0 Q1 Q6 Q7 Q 7' MBC323 - 1 Fig.6 Timing diagram. December 1991 5 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 DC CHARACTERISTICS FOR 74HC For the DC characteristics, see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard. ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) min. typ. max. min. −40 to +125 UNIT VCC (V) max. min. max. propagation delay SHCP to Q7’ − − − 44 16 14 150 30 26 − − − 185 37 31 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.7 propagation delay STCP to Qn − − − 44 16 14 150 30 26 − − − 185 37 31 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.8 propagation delay SHR to Q7’ − − − 39 14 12 150 30 26 − − − 185 37 31 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.11 propagation delay STR to Qn − − − 39 14 12 125 25 21 − − − 155 31 26 − − − 185 37 31 ns ns ns 2.0 4.5 6.0 Fig.12 shift clock pulse width 80 HIGH or LOW 16 14 10 4 3 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.7 storage clock pulse width HIGH or LOW 80 16 14 10 4 3 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.8 shift and storage reset 80 pulse width HIGH or 16 LOW 14 14 5 4 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.11 and Fig.12 set-up time Ds to SHCP 100 20 17 10 4 3 − − − 125 25 21 − − − 150 30 26 − − − ns ns ns 2.0 4.5 6.0 Fig.9 set-up time SHR to STCP 100 20 17 14 5 4 − − − 125 25 21 − − − 150 30 26 − − − ns ns ns 2.0 4.5 6.0 Fig.10 set-up time SHCP to STCP 100 20 17 17 6 5 − − − 125 25 21 − − − 150 30 26 − − − ns ns ns 2.0 4.5 6.0 Fig.8 SYMBOL tPHL/tPLH tPHL tW tsu TEST CONDITIONS December 1991 −40 to +85 +25 PARAMETER 6 WAVEFORMS Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 Tamb (°C) SYMBOL PARAMETER TEST CONDITIONS −40 to +85 +25 min. typ. max. min. −40 to +125 UNIT VCC (V) max. min. max. WAVEFORMS th hold time Ds to SHCP 25 5 4 −8 −3 −2 − − − 30 6 5 − − − 35 7 6 − − − ns ns ns 2.0 4.5 6.0 Fig.9 trem removal time SHR to SHCP, STR to STCP 50 10 9 −14 −5 −4 − − − 65 13 11 − − − 75 15 13 − − − ns ns ns 2.0 4.5 6.0 Fig.11 and Fig.12 fmax maximum clock frequency SHCP or STCP 6.0 30 35 30 92 109 − − − 4.8 24 28 − − − 4.0 20 24 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.7 and Fig.8 December 1991 7 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 Note to HCT types DC CHARACTERISTICS FOR 74HCT The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the following table. For the DC characteristics, see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard. UNIT LOAD COEFFICIENT INPUT ICC category: MSI. Ds 0.25 SHR 1.50 SHCP 1.50 STCP 1.50 STR 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) TEST CONDITIONS min. typ. max. min. −40 to +125 UNIT VCC (V) max. min. max. propagation delay SHCP to Q7’ − 18 32 − 40 − 48 ns 4.5 Fig.7 propagation delay STCP to Qn − 18 32 − 40 − 48 ns 4.5 Fig.8 propagation delay SHR to Q7’ − 17 30 − 38 − 45 ns 4.5 Fig.11 propagation delay STR to Qn − 17 30 − 38 − 45 ns 4.5 Fig.12 shift clock pulse width HIGH or LOW 16 4 − 20 − 24 − ns 4.5 Fig.7 storage clock pulse width HIGH or LOW 16 4 − 20 − 24 − ns 4.5 Fig.8 shift and storage reset pulse width HIGH or LOW 16 6 − 20 − 24 − ns 4.5 Fig.11 and Fig.12 set-up time Ds to SHCP 20 4 − 25 − 30 − ns 4.5 Fig.9 set-up time SHR to STCP 20 6 − 25 − 30 − ns 4.5 Fig.10 set-up time SHCP to STCP 20 7 − 25 − 30 − ns 4.5 Fig.8 th hold time Ds to SHCP 5 −3 − 6 − 7 − ns 4.5 Fig.9 trem removal time SHR to SHCP, STR to STCP 10 −5 − 13 − 15 − ns 4.5 Fig.11 and Fig.12 fmax maximum clock frequency SHCP or STCP 30 92 − 24 − 20 − MHz 4.5 Fig.7 and Fig.8 SYMBOL tPHL/tPLH tPHL tW tsu December 1991 −40 to +85 +25 PARAMETER 8 WAVEFORMS Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 AC WAVEFORMS SH CP INPUT VM (1) t su ST CP INPUT 1/ f max V M (1) tW t PHL t PLH Q n OUTPUTS V M (1) MLA512 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V Fig.8 Fig.7 Waveforms showing the shift clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and the maximum shift clock frequency. Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width, maximum storage clock frequency and the shift clock to storage clock set-up time. handbook, halfpage SH R INPUT VM (1) t su ST CP INPUT V M (1) Q n OUTPUTS V M (1) MBC326 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V Fig.9 Fig.10 Waveforms showing the set-up time from shift reset (SHR) to storage clock (STCP). Waveforms showing the data set-up and hold times for the Ds input. December 1991 9 Philips Semiconductors Product specification 8-bit shift register with output register handbook, halfpage handbook, halfpage SH R INPUT 74HC/HCT594 VM (1) ST R INPUT tW tW t rem VM (1) SH CP INPUT t rem VM (1) ST CP INPUT t PHL t PHL Q 7' OUTPUT VM (1) VM (1) Q n OUTPUTS VM (1) MBC324 MBC325 - 1 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V Fig.11 Waveforms showing the shift reset (SHR) pulse width, the shift reset to output (Q7’) propagation delay and the shift reset to shift clock (SHCP) removal time. Fig.12 Waveforms showing the storage reset (STR) pulse width, the storage reset to outputs (Qn) propagation delay and the storage reset to storage clock (STCP) removal time. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1991 10