FUJITSU SEMICONDUCTOR FACT SHEET NP05-13110-8E FRAM MB85RC128 MB85RC128 is a 128K-bits FRAM LSI with serial interface (I2C), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. ■ FEATURES Bit configuration ：16,384 words × 8 bits Two-wire serial interface ：Fully controllable by two ports: serial clock(SCL) and serial data(SDA) Operating frequency ：400 kHz (Max.) Read/write endurance ：1012 times / byte Data retention ：10 years (+85℃), 95 years (+55℃), over 200 years (+35℃) Operating power supply voltage ：2.7V to 3.6V Low power consumption ：Operating current 100μA (Typ＠400kHz), Standby current 5μA (Typ.) Operation ambient temperature range：-40℃ to +85℃ Package ：8-pin plastic SOP (FPT-8P-M02) RoHS compliant ■ ORDERING INFORMATION Product name Package Shipping form MB85RC128PNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube MB85RC128PNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Embossed Carrier tape ■ PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) 2013.5 1/2 Copyright©2010-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RC128 ■ PIN ASSIGNMENT Pin No. (TOP VIEW) Pin name Description Device Address pins A0 1 8 VDD A1 2 7 WP A2 3 6 SCL 4 VSS 5 1 to 3 A0 to A2 4 VSS 5 SDA 6 SCL MB85RC64 can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pin matches a Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A0, A1, and A2 are internally pulled-down and recognized as the "L" level. Ground pin Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the external circuit. SDA Serial Clock pin This is a clock input pin for input/output serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin 7 WP 8 VDD When Write Protect pin is the "H" level, writing operation is disabled. When Write Protect pin is the "L" level, the entire memory region can be overwritten. Reading operation is always enabled regardless of Write Protect pin input level. The Write Protect pin is internally pulled down to VSS pin, and that is recognized as the "L" level (write enabled) when the pin is the open state. Supply Voltage pin ■ BLOCK DIAGRAM Control Logic SCL WP Row Decoder Serial/Parallel Converter Address Counter SDA FRAM Array 16,384 × 8 Column Decoder/Sense Amp./ Write Amp. A0, A1, A2 ■ I2C The MB85RC128 has the two-wire serial interface; the I2C bus, and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, an I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is Pull-up Resistors necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. VDD SCL SDA I2C Bus Master I2C Bus MB85RC128 I2C Bus MB85RC128 I2C Bus MB85RC128 A2 0 A2 0 A2 0 A1 0 A0 0 A1 0 A0 1 A1 1 ... A0 0 Device address NP05-13110-8E 2013.5 2/2 Copyright©2010-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved