AK4958 English Datasheet - Brief

[AK4958]
AK4958
24bit Stereo CODEC with MIC/SPK/VIDEO-AMP & LDO
GENERAL DESCRIPTION
The AK4958 is a 24-bit stereo CODEC with a microphone, speaker, video amplifiers and LDO. The input
circuits include a microphone amplifier and the output circuits include a speaker amplifier. It is suitable for
portable application with recording/playback function. A one channel composite In/Out video amplifier is
also integrated. The AK4958 is available in a small 32-pin BGA (3.5mm x 3.5mm, 0.5mm pitch:
AK4958EG) and a 25-pin CSP (2.2mm x 2.2mm, 0.4mm pitch: AK4958ECB) packages saving mounting
area on the board.
FEATURES
1. Recording Functions
 Analog Input
(AK4958EG)
Stereo Single-ended input with two Selectors
(AK4958ECB)
Stereo Single-ended input
 Microphone Amplifier
(+30dB, +25dB, +21dB, +18dB, +15dB, +12dB, +6dB, 0dB)
 Digital ALC (Automatic Level Control)
- Setting Range: +36dB  52.5dB, 0.375dB Step & Mute
- Motor Noise Reduction Circuit
 ADC Performance: S/(N+D): 83dB, DR, S/N: 88dB (MIC-Amp=+18dB)
S/(N+D): 85dB, DR, S/N: 96dB (MIC-Amp=0dB)
 Microphone Sensitivity Compensation (with Moving Average Data Output Circuit)
 Automatic Wind Noise Reduction Filter
 5-Band Notch Filter
Include Dynamic Gain Control
 Stereo Separation Emphasis Circuit
 Digital Microphone Interface
2. Playback Functions
 Soft Mute
 Digital ALC (Automatic Level Control)
- Setting Range: +36dB ~ 52.5dB, 0.375dB Step & Mute
 Digital Volume Control
- +6dB ~ 89.5dB, 0.5dB Step & Mute)
 Stereo Separation Emphasis Circuit
 Stereo Line Output
- Output Voltage: 1Vrms (AVDD= 3.3V)
- S/(N+D): 85dB
- S/N: 92dB
 Mono Mixing Output
 Mono Speaker-Amplifier
- S/(N+D): [email protected], [email protected],
- S/N: 90dB
- BTL Output
- Output Power: [email protected] (AVDD=3.3V)
 Analog Mixing: BEEP Input
 Bass Boost Circuit
 3-band Dynamic Range Control Circuit
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[AK4958]
3. Master Clock:
Reference Clock Input Frequency
(1) MCKI Reference PLL Mode
Frequencies: 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
(2) BICK Reference PLL Mode
Frequencies: 32fs or 64fs (BICK pin)
(3) External Clock Mode
Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
Output Master Clock Frequency: 64fs/128fs/256fs/512fs
4. Sampling Frequencies
 MCKI Reference PLL Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
 BICK Reference PLL Master Mode:
8kHz ~ 48kHz
 EXT Mode:
7.35kHz ~ 48kHz (256fs), 7.35kHz  48kHz (512fs), 7.35kHz  13kHz (1024fs)
5. Master/Slave Mode
6. P I/F:
(AK4958EG)
 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode)
(AK4958ECB)
 I2C Bus (Ver 1.0, 400kHz Fast-Mode)
7. Master/Slave Mode
8. Audio Interface Format: MSB First, 2’s complement
 ADC: 24bit MSB justified, 16/24bit I2S
 DAC: 24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 24bit I2S
9. Video Functions
 One Composite Signal Input
 Video Amplifier for Composite Signal Output
Gain: (AK4958EG) +6 / +12 / +16.5dB, (AK4958ECB) +12 / +16.5dB
 Low Pass Filter
10. Ta = 30  85C
11. Power Supply:
(AK4958EG)
 Analog Power Supply (AVDD): 2.8 ~ 3.6V
 Digital Power Supply (DVDD): 1.6 ~ 2.0V
 Digital I/O Power Supply (TVDD): 1.6 or DVDD – 0.2 ~ 3.6V
(AK4958ECB)
 Analog Power Supply (AVDD): 2.8 ~ 3.6V
 Digital & Digital I/O Power Supply (DTVDD): 1.6 ~ 2.0V
12. Package:
(AK4958EG)
 32pin BGA (3.5 x 3.5 mm, 0.5mm pitch)
(AK4958ECB)
 25pin CSP (2.2 x 2.2 mm, 0.4mm pitch)
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[AK4958]
■ Block Diagram
▪ AK4958EG
AVDD
VSS1
VCOM
REGFIL
DVDD
TVDD VSS2
PMMP
MPWR
MIC Power
Supply
LDO: 2.3V
PDN
Analog Block
PMMICL
Internal
MIC
MIC Power, SPK-Amp,
LINE/Video-out-Amp
LIN1/DMDAT
RIN1/DMCLK
PMADL or PMADR
MIC-Amp
ADC
HPF
PMPFIL
PMMICR
External
MIC
MIC Sensitivity Correction
LIN2
Auto Wind Noise
Reduction Filter
RIN2
HPF2
PMLO
BICK
LOUT
LPF
LRCK
Line Out
Audio
I/F
Stereo Emphasis
ROUT
SDTO
EQ0
SDTI
4-band EQ
PMBP
BEEP
VSS3
ALC
HPF3
1-band EQ
Moving Average
Circuit
PMDAC
PMSPK
Mono/
Stereo
SPP
Speaker
SPN
DVOL
SPK-amp
MCKO
PMPLL
DAC SMUTE
3-band
DRC
Bass
Boost
PLL
MCKI
VSS4
PMV
Composite
Video Out
VOUT
+6/+12/16.5dB
CSN/SDA
Control
Register
LPF
CLAMP
CCLK/SCL
CDTIO/CAD0
I2C
VIN
Figure 1. Block Diagram (AK4958EG)
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[AK4958]
▪ AK4958ECB
AVDD
VSS1
VCOM
REGFIL
DTVDD
VSS2
PMMP
MPWR
MIC Power
Supply
LDO: 2.3V
PDN
Analog Block
PMMICL
MIC Power, SPK-Amp,
LINE/Video-out-Amp
Internal
MIC
LIN1/DMDAT
PMADL or PMADR
MIC-Amp
ADC
HPF
RIN1/DMCLK
PMPFIL
PMMICR
MIC Sensitivity Correction
Auto Wind Noise
Reduction Filter
HPF2
PMLO
BICK
LOUT
LPF
Line Out
LRCK
Audio
I/F
Stereo Emphasis
ROUT
SDTO
EQ0
SDTI
4-band EQ
PMBP
BEEP
ALC
HPF3
1-band EQ
Moving Average
Circuit
PMDAC
PMSPK
Mono/
Stereo
SPP
Speaker
SPN
DVOL
SPK-amp
MCKO
PMPLL
DAC SMUTE
3-band
DRC
Bass
Boost
PLL
PMV
Composite
Video Out
VOUT
+12/16.5dB
MCKI
SDA
Control
Register
LPF
SCL
CLAMP
VIN
Figure 2. Block Diagram (AK4958ECB)
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[AK4958]
■ Ordering Guide
AK4958EG
AK4958ECB
AKD4958EG
AKD4958ECB
30  +85C
32-pin BGA (0.5mm pitch)
30  +85C
25-pin CSP (0.4mm pitch)
Evaluation board for AK4958EG
Evaluation board for AK4958ECB
■ Pin Layout
▪ AK4958EG
6
5
4
Top View
3
2
1
A
B
C
D
E
F
6
MPWR
ROUT
REGFIL
VCOM
VSS1
VIN
5
RIN2
BEEP
LOUT
AVDD
VOUT
VSS4
LIN2
SPP
SPN
I2C
VSS2
VSS3
4
3
2
1
RIN1
/DMCLK
LIN1
/DMDAT
CDTIO
/CAD0
CCLK
/SCL
A
CSN
/SDA
SDTI
MCKO
MCKI
DVDD
LRCK
BICK
SDTO
TVDD
PDN
B
C
D
E
F
Top View
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[AK4958]
▪ AK4958ECB
5
4
Top View
3
2
1
A
B
C
D
E
5
PDN
VSS2
SPP
SPN
VIN
4
MCKO
MCKI
DTVDD
VOUT
VSS1
3
SDTI
SDTO
BEEP
AVDD
VCOM
2
LRCK
BICK
LOUT
REGFIL
1
SCL
SDA
MPWR
ROUT
A
B
D
E
RIN1
/DMCLK
LIN1
/DMDAT
C
Top View
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■ Comparison Table of the AK4958EG and AK4958ECB
Function
Digital I/O Voltage
AK4958EG
TVDD = 1.6 or DVDD-0.2  3.6V
Number of VSS Pin
ADC Input Channel
Control I/F mode
Four pins
2 Stereo (LIN1/RIN1, LIN2/RIN2)
3-wire / I2C
Package
32BGA (3.5 x 3.5mm, 0.5mm pitch)
MS1558-E-02-PB
AK4958ECB
DTVDD = 1.6V  2.0V
*Digital Power and Digital Interface
Supply share a pin.
Two pins
1 Stereo (LIN1/RIN1)
I2C
*Slave address “0010011”
25CSP (2.2 x 2.2mm, 0.4mm pitch)
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[AK4958]
PIN/FUNCTION (AK4958EG)
No Pin Name
Power Supply
I/O
D5
AVDD
-
D6
VCOM
O
E6
VSS1
-
F2
DVDD
-
E1
TVDD
-
C6
REGFIL
O
Function
Analog Power Supply, 2.8 ~ 3.6V
This pin must be connected to VSS1 through a 0.1μF ceramic capacitor.
Common Voltage Output
Bias voltage of ADC inputs and DAC outputs.
This pin must be connected to VSS1 through a 2.2μF ±50% capacitor.
Ground 1
Digital Power Supply, 1.6 ~ 2.0V
This pin must be connected to VSS2 through a 0.1μF ceramic capacitor.
Digital Interface Supply, 1.6 or DVDD-0.2V ~ 3.6V
LDO Voltage Output pin for Analog Logic (typ 2.3V)
This pin must be connected to VSS1 through a 2.2μF ±50% capacitor.
Ground 2
Ground 3
Ground 4
E3
VSS2
F3
VSS3
F5
VSS4
Audio Interface
MCKI
I
Master Clock Input (Note 1)
E2
O
Master Clock Output
D2 MCKO
I/O
Channel Clock Pin (Note 1)
B1 LRCK
I/O
Audio Serial Data Clock Pin (Note 1)
C1 BICK
I
Audio Serial Data Input (Note 1)
C2 SDTI
O
Audio Serial Data Output
D1 SDTO
Control Register Interface
CSN
I
Chip Select Pin
(I2C pin = “L”) (Note 1)
B2
SDA
I/O
Control Data Input/Output
(I2C pin = “H”) (Note 1)
CCLK
I
Control Data Clock Pin
(I2C pin = “L”) (Note 1)
A1
SCL
I
Control Data Clock Pin
(I2C pin = “H”) (Note 1)
CDTIO
I/O
Control Data Input/Output
(I2C pin = “L”) (Note 1)
A2
CAD0
I
Chip Address Select Pin
(I2C pin = “H”) (Note 1)
I
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire Serial (Note 1)
B3 I2C
Note 1. All input pins except analog input pins (BEEP, LIN1, RIN1, LIN2, RIN2, VIN) must not be allowed to float.
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[AK4958]
No Pin Name
Microphone Block
LIN1
3
DMDAT
RIN1
4
DMCLK
5 LIN2
6 RIN2
2 MPWR
MIN Block
1 BEEP
Lineout Block
31 LOUT
32 ROUT
Speaker Block
21 SPP
22 SPN
I/O
Function
I
I
I
O
I
I
O
Lch Analog Input 1
Digital Microphone Data Input
Rch Analog Input 1
Digital Microphone Clock
Lch Analog Input 2
Rch Analog Input 2
Microphone Power Supply
I
BEEP Signal Input
O
O
Lch Analog Output
Rch Analog Output
O
O
Speaker Amp Positive Output
Speaker Amp Negative Output
I
O
Composite Video Input
Composite Video Output
(DMIC bit = “0”)
(DMIC bit = “1”) (Note 1)
(DMIC bit = “0”)
(DMIC bit = “1”)
Video Block
25 VIN
24 VOUT
Other Functions
Reset & Power-down Pin (Note 1)
“L”: Reset & Power-down, “H”: Normal Operation
Note 1. All input pins except analog input pins (BEEP, LIN1, RIN1, LIN2, RIN2, VIN) must not be allowed to float.
18
PDN
I
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PIN/FUNCTION (AK4958ECB)
No Pin Name
Power Supply
I/O
D3
AVDD
-
E3
VCOM
O
E4
VSS1
-
C4
DTVDD
-
E2
REGFIL
O
B5 VSS2
Audio Interface
I
B4 MCKI
O
A4 MCKO
I/O
A2 LRCK
I/O
B2 BICK
I
A3 SDTI
O
B3 SDTO
Control Register Interface
B1 SDA
A1 SCL
Microphone Block
LIN1
C1
DMDAT
RIN1
C2
DMCLK
D1 MPWR
BEEP Block
C3 BEEP
Lineout Block
D2
LOUT
E1 ROUT
Speaker Block
C5 SPP
D5 SPN
I/O
I
Function
Analog Power Supply, 2.8 ~ 3.6V
This pin must be connected to VSS1 through a 0.1μF ceramic capacitor.
Common Voltage Output
Bias voltage of ADC inputs and DAC outputs.
This pin must be connected to VSS1 through a 2.2μF ±50% capacitor.
Ground 1
Digital Power & Digital Interface Supply, 1.6 ~ 2.0V
This pin must be connected to VSS2 through a 0.1μF ceramic capacitor.
LDO Voltage Output pin for Analog Logic (typ 2.3V)
This pin must be connected to VSS1 through a 2.2μF ±50% capacitor.
Ground 2
Master Clock Input (Note 2)
Master Clock Output
Channel Clock (Note 2)
Audio Serial Data Clock (Note 2)
Audio Serial Data Input (Note 2)
Audio Serial Data Output
Control Data Input/Output (Note 2)
Control Data Clock Pin (Note 2)
I
I
I
O
O
Lch Analog Input 1
Digital Microphone Data Input
Rch Analog Input 1
Digital Microphone Clock Pin
Microphone Power Supply
I
BEEP Signal Input
O
Lch Analog Output
O
Rch Analog Output
O
O
Speaker Amp Positive Output
Speaker Amp Negative Output
I
O
Composite Video Input
Composite Video Output
(DMIC bit = “0”)
(DMIC bit = “1”) (Note 2)
(DMIC bit = “0”)
(DMIC bit = “1”)
Video Block
E5 VIN
D4 VOUT
Other Functions
Reset & Power-down Pin
“L”: Reset & Power-down, “H”: Normal Operation
Note 2. All input pins except analog input pins (BEEP, LIN1, RIN1, VIN) must not be allowed to float.
A5
PDN
I
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[AK4958]
■ Handling of Unused Pin
Unused I/O pins must be processed appropriately as below.
Classification
Pin Name
MPWR, SPN, SPP, LOUT, ROUT, BEEP, RIN2,
LIN2, VIN, VOUT
Analog
LIN1, RIN1
Digital
MCKO, SDTO
MCKI, SDTI
LRCK, BICK
MS1558-E-02-PB
Setting
These pins must be open.
DMIC bit = “0”, and
these pins must be open.
These pins must be open.
These pins must be connected to VSS2.
M/S bit = “0”, and
these pins must be connected to VSS2.
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[AK4958]
ABSOLUTE MAXIMUM RATINGS
(AK4958EG: VSS1=VSS2=VSS3=VSS4=0V, AK4958ECB: VSS1=VSS2=0V; Note 3)
Parameter
Symbol
min
Power Supplies Analog
0.3
AVDD
(AK4958EG)
Digital
DVDD
0.3
Digital I/O
TVDD
0.3
Power Supplies Analog
AVDD
0.3
(AK4958ECB)
Digital, Digital I/O
DTVDD
0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 4)
VINA
0.3
max
6.0
2.5
6.0
6.0
2.5
10
AVDD+0.3
Unit
V
V
V
mA
V
(AK4958EG, Note 5)
VIND
TVDD+0.3
V
0.3
(AK4958ECB,
Note
6)
VIND
DTVDD+0.3
V
0.3
Digital Input Voltage
(Note 8)
VIND
6.0
V
0.3
Ambient Temperature (powered applied)
Ta
85
30
C
Storage Temperature
Tstg
150
65
C
AK4958EG
Pd1
460
mW
Maximum Power Dissipation (Note 8)
AK4958ECB
Pd1
460
mW
Note 3. All voltages are with respect to ground. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog
ground plane.
Note 4. BEEP, LIN1, RIN1, LIN2, RIN2, VIN, I2C pins
Note 5. PDN, CDTIO, SDTI, LRCK, BICK and MCKI pins
Note 6. PDN, SDTI, LRCK, BICK, MCKI pins
Note 7. CSN/SDA and CCLK/SCL pins
Note 8. This power is the AK4958 internal dissipation that does not include power dissipation of externally connected
speakers. The maximum junction temperature is 125C and θja (Junction to Ambient) is 80C/W at JESD51-9
(2p2s) for the AK4958EG and 56C/W for the AK4958ECB. When Pd =460mW and the θja is 80C/W for the
AK4958EG, and 56C/W for the AK4958ECB, the junction temperature does not exceed 125C. In this case, the
AK4958 will not be damaged by its internal power dissipation. Therefore, the AK4958EG should be used in the
condition of θja ≤ 80C/W, and the AK4958ECB should be used in the condition of θja ≤ 56C/W.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
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[AK4958]
RECOMMENDED OPERATING CONDITIONS (AK4958EG)
(VSS1=VSS2=VSS3=VSS4=0V; Note 3)
Parameter
Symbol
min
typ
max
Unit
Power Supplies
Analog
AVDD
2.8
3.3
3.6
V
(Note 9)
Digital
DVDD
1.6
1.8
2.0
V
Digital I/O (Note 10)
TVDD
1.6 or DVDD-0.2
1.8
3.6
V
Note 3. All voltages are with respect to ground.
Note 9. The power-up sequence between AVDD, DVDD and TVDD is not critical. The PDN pin must be “L” upon power
up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error.
Note 10. The minimum value is higher voltage between DVDD-0.2V and 1.6V.
* When TVDD is powered ON and the PDN pin is “L”, AVDD and DVDD can be powered ON/OFF.
When the AK4958EG is powered ON from power-down state, the PDN pin must be “H” after all
power supplies (AVDD, DVDD and TVDD) are ON.
RECOMMENDED OPERATING CONDITIONS (AK4958ECB)
(VSS1=VSS2 =0V; Note 3)
Parameter
Symbol
min
typ
max
Unit
Power Supplies
Analog
AVDD
2.8
3.3
3.6
V
(Note 9)
Digital, Digital I/O
DTVDD
1.6
1.8
2.0
V
Note 3. All voltages are with respect to ground.
Note 11. The power-up sequence between AVDD and DTVDD is not critical. The PDN pin must be “L” upon power up,
and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error.
* When DTVDD is powered ON and the PDN pin is “L”, AVDD can be powered ON/OFF. When the
AK4958ECB is powered ON from power-down state, the PDN pin must be “H” after all power
supplies (AVDD and DTVDD) are ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK4958]
ANALOG CHARACTERISTICS
(Ta=25C; fs=48kHz, BICK=64fs;Signal Frequency=1kHz; 24bit Data; Measurement Bandwidth =20Hz  20kHz; unless
otherwise specified; AK4958EG: AVDD = 3.3V, DVDD = TVDD= 1.8V;VSS1=VSS2=VSS3=VSS4=0V, AK4958ECB:
AVDD = 3.3V, DTVDD = 1.8V; VSS1=VSS2=0V)
Parameter
min
typ
max
Unit
Microphone Amplifier: LIN1, RIN1, LIN2, RIN2 pins
Input Resistance
20
30
42
k
MGAIN2-0 bits = “000”
-1
0
+1
dB
Gain
+5
MGAIN2-0 bits = “001”
+6
+7
dB
MGAIN2-0 bits = “010”
+11
+12
+13
dB
MGAIN2-0 bits = “011”
+14
+15
+16
dB
MGAIN2-0 bits = “100”
+17
+18
+19
dB
MGAIN2-0 bits = “101”
+20
+21
+22
dB
MGAIN2-0 bits = “110”
+24
+25
+26
dB
MGAIN2-0 bits = “111”
+29
+30
+31
dB
Microphone Power Supply: MPWR pin
MICL bit = “0”
2.2
2.4
2.6
V
Output Voltage
MICL bit = “1”
1.8
2.0
2.2
V
Output Noise Level (A-weighted)
dBV
108
Load Resistance
0.5
k
Load Capacitance
30
pF
PSRR (Sine Wave = 500mVpp, fin = 1kHz)
100
dB
ADC Analog Input Characteristics
AK4958EG: LIN1/RIN1/LIN2/RIN2 pins  ADC (Programmable Filter = OFF)
AK4958ECB: LIN1/RIN1 pins  ADC (Programmable Filter = OFF)
Resolution
24
Bits
(Note 13)
0.261
Vpp
Input Voltage (Note 12)
(Note 14)
1.86
2.07
2.28
Vpp
(Note 13)
73
83
dBFS
S/(N+D) (1dBFS)
(Note 14)
85
dBFS
(Note 13)
78
88
dB
D-Range (60dBFS, A-weighted)
(Note 14)
96
dB
(Note 13)
78
88
dB
S/N
(A-weighted)
(Note 14)
96
dB
(Note 13)
75
90
dB
Interchannel Isolation
(Note 14)
100
dB
(Note 13)
0
0.5
dB
Interchannel Gain Mismatch
(Note 14)
0
0.5
dB
PSRR (Sine Wave = 500mVpp, fin = 1kHz)
80
dB
Note 12. Vin = 0.9 x 2.3Vpp (typ) @MGAIN2-0 bits = “000” (0dB)
Note 13. MGAIN2-0 bits = “110” (+18dB)
Note 14. MGAIN2-0 bits = “000” (0dB)
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[AK4958]
Parameter
min
typ
max
DAC Characteristics:
Resolution
24
Stereo Line Output Characteristics: DAC  LOUT, ROUT pins, ALC=OFF, DVOL=OVOL =0dB,
RL=10k , PMBP bit = “0”, LVCM1-0 bits = “01”
LVCM0 bit = “0”
2.26
Output Voltage
(0dBFS)
(Note 15)
LVCM0 bit = “1”
1.00
LVCM0 bit = “0”
1.44
1.60
1.76
Output Voltage
(3dBFS)
(Note 15)
LVCM0 bit = “1”
1.82
2.00
2.22
75
85
S/(N+D) (3dBFS)
S/N
(A-weighted)
82
92
Interchannel Isolation
85
100
Interchannel Gain Mismatch
0
0.8
Load Resistance
10
Load Capacitance
30
80
PSRR (Sine Wave = 500mVpp, fin = 1kHz)
Speaker-Amp Characteristics: DAC  SPP/SPN pins, ALC=OFF, DVOL=OVOL =0dB, RL=8, BTL
Output Voltage (AK4958EG)
3.18
SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW)
3.20
4.00
4.80
SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW)
1.79
SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW)
S/(N+D) (AK4958EG)
65
SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW)
20
60
SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW)
20
SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW)
S/N (AK4958EG)
80
90
SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW)
(A-weighted)
Output Voltage (AK4958ECB)
3.18
SPKG1-0 bits = “00”, 0.7dBFS (Po=150mW)
3.20
4.00
4.80
SPKG1-0 bits = “01”, 0.7dBFS (Po=250mW)
1.79
SPKG1-0 bits = “10”, 0.85dBFS (Po=400mW)
S/(N+D) (AK4958ECB)
65
SPKG1-0 bits = “00”, 0.7dBFS (Po=150mW)
20
60
SPKG1-0 bits = “01”, 0.7dBFS (Po=250mW)
20
SPKG1-0 bits = “10”, 0.85dBFS (Po=400mW)
S/N (AK4958ECB)
80
90
SPKG1-0 bits = “01”, 0.7dBFS (Po=250mW)
(A-weighted)
Load Resistance
6.8
Load Capacitance
100
PSRR (Sine Wave = 500mVpp, fin = 1kHz)
60
Note 15. The output voltage does not track the AVDD.
MS1558-E-02-PB
Unit
Bits
Vpp
Vrms
Vpp
Vpp
dBFS
dB
dB
dB
k
pF
dB
Vpp
Vpp
Vrms
dB
dB
dB
dB
Vpp
Vpp
Vrms
dB
dB
dB
dB

pF
dB
2014/08
- 15 -
[AK4958]
Parameter
min
typ
max
Unit
BEEP Input: BEEP pin, Internal Resistance Mode
(PMBP bit =“1”, BPM bit = “0”, BPVCM bit = “0”, BPLVL3-0 bits = “0000”)
Input Resistance
46
66
86
k
Maximum Input Voltage (Note 16)
1.54
Vpp
Gain
LVCM1-0 bits = “00”
0
+1
dB
1
MIN  LOUT
LVCM1-0 bits = “01”
+2.0
dB
LVCM1-0 bits = “10”
+2.0
dB
LVCM1-0 bits = “11”
+4.0
dB
MIN  SPP/SPN (Note 17)
ALC2 bit = “0”, SPKG1-0 bits = “00”
+4.4
+6.4
+8.4
dB
ALC2 bit = “0”, SPKG1-0 bits = “01”
+8.4
dB
ALC2 bit = “0”, SPKG1-0 bits = “10”
+11.1
dB
ALC2 bit = “0”, SPKG1-0 bits = “11”
+13.1
dB
ALC2 bit = “1”, SPKG1-0 bits = “00”
+8.4
dB
ALC2 bit = “1”, SPKG1-0 bits = “01”
+10.1
dB
ALC2 bit = “1”, SPKG1-0 bits = “10”
+13.1
dB
ALC2 bit = “1”, SPKG1-0 bits = “11”
+15.1
dB
BEEP Input: BEEP pin, External Resistance mode
(PMBP bit =“1”, BPM bit = “1”, BPVCM bit = “0”, BPLVL3-0 bits = “0000”), External Input Resistance= 66k
Maximum Input Voltage
1.54
Vpp
Gain (Note 18)
BEEP  LOUT
LVCM1-0 bits = “00”
0
+4.5
dB
4.5
LVCM1-0 bits = “01”
+2.0
dB
LVCM1-0 bits = “10”
+2.0
dB
LVCM1-0 bits = “11”
+4.0
dB
BEEP  SPP/SPN
ALC2 bit = “0”, SPKG1-0 bits = “00”
+1.9
+6.4
+10.9
dB
ALC2 bit = “0”, SPKG1-0 bits = “01”
+8.4
dB
ALC2 bit = “0”, SPKG1-0 bits = “10”
+11.1
dB
ALC2 bit = “0”, SPKG1-0 bits = “11”
+13.1
dB
ALC2 bit = “1”, SPKG1-0 bits = “00”
+8.4
dB
ALC2 bit = “1”, SPKG1-0 bits = “01”
+10.4
dB
ALC2 bit = “1”, SPKG1-0 bits = “10”
+13.1
dB
ALC2 bit = “1”, SPKG1-0 bits = “11”
+15.1
dB
Note 16. The maximum value is AVDD Vpp when BPVCM bit = “1”. However, a click noise may occur when the
amplitude after BEEP-Amp is 0.5Vpp or more. (set by BPLVL3-0 bits)
Note 17. These are the ideal values with no load resistance. When an 8Ω is connected the value degrades about 0.4dB for
the AK4958EG and about 0.2dB for the AK4958ECB.
Note 18. The gain is in inverse proportion to external input resistance.
MS1558-E-02-PB
2014/08
- 16 -
[AK4958]
Parameter
Video Signal Input
External Resistor (Note 20) R1 (Figure 3)
External Capacitor
C1 (Figure 3)
Maximum Input Voltage: VG1-0 bits = “10” (+12dB)
Pull Down Current
Video Analog Output (Figure 4)
Output Gain
fin =100kHz
Sine wave Input (Note 19)
VG1-0 bits = “00”, 0.5Vpp Input
(AK4958EG)
VG1-0 bits = “10”, 0.5Vpp Input
VG1-0 bits = “11”, 0.3Vpp Input
Clamp Level (Note 19)
S/N (Note 21)
VG1-0 bits = “10”(+12dB)
Maximum Output Voltage
(Note 19)
Secondary Harmonic Distortion
VG1-0 bits = “10”(+12dB)
fin = 3.58MHz
Load Resistance
Load Capacitance
BW = 100kH  6MHz,
S = 0.35Vpp Input
fin =100kHz (Sine wave)
430mVpp: 20 ~ 100IRE,
Sine Wave Input
(Flat Field = 100 IRE
Burst = 20IRE)
C2 (Figure 4)
C3 (Figure 4)
fin = 10kHz
fin = 100kHz
min
typ
max
Unit
0.075
0.02
-
0.047
0.6
0.125
1.6
0.2
-
k
F
Vpp
A
5.5
6.0
6.5
11.5
16.0
-
12.0
16.5
50
12.5
17.0
100
mV
60
67
-
dB
2.54
-
-
Vpp
-
45
35
dB
140
-
150
45
30
15
400
-

pF
pF
dB
dB
dB
PSRR (Note 22)
VG1-0 bits = “10”(+12dB)
LPF for VIN signal : (Note 19)
Frequency Response (fin = 100kHz, 0.5Vpp, Sine wave Input), C2=15pF, C3=400pF
+2.0
Response at 6.75MHz
3.0
0.5
dB
Response at 27MHz
47
20
Group Delay
15
100
ns
|GD3MHzGD6MHz|
Note 19. This is a value at measurement point in Figure 4. 0.5Vpp input is the value when VG1-0 bit =“10”(+12dB). Input
amplitude is in inverse proportion to the gain. S/N and Secondary Harmonic Distortion values are measured at
measuring point 2.
Note 20. PMV bit must be set to “0” if the resistor value exceeds the range from 0.075 to 1.6kΩ in case of the input signal
is stopped or the input circuit of the VIN pin is powered down.
Note 21. S/N = 20xlog (Output Voltage[Vpp]/Noise Level[Vrms]). Output Voltage = 0.7 [Vpp].
Note 22. PSRR is applied to AVDD with 500mVpp sine wave when DC level of -20IRE, 0IRE and 100IRE are input to the
VIN pin.
VIN pin
From Video DAC
AK4958
R1
C1
Figure 3. External Resistor of Video Signal Input pin
Measurement point1
Measurement point 2
75 Ω
Video Signal Output
R3
75 Ω
R2
C2
C3
Figure 4. Load Capacitance C2 and C3
MS1558-E-02-PB
2014/08
- 17 -
[AK4958]
Parameter
min
typ
max
Unit
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up (Note 23)
AVDD
10.5
15
mA
DVDD +TVDD
2.8
4.2
mA
MIC + ADC (Note 24)
AVDD
2.5
mA
DVDD +TVDD
0.9
mA
DAC + Lineout (Note 25)
AVDD
2.2
mA
DVDD +TVDD
0.7
mA
DAC + SPK-Amp (Note 26)
AVDD
3.3
mA
DVDD +TVDD
0.7
mA
Video Block (Note 27)
AVDD
5.3
mA
Power Down (PDN pin = “L”) (Note 28)
AVDD+DVDD+TVDD
1
5
A
Note 23. When PMADL=PMADR=PMDAC=PMPFIL=PMLO=PMSPK=PMPLL=MCKO=PMBP=PMMP =PMMICR
=PMMICL =M/S =PMV bits = “1”, SPK-amp No load, no signals are input to LIN/RIN and BEEP pins, black
signal is input to the VIN pin, no output from the LOUT/ROUT pin and “0” data input to the SDTI pin in PLL
Master Mode (MCKI=13.5MHz, FS3-0 bits = “1011”). In this case, the output current of the MPWR pin is 0mA.
The path settings are, BRDAC= ADCPF = PFSDO bits = “1”, PFDAC bit= “0”, DACS = DACL bits = “1”, and
BEEPS = BEEPL bits = “0”. MG2-0 bits = “000”, HPF = LPF = FIL3 = EQ0 = EQ1~5 = ALC1~2 bits = “0”,
MONO1-0 bits = “00”, DVOL7-0 bits = “C0H”, and SMUTE bit = “0”.
Note 24. When PMADL = PMADR = PMMICL = PMMICLR bits = “1” and no signals are input to the LIN/RIN pin in
EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”). The path setting is ADCPF=PFSDO bits = “0”.
Note 25. When PMDAC = PMLO = “1”, “0” data input to the SDTI pin, and no output from the LOUT/ROUT pin in EXT
Slave Mode (PMPLL=M/S=MCKO bits =“0”). The path settings are BRDAC= PFDAC bit = “0”, DACL bit =
“1”, and DACS =BEEPS =BEEPL bits = “0”. MONO1-0 bits = “00”, DVOL7-0 bits = “0CH”, and SMUTE bit
= “0”.
Note 26. When PMDAC = PMSPK =SPPSN bits = “1”, “0” data input to the SDTI pin, and No load at SPK-amp in EXT
Slave Mode (PMPLL=M/S=MCKO bits =“0”). The path settings are MONO1-0 bits= “00”, DVOL7-0 bits
“C0H”, and SMUTE bit = “0”.
Note 27. When PMV bit = “1”, No-load, and the black signal is input to the VIN pin.
Note 28. Digital input pins (MCKI, LRCK, BICK, SDTI, CSN/SDA, CCLK/SCL, CDTIO/CAD0, I2C pins) are fixed to
TVDD (AK4958EG), DTVDD(AK4958ECB) or VSS2, and the I2C pin is fixed to AVDD or VSS.
MS1558-E-02-PB
2014/08
- 18 -
[AK4958]
FILTER CHARACTERISTICS
(Ta =25C; fs=48kHz; AK4958EG: AVDD=2.8  3.6V, DVDD = 1.6 ~ 2.0V, TVDD = 1.6 or (DVDD-0.2) 3.6V,
AK4958ECB: AVDD=2.8  3.6V, DTVDD = 1.6 ~ 2.0V)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 29)
PB
0
18.8
kHz
0.16dB
21.1
kHz
0.66dB
21.7
kHz
1.1dB
24.1
kHz
6.9dB
Stopband (Note 29)
SB
28.4
kHz
Passband Ripple
PR
dB
0.16
Stopband Attenuation
SA
73
dB
Group Delay (Note 30)
GD
17
1/fs
Group Delay Distortion
0
GD
s
ADC Digital Filter (HPF): HPFC1-0 bits = “00”
Frequency Response (Note 29) 3.0dB
FR
3.7
Hz
10.9
Hz
0.5dB
23.9
Hz
0.1dB
DAC Digital Filter (LPF):
Passband (Note 29)
PB
0
21.8
kHz
0.05dB
24
kHz
6.0dB
Stopband (Note 29)
SB
26.2
kHz
Passband Ripple
PR
dB
0.05
Stopband Attenuation
SA
54
dB
Group Delay (Note 30)
GD
22
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0  20.0kHz
1.0
Note 29. The passband and stopband frequencies scale with fs (sampling frequency). Each response refers to that of 1kHz.
For example, it is 0.454 x fs (ADC) when PB=21.7kHz (@1.1dB).
Note 30. A calculating delay time which is induced by digital filtering. This time is from the input of an analog signal to the
setting of 24-bit data of both channels to the ADC output register. For the DAC, this time is from setting the 24-bit
data of a channel from the input register to the output of analog signal. For the signal through the programmable
filters (1st order HPF + 1st order LPF + 4-band Equalizer + ALC + 1-band Equalizer), the group delay is
increased by 4/fs from the value above in both recording and playback modes if there is no phase change by the
IIR filter.
MS1558-E-02-PB
2014/08
- 19 -
[AK4958]
DC CHARACTERISTICS
(Ta =25C; fs=48kHz, AK4958EG: AVDD=2.8 ~ 3.6V, DVDD = 1.6 ~ 2.0V, TVDD = 1.6 or (DVDD-0.2) 3.6V;
AK4958ECB: AVDD=2.8~3.6V, DTVDD= 1.6~2.0V)
Parameter
Symbol
min
typ
max
Unit
Audio Interface & Serial µP Interface
(CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins )
High-Level Input Voltage
(Except I2C pin, TVDD ≥ 2.2V)
VIH
70%TVDD
V
(Except I2C pin, TVDD < 2.2V)
VIH
80%TVDD
V
(I2C pin)
VIH1
70%AVDD
V
Low-Level Input Voltage
(Except I2C pin, TVDD ≥ 2.2V)
VIL
30%TVDD
V
(Except I2C pin, TVDD < 2.2V)
VIL
20%TVDD
V
(I2C pin)
VIL1
30%AVDD
V
Input Leakage Current
Iin1
10
A
Audio Interface & Serial µP Interface (CDTIO, SDA MCKO, BICK, LRCK, SDTO pins Output)
High-Level Output Voltage
(Iout = 80A)
VOH
TVDD0.2
V
Low-Level Output Voltage
(Except SDA pin : Iout = 80A) VOL1
0.2
V
(SDA pin, 2.0V  TVDD  3.6V: Iout = 3mA) VOL2
0.4
V
(SDA pin, 1.6V  TVDD < 2.0V: Iout = 3mA) VOL2
20%TVDD
V
Digital Microphone Interface (DMDAT pin Input ; DMIC bit = “1”)
High-Level Input Voltage
Low-Level Input Voltage
VIH2
VIL2
65%AVDD
-
-
35%AVDD
V
V
Input Leakage Current
Iin2
10
A
Digital Microphone Interface (DMCLK pin Output ; DMIC bit = “1”)
High-Level Output Voltage
(Iout=80A)
VOH3
AVDD-0.4
V
Low-Level Output Voltage
(Iout= 80A)
VOL3
0.4
V
Note 31. TVDD means DTVDD for the AK4958ECB.
Note 32. The external pull-up resistors at the SDA and SCL pins should be connected to the voltage that is TVDD
(DTVDD) or more and 6V or less.
MS1558-E-02-PB
2014/08
- 20 -
[AK4958]
SWITCHING CHARACTERISTICS
(Ta =25C; fs=48kHz; CL=20pF; AK4958ECB: AVDD=2.8  3.6V, DVDD = 1.6 ~ 2.0V, TVDD = 1.6 or (DVDD-0.2)
3.6V, AK4958ECB: AVDD=2.8  3.6V, DTVDD = 1.6 ~ 2.0V)
Parameter
Symbol
min
typ
max
Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
PLL3-0 bits = “0100”
fCLK
11.2896
27
MHz
PLL3-0 bits = “0110”
fCLK
12
MHz
PLL3-0 bits = “0111”
fCLK
24
MHz
PLL3-0 bits = “1100”
fCLK
13.5
MHz
PLL3-0 bits = “1101”
fCLK
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
s
Pulse Width High
tCLKH
0.4/fCLK
s
MCKO Output Timing
Frequency
PS1-0 bits = “00”
fMCK
256fs
Hz
PS1-0 bits = “01”
fMCK
128fs
Hz
PS1-0 bits = “10”
fMCK
64fs
Hz
PS1-0 bits = “11” (Note 33)
fMCK
512fs
Hz
Duty Cycle
dMCK
40
50
60
%
LRCK Output Timing
エラー! 参
照元が見つ
Frequency
fs
Hz
かりませ
ん。
Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
32fs
Hz
BCKO bit = “1”
tBCK
64fs
Hz
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
s
Pulse Width High
tCLKH
0.4/fCLK
s
MCKO Output Timing
Frequency
PS1-0 bits = “00”
fMCK
256fs
Hz
PS1-0 bits = “01”
fMCK
128fs
Hz
PS1-0 bits = “10”
fMCK
64fs
Hz
PS1-0 bits = “11” (Note 33)
fMCK
512fs
Hz
Duty Cycle
dMCK
40
50
60
%
LRCK Input Timing
エラー! 参
照元が見つ
Frequency
fs
Hz
かりませ
ん。
Duty Cycle
Duty
45
55
%
BICK Input Timing
Frequency
tBCK
32fs
64fs
Hz
Pulse Width Low
tBCKL
0.4 x tBCK
s
Pulse Width High
tBCKH
0.4 x tBCK
s
Note 33. When MCKO=512fs, fs=8, 11.025, 12, 16, 32kHz are not available.
MS1558-E-02-PB
2014/08
- 21 -
[AK4958]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
PLL3-0 bits = “0010”
fs
PLL3-0 bits = “0011”
fs
Duty
Duty
BICK Input Timing
Frequency
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
FS1-0 bits = “00”
fCLK
FS1-0 bits = “01”
fCLK
FS1-0 bits = “10” or “11”
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
FS1-0 bits = “00”
fs
FS1-0 bits = “01”
fs
FS1-0 bits = “10”
fs
FS1-0 bits = “00”
fs
Duty
Duty
BICK Input Timing
Frequency
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs (FS1-0 bits = “00”)
fCLK
512fs (FS1-0 bits = “10”)
fCLK
512fs (FS1-0 bits = “11”)
fCLK
1024fs (FS1-0 bits = “01”)
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
FS1-0 bits = “00”
fs
FS1-0 bits = “01”
fs
FS1-0 bits = “10” or “11”
fs
Duty Cycle
Duty
BICK Output Timing
Frequency
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS1558-E-02-PB
min
typ
max
Unit
45
fBCK/32
fBCK/64
-
55
Hz
Hz
%
0.2352
0.4704
0.4/tBCK
0.4/tBCK
-
1.536
3.072
-
MHz
MHz
s
s
0.4/fCLK
0.4/fCLK
256fs
1024fs
512fs
-
-
Hz
Hz
Hz
s
s
7.35
7.35
7.35
7.35
45
-
48
13
24
48
55
kHz
kHz
kHz
kHz
%
32fs
130
130
-
64fs
-
Hz
ns
ns
1.8816
3.7632
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
24.576
13.312
-
MHz
MHz
MHz
MHz
s
s
-
fCLK/256
fCLK/1024
fCLK/512
50
-
kHz
kHz
kHz
%
-
32fs
64fs
50
-
Hz
Hz
%
2014/08
- 22 -
[AK4958]
Parameter
Symbol
min
typ
Audio Interface Timing
Master Mode
tMBLR
BICK “” to LRCK Edge (Note 34)
40
LRCK Edge to SDTO (MSB)
tLRD
70
(Except I2S mode)
tBSD
BICK “” to SDTO
70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Slave Mode
tLRB
50
LRCK Edge to BICK “” (Note 34)
tBLR
50
BICK “” to LRCK Edge (Note 34)
LRCK Edge to SDTO (MSB)
tLRD
(Except I2S mode)
tBSD
BICK “” to SDTO
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing (3-wire Mode) (Note 35)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTIO Setup Time
tCDS
40
CDTIO Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN Edge to CCLK “” (Note 36)
tCSH
50
CCLK “” to CSN Edge (Note 36)
tDCD
CCLK “” to CDTIO (at Read Command)
tCCZ
CSN “” to CDTIO (Hi-Z) (at Read Command)(Note 38)
Control Interface Timing (I2C Bus Mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 39)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Note 34. BICK rising edge must not occur at the same time as LRCK edge.
Note 35. The AK4958ECB does not support 3-wire Mode.
Note 36. CCLK rising edge must not occur at the same time as CSN edge.
Note 37. I2C-bus is a trademark of NXP B.V.
Note 38. It is the time of 10% potential change of the CDTIO pin when RL=1k (pull-up or TVDD).
Note 39. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1558-E-02-PB
max
Unit
40
70
ns
ns
70
-
ns
ns
ns
80
ns
ns
ns
80
-
ns
ns
ns
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
0.3
0.3
400
50
kHz
s
s
s
s
s
s
s
s
s
s
pF
ns
2014/08
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[AK4958]
Parameter
Symbol
min
typ
max
Unit
Digital Audio Interface Timing; CL=100pF
DMCLK Output Timing
Period
tSCK
1/(64fs)
s
Rising Time
tSRise
10
ns
Falling Time
tSFall
10
ns
Duty Cycle
dSCK
40
50
60
%
Audio Interface Timing
DMDAT Setup Time
tDSDS
50
ns
DMDAT Hold Time
tDSDH
0
ns
Power-down & Reset Timing
PDN Accept Pulse Width
(Note 40)
tAPD
200
ns
PDN Reject Pulse Width
(Note 40)
tRPD
50
ns
PMADL or PMADR “” to SDTO valid (Note 41)
ADRST1-0 bits =“00”
tPDV
1059
1/fs
ADRST1-0 bits =“01”
tPDV
267
1/fs
ADRST1-0 bits =“10”
tPDV
531
1/fs
ADRST1-0 bits =“11”
tPDV
135
1/fs
VCOM Voltage
Rising Time
(Note 42)
tRVCM
0.6
2.0
ms
Note 40. The AK4958 can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than 200ns for a certain
reset. The AK4958 is not reset by the “L” pulse less than 50ns.
Note 41. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
Note 42. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises up. An
external capacitor of the VCOM pin is 2.2F and the REGFIL pin is 2.2F. The capacitance variation should be
±50%.
MS1558-E-02-PB
2014/08
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[AK4958]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
1/fMCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
MCKO
50%TVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Note 43. MCKO is not available at EXT Master mode.
Figure 5. Clock Timing (PLL/EXT Master mode)
50%TVDD
LRCK
tBLR
tBCKL
BICK
50%TVDD
tDLR
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode)
MS1558-E-02-PB
2014/08
- 25 -
[AK4958]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
MCKO
50%TVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 8. Clock Timing (EXT Slave mode)
MS1558-E-02-PB
2014/08
- 26 -
[AK4958]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRD
tBSD
SDTO
50%TVDD
MSB
tSDS
tSDH
VIH
SDTI
VIL
Figure 9. Audio Interface Timing (PLL/EXT Slave mode)
VIH
CSN
VIL
tCSH
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTIO
R/W
A6
A5
VIL
Figure 10. WRITE Command Input Timing
MS1558-E-02-PB
2014/08
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[AK4958]
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTIO
D2
D1
D0
VIL
Figure 11. WRITE Data Input Timing
VIH
CSN
VIL
VIH
CCLK
Clock, H or L
tCCZ
tDCD
CDTIO
D3
VIL
D2
D1
D0
Hi-Z
50%
TVDD
Figure 12. Read Data Output Timing
MS1558-E-02-PB
2014/08
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[AK4958]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Start
Stop
Figure 13. I2C Bus Mode Timing
tSCK
65%AVDD
DMCLK
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 14. DMCLK Clock Timing
65%AVDD
DMCLK
35%AVDD
tDSDS
tDSDH
VIH2
DMDAT
VIL2
Figure 15. Audio Interface Timing (DCLKP bit = “1”)
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH2
DMDAT
VIL2
Figure 16. Audio Interface Timing (DCLKP bit = “0”)
MS1558-E-02-PB
2014/08
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[AK4958]
PMADL/R bit
or
PMDML/R bit
tPDV
SDTO
50%TVDD
Figure 17. Power Down & Reset Timing 1
tAPD
tRPD
PDN
VIL
Figure 18. Power Down & Reset Timing 2
PMVCM bit
tRVCM
1.15V
VCOM pin
Figure 19. VCOM Rising Timing
MS1558-E-02-PB
2014/08
- 30 -
[AK4958]
PACKAGE (AK4958EG)
32pin BGA (Unit: mm)
Top View
Bottom View
A
3.50.1
0.5
B
6
0.5
5
3.50.1
4
3
2
1
1
F
A
E
D
C
B
C
0.08
 0.15 M C A B
0. 870.13
0.210.05
32 x (0.27~0.37)
A
C
■ Material & Lead finish
Package material: Epoxy Resin, Halogen (Br and Cl) free
Solder ball material: SnAgCuNi (LF35)
MS1558-E-02-PB
2014/08
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[AK4958]
PACKAGE (AK4958ECB)
25pin CSP (Unit: mm)
25 -0.260  0.03
Top View
 0.15 M
C
 0.05 M
C
A
B
A
(0.040)
1
E
A
D
C
B
A
(0.279)
0.4
2.158 0.03
0.585±0.059
0.385±0.025
0.4
1
0.282
2
3
2.164 0.03
4
5
B
0.075 C
0.20  0.030
C
■ Material & Lead finish
Package material: Polyimide Resin, Halogen (Br and Cl) free
Solder ball material: SnAgCu
MS1558-E-02-PB
2014/08
- 32 -
[AK4958]
MARKING (AK4958EG)
4958
XXXX
A1
XXXX: Date code (4 digit)
Pin #A1 indication
MARKING (AK4958ECB)
4958
XXXX
A1
XXXX: Date code (4 digit)
Pin #A1 indication
MS1558-E-02-PB
2014/08
- 33 -
[AK4958]
REVISION HISTORY
Date (Y/M/D)
13/09/13
Revision
00
13/10/25
01
14/08/06
02
Reason
First
Edition
Error
Correction
Page/Line
Contents
139
Spec.
Change
2, 3, 17, 90
Package dimension was corrected. (AK4958EG)
Stand off: 0.16±0.5 → 0.21±0.05
Total thickness: Max 1 → 0.87±0.13
The setting of the video amplifier gain was added. (AK4958EG)
VG1-0 bits = “00”: +6dB
MS1558-E-02-PB
2014/08
- 34 -
[AK4958]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product stipulated
in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to
current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application examples
of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or
completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of AKM or any third party with respect to the information in this document. You are
fully responsible for use of such information contained in this document in your product design or applications.
AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES
ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high
levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily
injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear
facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains,
ships and other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in
finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware, software
and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could
cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this
document for any military purposes, including without limitation, for the design, development, use, stockpiling
or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction
weapons). When exporting the Products or related technology or any information contained in this document,
you should comply with the applicable export control laws and regulations and follow the procedures required
by such laws and regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility
of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the
inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes
no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in
any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS1558-E-02-PB
2014/08
- 35 -