AK4958ECB

[AKD4958ECB-B]
AKD4958ECB-B
AK4958ECB Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD4958ECB-B is an evaluation board for the AK4958, a 24bit stereo CODEC with a microphone/ speaker/ video
amplifiers, and LDO. The AKD4958ECB-B is controlled via USB port, allowing simple evaluation. It features a USB
audio device therefore audio signals can be input through the USB port from a PC. The built-in digital audio interface
realizes interfacing to digital audio systems via optical connector. For analog connections, the AKD4958ECB-B has a
Line output, Microphone input, and Headphone output terminals.
 Ordering Guide
AKD4958ECB-B
---
AK4958 Evaluation Board
(Control software and USB cable are included in this package. )
FUNCTION
• DIR/DIT with optical input/output
• With USB-Audio device
• Equipped with three digital audio interface
- Optical Input / Output
- USB Input
- 10-pin header for external interfaces
• Analog input / output circuit for Line output, Mic input and Headphone output, and
Micro-speaker
• USB port for board control
SPDIF
-OUT
HP
Out
SPDIF
-IN
PORT3
Speaker
AK4371
USB
(Audio)
PCM
2902B
MicIn
AK4118A
LineOut
AK4958ECB
Flash
Rom
USB
(CTRL)
PIC18F4550
LDO [ T1 ]
(+5V => +3.3V)
VIN
VOUT
for AK4371
LDO [ T2 ]
(+5V => +3.3V)
LDO [ T3 ]
(+5V => +1.8V)
3.3V
1.8V
GND
Figure 1.AKD4958ECB-B Block Diagram
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 Operation Sequence
1) Set up the Power Supply Lines.
2) Setup the Audio I/F Evaluation Mode.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting for External Slave Mode.
(1-2) Setting for External Master Mode.
(1-3) Setting for PLL Master Mode.
(2) Evaluation of D/A using DIR of AK4118A.
(2-1) Setting for External Slave Mode. < Default >
(2-2) Setting for External Master Mode.
(3) Evaluation of A/D, D/A using external clocks.
(3-1) Setting for External Slave Mode.
(3-2) Setting for External Master Mode.
(3-3) Setting for PLL Slave Mode (Reference: BICK).
3) Jumper pins and SW Setting.
(1) Setting of other jumper pins.
(2) Setting of SW.
4) Power on.
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1) Set up the Power Supply Lines.
(1-1) In case of using the U7 (CTRL) connector. < Default >
R42 and R43 must be “Short (0ohm)”.
JP9
JP10
Figure 2.Setting of jumper pins when using the U7 (CTRL) connector.
Name of Jack
Reference No.
Default Setting
CTRL
U7
+5V
3.3V
1.8V
GND
TM1
TM2
TM3
Open
Open
Open
Using
For regulator (T1, T2 and T3) and
AK4118A, AK4371 and Digital Logic.
For AVDD of AK4958
For DTVDD of AK4958
For ground
Table 1.Set up of power supply lines
(1-2) In case of using the power supply pads.
R42 and R43 must be “Open”.
JP9
JP10
Figure 3.Setting of jumper pins when using the power supply connectors.
Name of Jack
Reference No.
Default Setting
CTRL
U7
+5V
3.3V
1.8V
GND
TM1
TM2
TM3
+2.8V~+3.6V [ typ :+3.3V ]
+1.6V~+2.0V [ typ:+1.8V ]
0V
Using
For regulator (T1, T2 and T3) and
AK4118A, AK4371 and Digital Logic.
For AVDD of AK4958
For DTVDD of AK4958
For ground
Table 2.Set up of power supply lines (Note 1)
Note 1.Each supply line should be distributed from the power supply unit.
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2) Setup the Audio I/F Evaluation Mode.
In case of using the AK4118A when evaluating the AK4958, both the AK4958 and AK4118A’s audio interface
formats must be matched.
Refer to the datasheet for AK4958’s audio interface format, and AK4118A’s audio interface format (Table 4).
The AK4118A operates at sampling frequency of 32 kHz or more. If the sampling frequency is slower than 32
kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please
use other mode.
Refer to the datasheet for register setting of the AK4958.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting for External Slave Mode
X2 (X’tal) and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN) and
PORT3.MCKI, BICK and LRCK are supplied from the AK4118A, and SDTO of the AK4958 is output to the
AK4118A. In addition, registers of the AK4958 should be set to “External Slave Mode” and setting of
AK4118A should be set to “Master Mode”.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 4.Setting of jumper pins for External Slave Mode
(1-2) Setting for External Master Mode
X2 (X’tal) and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN) and
PORT3.MCKI is supplied from the AK4118A, and BICK, LRCK and SDTO of the AK4958 is output to the
AK4118A. In addition, registers of the AK4958 should be set to “External Master Mode” and setting of
AK4118A should be set to “Slave Mode”.
JP8
3
XTI
3
MCKO
MCKO
MCKI
JP6
Figure 5.Setting of jumper pins for External Master Mode
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(1-3) Setting for PLL Master Mode
A reference clock of PLL is selected among the input clocks supplied to MCKI pin. The required clock to the
AK4958 is generated by an internal PLL circuit.
PORT3 and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN). MCKI is
supplied from the PORT3, and MCKO, BICK, LRCK and SDTO of the AK4958 is output to the AK4118A.
In addition, registers of the AK4958 should be set to “PLL Master Mode” and setting of AK4118A should be
set to “Slave Mode”.
R46 must be “Open”.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 6.Setting of jumper pins for PLL Master Mode
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(2) Evaluation of D/A using DIR of AK4118A.
Setting for input signal of AK4118A.
When using USB audio device, connect cable with the U3 (Audio) on board and USB port of PC.
(a) Select Optical jack <Default>
(b) Select USB Audio device
JP5
JP5
3
USB-IN
3
OPT-IN
USB-IN
OPT-IN
Figure 7.Setting of jumper pins for input signal of AK4118A
(2-1) Setting for External Slave Mode < Default >
PORT1 (SPDIF-IN) is used. Nothing should be connected to PORT2 (SPDIF-OUT) and PORT3.
MCKI, BICK, LRCK and SDTI are supplied from the AK4118A. In addition, registers of the AK4958 should
be set to “External Slave Mode” and setting of AK4118A should be set to “Master Mode”.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 8.Setting of jumper pins for External Slave Mode
(2-2) Setting for External Master Mode
PORT1 (SPDIF-IN) is used. Nothing should be connected to PORT2 (SPDIF-OUT) and PORT3.
MCKI and SDTI are supplied from the AK4118A, and BICK and LRCK of the AK4958 is output to the
AK4118A.In addition, registers of the AK4958 should be set to “External Master Mode” and setting of
AK4118A should be set to “Slave Mode”.
JP8
3
XTI
3
MCKO
MCKO
MCKI
JP6
Figure 9.Setting of jumper pins for External Master Mode
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(3) Evaluation of A/D, D/A using PORT3.
(3-1) Setting for External Slave Mode
Registers of the AK4958 should be set to “External Slave Mode”.
R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.
AK4958
DSP or P
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 10.External Slave Mode
PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).
MCLK, BICK, LRCK, and SDTI are input from PORT3 and SDTO of the AK4958 is output to the PORT3.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 11.Setting of jumper pins for External Slave Mode
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(3-2) Setting for External Master Mode
Registers of the AK4958 should be set to “External Master Mode”.
R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.
AK4958
DSP or P
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
32fs or 64fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 12.External Master Mode
PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).
MCLK and SDTI are input from PORT3 and BICK, LRCK and SDTO of the AK4958 is output to the
PORT3.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 13.Setting of jumper pins for External Master Mode
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(3-3) Setting for PLL Slave Mode (Reference Clock: BICK pin)
Registers of the AK4958 should be set to “PLL Slave Mode” (Reference Clock: BICK pin).
R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.
AK4958
DSP or P
MCKO
MCKI
32fs, 64fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14.PLL Slave Mode (PLL Reference Clock: BICK pin)
PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).
BICK, LRCK and SDTI are input from PORT3. SDTO of the AK4958 is output to the PORT3.
MCKI
JP8
3
XTI
3
MCKO
MCKO
JP6
Figure 15.Setting of jumper pins for PLL Slave Mode
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3) Jumper pins and SW Setting.
(1) Setting of other jumper pins.
[JP11]: Not to Use.
[JP20 (RIN)]: The selection of RIN1 pin.
OPEN
: No connected.
SHORT
: Connect to RIN1pin. < Default >
[JP21 (MPWRR)]: The selection of MIC-power of RIN pin.
OPEN
: MIC-power is not supplied. < Default >
SHORT
: MIC-power is supplied.
[JP22 (MPWRL)]: The selection of MIC-power of LIN pin.
OPEN
: MIC-power is not supplied. < Default >
SHORT
: MIC-power is supplied.
[JP23 (LIN)]: The selection of LIN1 pin.
OPEN
: No connected.
SHORT
: Connect to LIN1pin. < Default >
[JP25 (SPN)]: The selection of micro-speaker (LS1).
OPEN
: No connected.
SHORT
: Connect to micro-speaker. < Default >
[JP26 (SPP)]: The selection of micro-speaker (LS1).
OPEN
: No connected.
SHORT
: Connect to micro-speaker. < Default >
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(2) Setting of SW.
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[S1] (SW DIP-5): Mode setting for AK4118A.
No.
Name
ON (“H”)
OFF (“L”)
1
2
3
DIF2
DIF1
DIF0
Audio I/F Format Setting for AK4118A
See Table 4
4
OCKS1
5
PDN
Default
ON
OFF
OFF
Master Clock setting for AK4118A
See Table 5
AK4118A is Power-up.
AK4118A is Power-down
OFF
ON
Table 3. Mode Setting for AK4118A
Mode
DIF2
DIF1
DIF0
DAUX
SDTO
0
1
2
3
4
5
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
6
H
H
L
24bit, Left justified
24bit, Left justified
H/L
I
7
H
H
H
24bit, I2S
24bit, I2S
L/H
I
BICK
I/O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64
I
-128fs
64
I
-128fs
Default
Table 4.Audio I/F Format Setting for AK4118A
OCKS1
L
H
MCKO1
256fs
512fs
Default
Table 5.Master Clock setting for AK4118A
4) Power on.
After power-up, the AK4958 and the AK4118A should be reset once.
Reset and power-up sequence of the AK4118A.
1. S1 (5): OFF; power-down and reset.
2. S1 (5): ON; power-up.
Reset and power-up sequence of the AK4958.
1. To start the control software.
2. [PDN: H (L)] button is set to [PDN: L] (Power-down and Reset).
3. [PDN: H (L)] button is set to [PDN: H] (Power-up).
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 Indication for LED
[D1] (FLASH-ROM) : Not to Use.
 Control Port
It is possible to control AKD4958ECB-B via general USB port. Connect cable with the U7 (CTRL) on board and
PC.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
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■ Analog Input / Output Circuits
1) Input circuit
(1-1) MIC/LINE1 input circuit (except for Digital-MIC circuit).
MPWR
2.2k
2.2k
JP21
MPWRR
J3
MIC
JP22
MPWRL
6
1u
JP20
RIN
4
3
1u
JP23
LIN
RIN1
LIN1
Figure 16.Circuit diagram of MIC/LIN1 input
(1-2) Video input circuit.
2
3
4
5
J10
VIN
1
VIN
75
0.047u
Figure 17.Circuit diagram of Video input
(1-3) BEEP input circuit.
1
TP20
BEEP
1u
0
BEEP
Figure 18.Circuit diagram of BEEP input
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2) Output circuit
(2-1) LINE output circuit.
ROUT
LOUT
1u
220
6
1u
220
4
3
20k
J2
LINE
20k
Figure 19.Circuit diagram of LINE output
(2-2) Video output circuit.
1
75
VOUT
J11
VOUT
2
3
4
5
Figure 20.Circuit diagram of Video output
(2-3) Speaker output circuit.
SPP
JP26
LS1
SPEAKER
SPP
(open)
SPN
JP25
SPN
Figure 21.Circuit diagram of Speaker output
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Control Software Manual
■ Evaluation Board and Control Software Settings
1. Set up the evaluation board as needed, according to the previous terms.
2. Connect the evaluation board and PC with a USB cable.
3. The USB control is recognized as HID (Human Interface Device) on the PC
4. Double-click the icon “akd4958ecb-b.exe” to open the control program. (Note 3)
When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push
the [Port Reset] button.
5. Begin evaluation by following the procedure below.
Figure 22. Window of Control Soft
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■ Operation Overview
Function and Register map are controlled by this control software. These controls may be selected by the upper tabs.
Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
1. [Port Reset]: Resets the connection to PC.
Click this button when connecting USB cable after the control software set up..
2. [Write Default]: Register Initialization.
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executes write commands for all registers displayed. (Note 2)
4. [All Read]: Executes read commands for all registers displayed. (Note 2)
5. [Save]: “Save Address of Register” dialog box pops up.
6. [Load]: Executes data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box pops up.
8. [Sequence]: “Sequence” dialog box pops up.
9. [Sequence (File)]: “Sequence (File)” dialog box pops up.
10. [Read]: Reads current register settings and displays to the register area (on the right of the main window).
This is different from [All Read] button as it does not reflect to the register map. It only displays register
values in hexadecimal numbers.
11. [PDN: H (L)]: Setup of an input at PDN pin. (Note 3)
Note 2. After [All Write] or [All Read] are executed, “RBANK bit” is set to "1".
Note 3. After Power-up the evaluation board, put the “PDN” button to “L” and return to “H” to release the
power-down state. After “PDN” button becomes “H”, “Dummy Command” is executed.
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■ Tab Functions
1. [Function] Tab: Function Control
When a button in the “Function” frame is clicked, a sequential process is executed.
When other button is clicked, the setting dialog opens.
(Refer to the “■ Sequential process” section for details of each dialog box setting, or “■ Dialog Box” section for
details of each dialog box setting.)
Figure 23. [Function] Window
[Function] button
Setting dialog button
: Executes a sequential process shown on each button. (Refer to 1- 1)
: Opens a setting dialog. (Refer to 1- 2)
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1- 1. [Function] Button
Figure 24. [Function] Button
A function button executes the sequence process shown on the each button and updates several registers.
These functions are mainly for path settings.
Function Name
Rec_MIC+18dB_ALC
Description
Input
Output
Path
MIC Input Recording
(Stereo)
Digital MIC Input
Recording (Stereo)
LIN1,
RIN1
DMDAT
SDTO
Playback_Lineout
Stereo Line Output
SDTI
Loopback_Lineout
Loopback
(MIC Input Recording,
Stereo Line Output)
SPK Output
(Bass Boost ON)
LIN1,
RIN1
LOUT,
ROUT
LOUT,
ROUT
LIN1,RIN1→MIC-AMP(+18dB)→ADC
→Digital Filter→SDTO
DMDAT→Digital Filter→SDTO
(When Digital MIC used, LIN1 changes to
DMDAT.)
SDTI→Digital
Filter→DAC→LOUT,ROUT
LIN1,RIN1→ADC→
Digital Filter→DAC→LOUT,ROUT
SPP,
SPN
SDTI→Digital Filter→Bass
Boost→DAC→SPP,SPN
Rec_D-MIC_ALC
Playback_SPK
(Bass Boost ON)
SDTI
SDTO
Table 6. Sequence Process Setting
* The setting of Clock mode and I/F mode are not changed. The default values are follows.
Clock Mode
: EXT mode (slave)
I/F mode
: 24bit MSB Justified
Sampling Frequency : 48 kHz
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1- 2. Setting Dialog Button
Figure 25. Setting Dialog button
[MIC - ADC Setting] button
[Digital MIC Setting] button
[System Clock Audio I/F] button
[ALC Setting] button
[DAC Setting] button
[Digital Filter] button
[BEEP Setting] button
[MIC Gain Adjustment] button
[Video Setting] button
[Bass Boost 3 Band DRC] button
[AK4371 Setting] button
: Opens “MIC_ADC Setting” dialog box.
: Opens “Digital MIC Setting” dialog box.
: Opens “System Clock & Audio I/F” dialog box.
: Opens “ALC Setting” dialog box.
: Opens “DAC_LINE/SPK Setting” dialog box.
: Opens “Programmable Digital Filter Setting” dialog box.
: Opens “BEEP Setting” dialog box.
: Opens “MIC Gain Adjustment” dialog box.
: Opens “Video Setting” dialog box.
: Opens “Bass Boost & 3 Band DRC control” dialog box.
: Opens “AK4371” dialog box.
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2. [REG] [RBANK0] [RBANK1] Tab: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch. The register is updated by mouse operation.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 26. [REG] Window
Note 4. “RBANK bit” is changed automatically at the time of each register Write/Read of BANK0 and
BANK1.
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2-1. [Write]: Data Write Dialog Box
Select the [Write] button located on the right of the each corresponding address when changing two or more
bits on the same address simultaneously.
Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When the checkbox next to the bit name is checked, the data will become “1”. When the checkbox is not
checked, the data will become “0”.
Click [OK] to write the set values to the registers, or click [Cancel] to cancel this setting.
Figure 27. [Register Set] Window
2-2. [Read]: Data Read Dialog Box
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray).
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■ Dialog Box
1. [Save]: [Save Address of Register] Dialog Box
Click the [Save] button in the main window for save address setting dialog box.
Figure 28. [Save] Window
[All Address] check box
[RBANK=1] check box
[Start Address] edit box
[End Address] edit box
[OK] button
[Cancel] button
: When the [All Address] checkbox is checked, all register settings will be saved.
: Checked: Register setting in RBANK1 will be saved.
Unchecked: Register setting in REG and RBANK0 will be saved.
: When the [All Address] check box is not checked, set starts register address to save.
: When the [All Address] check box is not checked, set end register address to save.
: Selects a file to save and saves register settings.
: Cancel and finish this process.
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2. [All Reg Write]: [All Register Write] Dialog Box
Click the [All Reg Write] button in the main window to open register setting file window show below.
Register setting files saved by the [Save] button may be applied.
Figure 29. [All Reg Write] Window
[Open (left)] button
[Write] button
[Help] button
[Save] button
[Open (right)] button
[Close] button
[All Write] flame
: Selects a register setting file (*.akr).
: Executes register write with selected file setting.
: Opens a help window.
: Saves a register setting file assignment. File name is “*.mar”.
: Opens a saved register setting file assignment “*. mar”.
: Closes the dialog box and finish the process.
: Executes all register write.
Selected files are executed in descending order.
[Start] button
: Start the register writing.
[Stop] button
: Stop the register writing.
[Interval time] edit box : Set interval time to start next register setting file. (5msec ~ 10,000msec)
[Current No] edit box : The file number which is being processed is displayed. (File number is assigned 1-10
from top to bottom.)
~ Operating Suggestions ~
1. Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mar” should
be stored in the same folder.
2. hen register settings are changed by the [Save] button in the main window, re-read the file to reflect new
register settings.
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3. [Sequence]: [Sequence] Dialog Box
Click the [Sequence] button in the main window to open register sequence setting dialog box
Register sequence can be set in this dialog box.
Figure 30. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process.
1. Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select items>
・No use
・Register
・Reg_Mask
・Interval
・Stop
・End
: Not using this address
: Register write
: Register write (Masked)
: Takes an interval
: Pauses the sequence
: Ends the sequence
Changes of RBANK bit setting must be included in the sequence.
Please pay attention to the RBANK bit value when starting the sequence since the process could be
changed depending on the starting value of RBANK bit.
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2. Input sequence
[Address] : Data address
[Data]
: Write data
[Mask]
: Mask
This value “ANDed” with the write data becomes the input data. The bits which corresponding
Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of
this software is used. “Write Default” must be executed after power up the AK4958 or when
the AK4958 is reset by the PDN pin since the storage data and register values are different.
This is the actual write data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval] : Interval time
Valid boxes for each process command are shown below.
・No use
: None
・Register
: [ Address ], [ Data ], [ Interval ]
・Reg_Mask
: [ Address ], [ Data ], [ Mask ], [ Interval ]
・Interval
: [ Interval ]
・Stop
: None
・End
: None
~ Control Buttons ~
Functions of Control Button are shown below.
[DEL] button
: Checked step is deleted.
[INS] button
: The last deleted step is inserted to checked step.
[Start Step] select : Select start step.
No.1 Step
: Start from No.1 step.
Checked Step
: Start from checked step.
[Start] button
: Executes the sequence.
[Stop] button
: Stops the sequence.
[Help] button
: Opens a help window.
[Save] button
: Saves sequence settings as a file. The file name is “*.aks”.
[Open] button
: Opens a sequence setting file “*.aks”.
[Close] button
: Closes the dialog box and finishes the process.
~ Stop of the Sequence ~
When “Stop” is selected in the sequence, the process is paused at this step and restart step number is
checked.
It starts again from the checked step by clicking the [Start] button. When the process at the end of sequence
is finished, “Step No.1” of [start step] is selected automatically.
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4. [Sequence (File)]:[Sequence by *.aks file] Dialog Box
Click the [Sequence (File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 31. [Sequence (File)] Window
[Open (left)] button
[Start] button
[Start All] button
: Opens a sequence setting file (*.aks).
: Executes the sequence by the setting of selected file.
: Executes all sequence settings.
Selected files are executed in descending order.
[Stop] button
: Stops the sequence process.
[Help] button
: Opens a help window.
[Save] button
: Saves a sequence setting file assignment. The file name is “*.mas”.
[Open (right)] button : Opens a saved sequence setting file assignment “*. mas”.
[Close] button
: Closes the dialog box and finishes the process.
~ Operating Suggestions ~
1. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” is selected in the sequence, the process will be paused and a pop-up message will appear.
Click “OK” to continue the process.
Figure 32. [Sequence Pause] Window
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5. [MIC – ADC Setting]: [MIC – ADC Setting (Recording)] Dialog Box
Click the [MIC-ADC Setting] button in the main window to open MIC and ADC setting dialog box.
ADC, MIC gain and sensitivity setting are available. (Input is LIN1/RIN1 fixation)
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 33. [MIC-ADC Setting] Window
In the following cases, PMVCM bit is set to "1" automatically.
Since PMVCM bit is not set to "0" even if it returns each setup, please operate a register map directly.
1). When MIC Power (PMMP bit) is Power-up
2). When MIC Amp Power (PMMICL/R bit) is Power-up
3). When choice other than [All”0”, All”0”] are chosen by combo box of “Input Signal Select (PMADL/R bit)”
(Note 5)
Note 5. When “1)” executes and the path of a digital filter is selected, "1" is set to PMPFIL bit. Since a
PMPFIL bit is not set to "0" even if it returns each setup, please operate a register map directly.
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~ Gain Control by Slider ~
The volume can also be changed by slider.
When a value is input to the edit box, the slide bar moves automatically to the value set in the edit box.
Slide bar is
moved to the
selected value.
The value which can be set up is chosen
automatically.
Figure 34. Volume Slider Control
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6. [Digital MIC Setting]: [Digital MIC Setting] Dialog Box
Click the [Digital MIC Setting] button in the main window to open Digital MIC setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 35. [Digital MIC Setting] Window
PMVCM bit is set to “1” automatically when the “Input Signal Select (PMDML, PMDMR bit)” setting is not
[All”0”, All”0”]. Set PMVCM bit = “0” on the register map directly when changing the input signal select to [All”0”,
All”0”] since PMVCM bit does not return to “0”.
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7. [System Clock Audio I/F]: [System Clock Audio I/F] Dialog Box
Click the [System Clock Audio I/F] button in the main window to open system clock and Audio I/F setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 36. [System Clock Audio I/F] Window
When clock mode is changed to “PLL Mode” from “EXT Mode”, PMVCM bit is set to "1" automatically.
Even if “Clock Mode” returns to “EXT Mode”, PMVCM bit is not set to “0”. Please operate a register map directly.
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8. [ALC Setting]: [ALC Setting] Dialog Box
Click the [ALC Setting] button in the main window to open ALC setting dialog.
ALC parameters are controlled in this dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 37. [ALC Setting] Window
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8-1. Simulation of the point of inflection in recording
The following dialog for ALC curve will be displayed if "Output Level" button on "ALC Setting" dialog is
pushed.
REF (input-output characteristics) of ALC is displayed.
Figure 38. ALC Input-output characteristics (default settings)
Figure 39. ALC Input-output characteristics (change settings)
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~ Volume Read ~
The ALC input level (INVOL) and ALC volume (VOL) can be readout by the [Start] button on the bottom right of
the dialog (It changes to [Stop] when clicked).
The register read of INVOL and VOL will be continued with the interval time set in the edit box beside the start
button until the stop is clicked.
The read value is displayed on the progress control
and edit box.
The Interval of read-out can set up in 100~1000 msec.
Figure 40. Volume Progress Control
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9. [DAC Setting]: [DAC_LINE/SPK Setting (Playback)] Dialog Box
Click the [DAC Setting] button in the main window to open DAC setting dialog.
Register setting of DAC output select and output gain are available.The settings on this dialog are
interlocked with the settings on the register map.
(Refer to the datasheet for register definitions.)
Figure 41. [DAC Setting] Window
In the following cases, PMVCM bit is set to "1" automatically.
Set PMVCM bit = “0” on the register map directly since PMVCM bit does not return to “0” if the each condition is
released.
1). When DAC Power (PMDAC bit) is Power-up
2). When SPK-Amp (PMSPK, SPPSN, DACS bit) are Enable
3). When Line Out (PMLO, LOPS, DACL bit) are Enable
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10. [Digital Filter]: [Filter Setting] Dialog Box
Click the [Digital Filter] button in the main window to open Digital Filter setting dialog.
Coefficient and frequency of digital filter are calculated on this dialog.
(Refer to the datasheet for register definitions.)
Figure 42. [Digital Filter] Window
[Register Setting] button
: Opens the register setting dialog.
Register writes of a filter factor are also executed.
[F Response] button
: Opens the frequency response plot dialog [Filter Plot].
Register writes of a filter factor are also executed.
[Write] button
: Calculation of all the filters and coefficient writing are executed.
[Reg Map to Fc/Plot] check box :
When [Reg Map to Fc/Plot] is checked, the coefficient currently written in the
register map is reflected to each parameter.
Gain of HPF and LPF needs to be set to 1.0. When carrying out coefficient
writing by [Coefficient Write] etc. on this dialog, Gain of HPF and LPF is
always 1.0.
EQ Sequence for Noise [ON/OFF] button :
ON: EQCx bit, EQxT bits and EQxG bits are set for noise processing.
OFF: The bits will return to the state of before the button is set to ON.
[Close] button
: Closes the dialog box and finishes the process.
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10-1. Parameter Setting
Please set a parameter of each Filter.
Parameter
Sampling Rate
Detail
Setting Range
Sampling Frequency (fs)
8, 11.025, 12, 16, 22.05, 24,
32, 44.1 or 48kHz
HPF
HPF1 Cut Off Frequency
HPF2 Cut Off Frequency
AHPF
AHPF Detection Level
AHPF Suppressor Level
High Pass Filter 1 cut off frequency
High Pass Filter 2 cut off frequency
Auto High Pass Filter Detection Level
Auto High Pass Filter Suppressor Level
3.7×fs/48 ~ 236.8×fs/48 (kHz)
0.0001  fc/fs < 0.497
0.5(weak) ~ 4.0(strong)
weak, medium1, medium2, strong
LPF
Cut Off Frequency
Low Pass Filter cut off frequency
0.05  fc/fs < 0.497
FIL3
Cut Off Frequency
Filter type
Gain
FIL3 cut off frequency
The selection of filter type
Gain
0.0001  fc/fs < 0.497
LPF or HPF
-10dB  Gain  0dB
EQ0 Pole frequency
EQ0 Zero-point frequency
Gain
Gain2
0.0001  fc/fs < 0.497
0.0001  fc/fs < 0.497
-20dB  Gain  +12dB
0 / +12 / +24dB
EQ0
Pole Frequency
Zero-point Frequency
Gain
Gain2
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Band Width
EQ1-5 Gain
EQ1-5 Center frequency
EQ1-5 Band width
EQ1-5 Gain
(Note 6)
(Note 7)
0.003 < fc/fs < 0.497
0.05  fc/fs
-1  Gain <3
Table 7. Parameter Setting of [Filter Setting]
Note 6. A gain difference is a bandwidth of 3dB from center frequency.
Note 7. When a gain is “-1”, EQ becomes a notch filter.
“HPF1 Enable”, “AHPF Enable”, “HPF2 Enable”, “LPF Enable”, “FIL3 Enable”, “EQ0 Enable”, “EQ1”,
“EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform automatic
correction of the center frequency of the notch filter is executed.
Figure 43. Filter ON/OFF Check Box
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10-2. [Register Setting]: [Register Setting for Filter] Dialog Box
Click the [Register Setting] button, a register set value is displayed. When a value out of a setting range is set,
error message is displayed, and a calculation of register setting is not carried out.
Figure 44. [Register Setting for Filter] Window
Followings are the cases when a register set value is updated.
1. When [Register Setting] button was pushed.
2. When [F Response] button was pushed.
3. When [Write] button was pushed.
4. When [UpDate] button was pushed on a frequency characteristic indication window.
5. When Enter or the Tab key is pressed after setting each parameter.
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10-3. [F Response]: [Filter Plot] Dialog Box
A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also
updated.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 45. [F Response] Window
[Frequency Range] edit box
[UpDate] button
[Gain/Phase] radio button
[Log View] check button
[Close] button
: The width of the frequency display is specified.
: It draws in the graph again.
: Switch of “Gain/Phase” display.
: Switch of “Linear/Log” display.
: Closing the dialog box and finish the process.
~ Adjustment of vertical range ~
1.[ Y-axis Ref ] edit box
2.[Vertical slider]
3.[Horizontal slider]
: Display setting of center value.
: Movement of vertical display.
: Adjustment of the horizontal display.
(The left side reduces, and the right side expands.)
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10-4. 5-BandEQ operation on Filter Plot screen
When EQ (1 ~ 5) is turning “ON”, a green number is displayed on the Filter Plot dialog box.
This number shows the setting of the center frequency and the gain of each EQ.
(The horizontal coordinates of a number is the center frequency of EQ, and the vertical ordinate is a gain of EQ
(-1 ~ 2.99).)
The number under the display is operated with the mouse, and it is possible to set the filter characteristic on this
screen.
The center frequency and the gain setting are changed by moving the mouse while left-clicking.
The setting of the bandwidth is changed by moving the mouse while right-clicking.
After operating the mouse
the value of the center frequency and the gain is
updated.
The number is selected.
The movement operation is done while
left-clicking.
Figure 46. Filter Setting (Left-clicking operation)
After operating the mouse
the value of the bandwidth is updated.
Figure 47. Filter Setting (Right-clicking operation)
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10-5. Simulation of Fil3 Filter
Setting of Stereo-MIC
[L-ch Level]/[R-ch Level] edit box
[Distance] edit box
[Angle] edit box
Default
Fil3: OFF
: Gain mismatch of stereo MIC sensitivity are set.
: The distance between the sound source and the MIC is set.
: The angle between the sound source and the MIC is set.
FIL3: ON, Filter Type: LPF, EQ0: ON
Figure 48. Stereo Separation Emphasis Operation
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10-6. About “Notch Auto Correct”
If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter.
When the center frequency of two or more notch filters is adjacent, the gap is generated in the center frequency.
(Figure 49) When “Notch Auto Correct” button is checked, the center frequency of the notch filter is
automatically corrected. The gain setting of the automatic correction function is effective and only EQ of “-1” is
effective. (Figure 50)
This automatic compensation is effective to EQ which set the gain as "-1". (Note 8)。
Note 8. There is a possibility that the automatic compensation is not correctly done when the width of the
center frequency is smaller than that of the bandwidth setting.
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 49. 5Band Equalizer Operation (Not Check of “Notch Auto Correct”)
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 50. 5Band Equalizer Operation (Checked of “Notch Auto Correct”)
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10-7. Common Gain Sequence for Noise.
If “EQ Sequence for Noise (ON/OFF)” button is pushed, setup bit about EQ2-5 shown below are changed.
When the button pushed to OFF, each setup is returned the state of before pushing a button.
Please use the button when it expected that a noise continues.
Figure 51. Equalizer Gain Setting
Button ON:EQCx bit: OFF, EQxG5-0 bits: 0x3F (-0.03dB), EQxT1-0 bits: 00 (256/fs)
Figure 52. Equalizer Gain Setting (Setting for Noise button is “ON”)
Button OFF:the state of before pushing a button.
Figure 53. Equalizer Gain Setting (Setting for Noise button is “OFF”)
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11. [BEEP Setting]: [BEEP Setting] Dialog Box
Click the [BEEP Setting] button in the main window to open BEEP setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 54. [BEEP Setting] Window
When BEEP Input Power (PMBP bit) is Power-up, PMVCM bit is set to "1" automatically.
Since PMVCM bit is not set to "0" even if it returns the setup, please operate a register map directly.
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12. [MIC Gain Adjustment]:
[MIC Gain Adjustment] Dialog Box
Click the [MIC Gain Adjustment] button in the main window to open MIC Gain Adjustment dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 55. [MIC Gain Adjustment] Window
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~ ALC Volume Read ~
When the [Start] button on the top right of the dialog is clicked, reading “RMG” register is executed.
This reading continues at intervals of 100msec until the stop button is pushed.
MIC sensitivity is
displayed.
Figure 56. Reading ALC Input Level
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~ MIC Gain Auto Adjustment ~
If “Automatically” check button is checked, MIC gain is adjusted automatically, when reading is stopped.
Figure 57. End message of adjustment
The gain of MIC with a larger
read-out level is lowered so that it may
be set to loser Level of another MIC.
Figure 58. MIC Gain auto adjustment
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13. [Video Setting]: [Video Setting] Dialog Box
Click the [Video Setting] button in the main window to open Video Setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 59. [Video Setting] Window
When Composite Video Block Power (PMV bit) is Power-up, PMVCM bit is set to "1" automatically.
Since PMVCM bit is not set to "0" even if it returns setup, please operate a register map directly.
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14. [Bass Boost 3 Band DRC]: [Bass Boost & 3 Band DRC control] Dialog Box
Click the [Bass Boost 3 Band DRC] button in the main window to open Bass Boost and 3 Band DRC setting
dialog.
Coefficient and frequency of digital filter are calculated on this dialog.
(Refer to the datasheet for register definitions.)
Figure 60. [Bass Boost & 3 Band DRC control] Window
[Write Bass Boost Setting] button :
Calculation of all the filters and coefficient writing are performed
(for Bass Boost).
[Write] button
: Calculation of all the filters and coefficient writing are performed (for 3 Band DRC).
[F Response] button
: Opens the frequency response plot dialog [DRC Filter Plot].
[DRC Curve] button
: Opens the DRC plot dialog [DRC Curve].
[Close] button
: Closes the dialog box and finishes the process.
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14-1. Parameter Setting
Please set a parameter of Bass Boost Block.
Parameter
Sampling Rate
Detail
Sampling Frequency (fs)
Setting Range
8, 11.025, 12, 16, 22.05, 24,
32, 44.1 or 48kHz
HPF
HPF4
High Pass Filter 4 cut off frequency
250Hz  fc
Low Pass Filter 2 cut off frequency
500Hz  fc
LPF
LPF2
BPF1-3
BPF1-3 Center Frequency
BPF1-3 Band Width
BPF1-3 Center frequency
BPF1-3 Band Width
250Hz  fc  3000Hz
40Hz  fc  300Hz
Bass Boost Block
Boost Level
Bass Boost Level
0: Mute、
20* log10 (1/4) ~ 20* log10 (63/4)
Table 8. Parameter Setting of [Bass Boost Function]
Figure 61. Bass Boost ON/OFF setting button
Please set a parameter of DRC Block.
Parameter
Sampling Rate
Detail
Sampling Frequency (fs)
Setting Range
8, 11.025, 12, 16, 22.05, 24,
32, 44.1 or 48kHz
Dynamic Volume Control
Low Frequency Range
LPF
Low Pass Filter cut off frequency
0.002  fc/fs
High Pass Filter cut off frequency
Low Pass Filter cut off frequency
0.0001  fc/fs
0.05  fc/fs
High Pass Filter cut off frequency
0.0001  fc/fs
Middle Frequency Range
HPF
LPF
High Frequency Range
HPF
Table 9. Parameter Setting of [DRC Function]
Please control ON/OFF by the check button of "3 Band DRC ON."
Dynamic Volume is set to “ON” when the check button is checked.
Figure 62. DRC ON/OFF setting button
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14-2. Frequency Response
A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also
updated.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 63. A frequency characteristic indication result
[Frequency Range] edit box
[UpDate] button
[Gain/Phase] radio button
[Close] button
: The width of the frequency display is specified.
: It draws in the graph again.
: Switch of “Gain/Phase” display.
: Closing the dialog box and finish the process.
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14-3. Filter Setting
If a check box of "3 Band DRC ON" on "Bass Boost & 3 Band DRC control" dialog is checked and the button of
“F Response” is pushed, the frequency response of each 3 band and all band will be displayed.
Movement can be performed by
left-clicking a mouse on L/M.
A display is updated
after movement.
Figure 64. Filter Setting (Left-clicking operation)
A display is updated after
setting change.
Figure 65. Filter Setting (Middle Frequency Range Selecting)
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14-4. Dynamic Volume Control
The following dialog for DVLC or DRC curve will be displayed if "DRC Curve" button on "Bass Boost & 3 Band
DRC control" dialog is pushed.
When DVLC frequency band ("LOW", "MIDDLE" or "HIGH") is chosen with the radio button of the upper part
of a screen, the DVLC curve will be displayed.
A preset value can be changed by screen operation.
The frequency band of the DVLC is chosen at
this frame. Each band is displayed by specified
color that shows below.
Red: LOW
Blue: MIDDLE
Green: HIGH
Register map
Inflection point of DVLC
curve.
A display is updated after
movement.
Movement can be performed by
left-clicking.
Figure 66. DVLC Curve Setting
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14-5. Dynamic Range Control
The following dialog for DVLC or DRC curve will be displayed if "DRC Curve" button on "Bass Boost & 3 Band
DRC control" dialog is pushed.
When DRC is chosen with the radio button of the upper part of a screen, the DRC curve will be displayed.
A preset value can be changed by screen operation.
Register map
Movement can be performed by
left-clicking.
A display is updated after
movement.
Figure 67. Dynamic Range Control Setting
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15. [AK4371 Setting]: [AK4371 Setting] Dialog Box
Click the [AK4371 Setting] button in the main window to open AK4371 Setting dialog.
When "Power-Down" button is pushed, Clock Mode (32fs or 64fs) and Audio I/F (MSB, I2S) of AK4958 is
checked and AK4371 is set up automatically.
(Refer to the datasheet for register definitions of the AK4371.)
Figure 68. [AK4371 Setting] Window
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■ Sequential process
1. [Rec_MIC+18dB_ALC]
When [Rec_MIC+18dB_ALC] button in the main window is clicked, the sequence for MIC input Settings (stereo)
is executed. (Note 9)
[MIC-ADC Setting] Window
[ALC Setting] Window
Figure 69. [Rec_MIC+18dB_ALC] Setting
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2. [Rec_D-MIC ALC]
When [Rec_D-MIC ALC] button in the main window is clicked, the sequence for Digital MIC input Settings
(stereo) is executed. (Note 9)
[Digital MIC Setting] Window
Figure 70. [Rec_D-MIC ALC] Setting
3. [Playback_Lineout]
When [Playback_Lineout] button in the main window is clicked, the sequence for Stereo Line output Settings is
executed.
[DAC Setting] Window
Figure 71. [Playback_Lineout] Setting
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4. [Loopback_Lineout]
When [Loopback_Lineout] button in the main window is clicked, the sequence of Loopback settings is executed.
(Note 9)
[MIC-ADC Setting] Window
[DAC Setting] Window
Figure 72. [Loopback] Setting
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5. [Playback_SPK (Bass Boost ON)]
When [Playback_SPK (Bass Boost ON)] button in the main window is clicked, the sequence for Bass Boost settings
is executed.
[DAC Setting]
Window
[Bass Boost & 3 Band DRC Control] Window
Figure 73. [Playback_SPK (Bass Boost ON)] Setting
Note 9. The register setting of ALC by the sequence of [Rec_D-MIC ALC] or [Loopback_Lineout] is same as
[Rec_MIC+18dB_ALC].
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Measurement Results
[Measurement condition]
 Measurement Unit
 MCLK
 BICK
 fs
 Bit
 Power Supply
 Band Width
 Measurement Mode
 Temperature
: Audio Precession System Two Cascade, PSIA
: 12.2880MHz
: 64fs
: 48 kHz
: 24bit
: AVDD = 3.3V, DTVDD = 1.8V
: 20Hz ~ 20kHz
: PLL Slave Mode (MCKI = 12MHz)
: Room Temperature
[Measurement Result]
1. ADC
a). LIN1/RIN1 pins, MGAIN bits = “+18dB”
Parameter
Lch
S/(N+D)
(-1dBFS Input)
D-Range
(-60dB Input, A-weighted)
S/N
(No Signal, A-weighted)
Result
/
Rch
Unit
84.1
/
83.9
dB
88.5
/
88.5
dB
88.6
/
88.6
dB
b). LIN1/RIN1 pins, MGAIN bits = “0dB”
Parameter
Lch
S/(N+D)
(-1dBFS Input)
D-Range
(-60dB Input, A-weighted)
S/N
(No Signal, A-weighted)
Result
/
Rch
Unit
86.1
/
85.9
dB
95.0
/
95.2
dB
95.2
/
95.3
dB
2. DAC
a). LOUT/ROUT pins, LVCM bits = “01”, RL=20kΩ
Parameter
Lch
S/(N+D)
(-3dBFS Input)
S/N
(No Signal, A-weighted)
b). SPP/SPN pins, SPKG bits = “01”, RL=8Ω
Parameter
S/(N+D)
(-0.7dBFS Input)
S/N
(No Signal, A-weighted)
<KM112801>
Result
/
Rch
Unit
86.7
/
86.0
dB
93.8
/
93.9
dB
Result
Unit
77.6
dB
97.5
dB
2013/06
- 59 -
[AKD4958ECB-B]
PLOT DATA
1-a). ADC [LIN1/RIN1 pins, MGAIN = “+18dB”]
AKM
AK4958 S/(N+D) vs. Input Level [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
-70
-72
-74
-76
-78
-80
d
B
F
S
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 74. S/(N+D) vs. Input Level
AKM
AK4958 S/(N+D) vs. Input Frequency [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
-70
-72
-74
-76
-78
-80
d
B
F
S
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 75. S/(N+D) vs. Input Frequency
C1 and C2: Electrolytic Capacitor
<KM112801>
2013/06
- 60 -
[AKD4958ECB-B]
AKM
AK4958 Linearity [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
+0
TT T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 76. Linearity
AKM
AK4958 Frequency Response [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 77. Frequency Response
C1 and C2: Electrolytic Capacitor
<KM112801>
2013/06
- 61 -
[AKD4958ECB-B]
AKM
AK4958 Crosstalk [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
-70
TTTTTTTTTT
TTTTTT TTTTTT
TTTTTTTTT
TTTT TT
T TTTTT
TT T TT TTT TT
TTTTTTTTT
TT TT
TTTTT T TT
TT T
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 78. Crosstalk
AKM
AK4958 FFT (-1dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 79. FFT (-1dBFS Input)
<KM112801>
2013/06
- 62 -
[AKD4958ECB-B]
AKM
AK4958 FFT (-60dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 80. FFT (-60dBFS Input)
AKM
AK4958 FFT (No Signal Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+18dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 81. FFT (No Signal Input)
<KM112801>
2013/06
- 63 -
[AKD4958ECB-B]
1-b). ADC [LIN1/RIN1 pins, MGAIN = “0dB”]
AKM
AK4958 S/(N+D) vs. Input Level [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
-70
-72
-74
-76
-78
-80
d
B
F
S
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 82. S/(N+D) vs. Input Level
AKM
AK4958 S/(N+D) vs. Input Frequency [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
-70
-72
-74
-76
-78
-80
d
B
F
S
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 83. S/(N+D) vs. Input Frequency
C1 and C2: Electrolytic Capacitor
<KM112801>
2013/06
- 64 -
[AKD4958ECB-B]
AKM
AK4958 Linearity [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
+0
TT T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 84. Linearity
AKM
AK4958 Frequency Response [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 85. Frequency Response
C1 and C2: Electrolytic Capacitor
<KM112801>
2013/06
- 65 -
[AKD4958ECB-B]
AKM
AK4958 Crosstalk [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
-70
T TTTTTT
TTT
TTTTTTT
TTTTT
TTTTTT
TT
T
T
TT
T
T
TT
TT T
T
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 86. Crosstalk
AKM
AK4958 FFT (-1dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 87. FFT (-1dBFS Input)
<KM112801>
2013/06
- 66 -
[AKD4958ECB-B]
AKM
AK4958 FFT (-60dBFS Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 88. FFT (-60dBFS Input)
AKM
AK4958 FFT (No Signal Input) [ ADC, LIN1/RIN1 ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, MGAIN="+0dB"
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 89. FFT (No Signal Input)
<KM112801>
2013/06
- 67 -
[AKD4958ECB-B]
2-a). DAC [LOUT/ROUT pins, LVCM(1-0) bits = “01”]
AKM
AK4958 THD+N vs. Input Level [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
-70
-72
-74
-76
-78
-80
d
B
r
-82
A
-88
-84
-86
-90
-92
-94
-96
-98
-100
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 90. THD+N vs. Input Level
AKM
AK4958 THD+N vs. Input Frequency [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
-70
-72
-74
-76
-78
-80
d
B
r
-82
A
-88
-84
-86
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 91. THD+N vs. Input Frequency
C3and C4 Electrolytic Capacitor
<KM112801>
2013/06
- 68 -
[AKD4958ECB-B]
AKM
AK4958 Linearity [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
+0
-10
-20
-30
-40
d
B
r
-50
-60
A
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 92. Linearity
AKM
AK4958 Frequency Response [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
-2.5
-2.6
-2.7
-2.8
d
B
r
-2.9
A
-3.1
-3
-3.2
-3.3
-3.4
-3.5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 93. Frequency Response (Pin Direct)
C3and C4 Electrolytic Capacitor
<KM112801>
2013/06
- 69 -
[AKD4958ECB-B]
AKM
AK4958 Crosstalk [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
-70
TTTTTTTTTT
TT
TTTT TTTTT T
TTT
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 94. Crosstalk
C3and C4 Electrolytic Capacitor
AKM
AK4958 FFT (-3dBFS Input) [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 95. FFT (-3dBFS Input)
<KM112801>
2013/06
- 70 -
[AKD4958ECB-B]
AKM
AK4958 FFT (-60dBFS Input) [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 96. FFT (-60dBFS Input)
AKM
AK4958 FFT (No Signal Input) [ DAC, LINEOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, LVCMbit="01", RL=20kohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 97. FFT (No Signal Input)
<KM112801>
2013/06
- 71 -
[AKD4958ECB-B]
2-b). DAC [SPP/SPN pins, SPKG(1-0) bits = “01”]
AKM
AK4958 THD+N vs. Input Level [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
-70
-72
-74
-76
-78
-80
d
B
r
-82
A
-88
-84
-86
-90
-92
-94
-96
-98
-100
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 98. THD+N vs. Input Level
AKM
d
B
r
A
AK4958 THD+N vs. Input Frequency [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 99. THD+N vs. Input Frequency
<KM112801>
2013/06
- 72 -
[AKD4958ECB-B]
AKM
AK4958 Linearity [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
d
B
r
-50
-60
A
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 100. Linearity
AKM
AK4958 Frequency Response [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
+0
-0.1
-0.2
-0.3
d
B
r
-0.4
A
-0.6
-0.5
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 101. Frequency Response
<KM112801>
2013/06
- 73 -
[AKD4958ECB-B]
AKM
AK4958 FFT (-0.5dBFS Input) [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 102. FFT (-0.5dBFS Input)
AKM
AK4958 FFT (-60dBFS Input) [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 103. FFT (-60dBFS Input)
<KM112801>
2013/06
- 74 -
[AKD4958ECB-B]
AKM
AK4958 FFT (No Signal Input) [ DAC, SPKOUT ]
AVDD=3.3V, DTVDD=1.8V, fs=48kHz, PLL Slave Mode, SPKGbit="01", RL=8ohm
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 104. FFT (No Signal Input)
<KM112801>
2013/06
- 75 -
[AKD4958ECB-B]
3. VIDEO PLOT DATA
[Measurement condition]
 Measurement unit
 Power Supply
 Temperature
 Input Level
 VG bits
: Tektronix VM700T Video Measurement set
: AVDD = 3.3V, DTVDD = 1.8V
: Room Temperature
: 0.35Vpp Input (S/N), 0.5Vpp Input (DC and Vector)
: “10” (+12.0dB)
・S/N
 Input signal
: 0% Flat Field
 Measurement Frequency : 100kH  6MHz
Figure 105. Noise Spectrum
<KM112801>
2013/06
- 76 -
[AKD4958ECB-B]
・DC
 Input signal
: Field Square Wave
Figure 106. Field Time Distortion
<KM112801>
2013/06
- 77 -
[AKD4958ECB-B]
・Vector
 Input signal
: 75% Color Bar
Figure 107. Vector
<KM112801>
2013/06
- 78 -
[AKD4958ECB-B]
Revision History
Date
(YY/MM/DD)
13/06/19
Manual
Revision
KM112801
Board
Revision
1
Reason
Page
First edition
-
<KM112801>
Contents
2013/06
- 79 -
[AKD4958ECB-B]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information in
this document. You are fully responsible for use of such information contained in this document in your
product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY
YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR
PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above
use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM112801>
2013/06
- 80 -
A
B
C
D
E
1
1
+
1
C12
10u(T)
TP26
VSS3
JP26
SPP
C11
0.1u
D5
SPN
SPP
DTVDD
SPP
D4
VOUT
RIN
6
BEEP
E2
C6
2.2u
C3
R16
0
C1
1u
JP23
LIN
C2
1u
C3
1u
R5
220
C4
1u
R6
220
TP35
LOUT
TP36
AVDD
3
2
1
3
R8
20k
1
TP22
VOUT
VOUT
1
VOUT
CN3
TP25
VSS1
VIN
R14
75
C16
(open)
R15
75
1
C15
(open)
1
TP27
VSS4
C13
0.047u
J11
5
J10
VIN
5
4
3
2
2
3
4
5
VOUT
Title
Size
A3
- 81 C
TP31
ROUT
4
5
B
AGND
1
JP20
RIN
4
3
PDN
SCL
2
SDA
1
TP20
BEEP
JP21
MPW RR
JP22
MPW RL
PDN
R13
0
C14
1u
TP23
VIN
1
4
AVDD
R7
20k
MCKO
TP24
VSS2
LOUT
4
1
D3
C8
10u(T)
1
ROUT
C7
0.1u
1
E3
5
VIN
SDTO
LIN
C5
2.2u(T)
ROUT
MCKO
E4
1
REGFIL
SCL
A4
SDTO
R4
2.2k
R3
2.2k
A
7
1
9
1
TP34
MCKO
51
B3
AVDD
A1
8
1
TP33
SDTO
VIN
E1
R10
7
3
51
BICK
LOUT
R9
VCOM
D2
DGND
AK4958ECB
LRCK
MPWR
B2
DTVDD
VSS1
D1
A2
BICK
U100
SDTI
RIN1
6
A3
C2
5
E5
(open)
LRCK
LIN1
TP30
DTVDD
VOUT
C1
4
VIN
MCKI
SDA
TP38
BICK
B4
B1
3
1
TP37
LRCK
PDN
8
2
R11
0
MCKI
C5
B5
A5
SDTI
R12
1
1
2
1
TP29
MCKI
1
+
TP28
SDTI
CN1
SPN
+
2
1
VSS2
CN2
C4
JP25
SPN
PDN
Date:
D
AKD4958ECB-B
Document Number
AKD4958ECB-B-SUB
W ednesday, February 13, 2013
Sheet
1
E
Rev
1
of
1
A
B
C
8pin_L
1
JP2
C1
(open)
RIN1
JP1
AK4958-MCKI
2
AK4958-LRCK
(open)
C2
(open)
LIN1
B5
3
MCKI
LRCK
SVDD
E6
C3
(open)
AK4958-BICK
4
AK4958-DVDD
5
A5
B4
+
C5
(open)
BICK
VSS3
DVDD
LVDD
A4
U1 (open)
AK4955
VSS2
7
AK4958-SDTO
8
B3
R3
(open)
A3
TVDD
VCOM
F5
D5
F4
VSS1
+
E4
AK4958-RIN1
5
AK4958-LIN1
4
AK4958-ROUT
3
AK4958-LOUT
2
AK4958-AVDD
+
CN1
C8
(open)
C12
(open)
SDTO
REGFIL
2
C11
(open)
GND
TP1
F3
TP3
3
(open)
MIN
C3
1
MIN
1
JP4
MCKO
(open)
A2
(open)
MCKO
VSS1
F2
(open)
C13
PVEE
E2
(open)
C14
F1
VSS1
E1
VOUT
C2
VIN
D1
CSN/SDA
PDN
C1
4
B1
A1
1
(open)
I2C
AVDD
CCLK/SCL
GND
TP2
CDTIO/CAD0
D2
B2
+
R4
(open)
9pin_L
6
1
C10
(open)
9
AK4958-MCKO
AK4958-SPP
C4
(open)
C7
(open)
C9
(open)
AK4958-TVDD
+
C6
(open)
6
7
E5
SPP
SPN
F6
E3
D6
LIN1
D4
D3
LIN2
RIN2
C5
C6
RIN1
MPWR
A6
(open)
C4
B6
R44
(open)
LOUT
MCKI
SDTI
1
ROUT
AK4958-SDTI
AK4958-SPN
R1 (open)
(open)
JP3
8
R2 (open)
CN2
3
E
Unmount Area
1
2
D
4
C15
R5
(open)
4
3
2
1
(open)
CN3
4pin_1
PC-PDN
PC-CSN
PC-CCLK
5
PC-CDTIO
5
Title
Size
A3
- 82 A
B
C
Date:
D
AKD4958ECB-B
Document Number
Under
the Sub-Board
W ednesday, February 13, 2013
Sheet
E
Rev
1
1
of
5
A
B
C
D
E
1
1
TP14
HPR
+
1
HPR
C16
220u(A)
+
1
HPL
J1
6
TP4
HPL
4
3
C17
220u(A)
25
2
22
20
19
C21
0.1u
C24
0.22u
+
C22
2.2u(T)
AK4958-SPP
1
21
TP5
SPP
TP6
SPN
LS1
18
R8
(open)
17
AK4958-SPN
SPEAKER
AK4371
16
15
9
C27
47n
C20
0.1u
MUTET
MOUT
I2C
LOUT
VSS2
AK4371-AVDD
24
23
10u
C19
1
26
HPL
HPR
27
28
LIN2
RIN2
29
30
LIN3
RIN3
31
ROUT
VCOC
PDN
8
PVDD
CSN/CAD0
R7
6.8k
VREF
14
7
C26
0.1u
VCOM
AK4371
DVDD
13
C25
10u
MCLKI
VSS3
+
6
C23
0.1u
AVDD
U2
CCLK/SCL
5
HVDD
LRCK
CDTI/SDA
4
BICK
12
3
VSS1
11
AK4958-LRCK
RIN1
LIN1
R6
10
SDATA
MCKO
2
AK4958-BICK
2
1
10
AK4958-SDTO
AK4371-AVDD
C18
0.1u
+
32
HP
GND
TP8
TP7
ROUT
3
TP(Black)
+
PC2-CDTI
C28
1u
PC2-CCLK
AK4958-ROUT
C29
(short)
1
R9
0
1
3
6
PC2-CSN
PC2-PDN
AK4958-LOUT
4
1
+
LOUT
J2
4
3
TP9
RIN1
TP10
LIN1
TP11
C30
(short)
LINE
4
GND
TP12
1
1
1
TP(Black)
6
AK4958-RIN1
J3
4
3
AK4958-LIN1
MIC
5
5
Title
Size
A3
- 83 A
B
C
Date:
D
AKD4958ECB-B
Document Number
Analog
W ednesday, February 13, 2013
Rev
1
Sheet
E
2
of
5
A
B
E
R12 2.2
U3
1
2
3
4
C32
1u
5
6
Audio
7
8
9
C36 10u
10
+
11
12
2
13
C39 10u
14
D+
SSPNDN
D-
Vddi
VBUS
DGND
DGNDU
DOUT
HID0
DIN
U4
PCM2902
HID1
HID2
SSOP-28
Vccxi
AGNDX
SEL0
XTI
SEL1
XTO
Vccc
Vccp2
AGNDC
AGNDP
VINL
Vccp1
VINR
VOUTL
+
VCOM
VOUTR
28
1
C31 1u
27
GND
TP15
26
TP(Black)
25
USB-IN
24
C33 1u
23
22
21
20
R14
1M
19
C34
10p
C35
10p
X1
12MHz
C37 1u
18
USB-DVDD
C38 1u
17
10
9
8
7
6
22
16
H
2
S1
15
L
C40
1:
2:
3:
4:
5:
1
2
3
4
5
22
R13
1
R11
1
4
3
2
1
2
GND
D+
DVUSB
D
R10
1.5k
USB(B type)
1
C
10u
USB-DVDD
+
C41
0.1u
DIF2
DIF1
DIF0
OCKS1
PDN
10uH
R15 10k
USB-DVDD
DIF2
DIF1
DIF0
OCKS1
PDN
L1
C42
0.47u
USB-IN
R16 470
TP(Black)
OPT-IN
JMP3_1_1
DIF0
DIF1
DIF2
IPS0/RX4
NC
DIF0/RX5
TEST2
DIF1/RX6
VSS1
DIF2/RX7
IPS1/IIC
P/SN
XTL0
XTL1
VIN
USB-DVDD
IN
VCC
GND
RP1
47k(5P)
36
35
34
33
32
31
30
29
28
27
26
25
JP6
MCKO
AK4958-MCKO
XTI
C45 10p
JMP3_1_1
X2
12.288MHz
C46 10p
AK4118A
3
2
1
4
AK4958-SDTO
R17 51
AK4958-BICK
C48
10u
C49 0.1u
C50 0.1u
C51 10u
C52 10u
R45 0
R18 51
AK4958-SDTI
+
C47
0.1u
+
+
SPDIF-OUT
PORT2
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
AK4118A
XTI
XTO
DAUX
MCKO2
BICK
SDTO
13
14
15
16
17
18
19
20
21
22
23
24
L2
4
PDN
TVDD
NC
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
VSS2
MCKO1
LRCK
10uH
1
2
3
4
5
6
7
8
9
10
11
12
3
OCKS1
1
U5
1
USB-IN
5
4
3
2
1
GND
TP16
JP5
C44
10u
2
3
+
C43
0.1u
48
47
46
45
44
43
42
41
40
39
38
37
VCC
GND
OUT
3
2
1
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
SPDIF-IN
PORT1
R19 51
AK4958-LRCK
USB-DVDD
R46 0
R20 51
AK4958-MCKI
PORT3
1: MCKIO
3: BICK
5: LRCK
7: SDTI
9: VDD
10: SDTO
5
10
8
6
4
2
JP8
PORT3
9
7
5
3
1
MCKI
MCKO
5
R21
0
USB-DVDD
- 84 A
B
C
C53
0.1u
Title
Size
A3
Date:
D
AKD4958ECB-B
Document Number
DIN/DOUT
W ednesday, February 13, 2013
Rev
1
Sheet
E
3
of
5
A
B
C
D
4.7k
R22
USB-DVDD
C54
E
0.1u
1
1
L3
10uH
USB-DVDD
0.1u
+
10u
R26
R27
R28
R25
R29
38
39
40
41
2
3
4
5
51
51
51
51
51
51
32
35
36
U7
VUSB
DD+
GND
0.1u
6
VSS0
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
7
C60
0.1u
29
R24
VUSB
CTRL
C59
MCLR_N/Vpp/RE3
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
open
R30
PC2-PDN
FLASH-SO
PC2-CCLK
PC2-CDTI
PC2-CSN
FLASH-CSN
FLASH-TOGGLE
FLASH-LOAD
C65
3
C57
10u
VSS1
5V => 3.3V
NC
NC
Vin
Vout
Vcont PCL
NC
GND
C63
17
16
15
14
11
10
9
8
FSEL-5
FSEL-4
FSEL-3
FSEL-2
FSEL-1
FSEL-0
8
7
6
5
T1
2
TK73633AME
1
2
3
4
PIC
C56
10u
VDD0
SILK-SCREEN(P1)
1:VDD
JP11
2:MCLR
1
3:PGD
2
3
4:PGC
4
5:GND
5
28
0.1u
VDD1
C58
+
10u
+
+
C55
AK4371-AVDD
1
2
3
4
R34
R36
42
43
44
1
0
0
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
U6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VUSB
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
18
USB-RST
12
13
33
34
30
31
C61
R23
0.1u
100k
XTI
XTO
25
26
27
2
22p
C62
X3
20MHz
C64
22p
0.47u
37
C66
19
20
21
22
23
24
R31
R32
R33
51
51
51
PC-CSN
PC-CCLK
PC-CDTIO
R35
51
PC-PDN
3
R38
USB(B type)
10k
R37
10k
PIC18F4550
USB-DVDD
12
11
10
9
8
7
USB-DVDD
H
USB-DVDD
S2
SW DIP-6
R40
+
C67
10u
FLASH-TOGGLE
FSEL-0
FSEL-1
FSEL-2
FSEL-3
FSEL-4
FSEL-5
C68
0.1u
SW SPDT
1
2
3
4
D1
FLASH-SO
FLASH-CSN
S3
FLASH-LOAD
C69
0.1u
51
R41
1k
U8
S
Q
W
VSS
VCC
HOLD
C
D
8
7
6
5
GND
TP17
FSEL0
FSEL1
FSEL2
FSEL3
FSEL4
FSEL5
4
TP(Black)
6
5
4
3
2
1
R39
10k
1:
2:
3:
4:
5:
6:
1
2
3
4
5
6
L
SILK-SCREEN
BANK-SEL
1
USB-DVDD
4
PC2-CCLK
PC2-CDTI
M25P80
LED
RP2
47k(6P)
5
5
FLASH-ROM
Title
Size
A3
- 85 A
B
C
Date:
D
AKD4958ECB-B
Document Number
PIC
W ednesday, February 13, 2013
Rev
1
Sheet
E
4
of
5
A
B
C
D
E
1
1
TM1, TM2, TM3:
Not Mount, Land Only, Size = 5mm x 5mm
3.3V
TM1
1
i
AK4958-AVDD
JP9
JMP2_1
TJ-563
T2
2
VUSB
+
C70
47u(A)
C71
0.1u
8
7
6
5
NC
NC
Vin
Vout
Vcont PCL
NC
GND
1
2
3
4
R42
0
L4
+
C72
0.1u
TK73633AME
C73
10u
C74
0.1u
10uH
+
AK4958-TVDD
2
C75
10u
5V => 3.3V
1.8V
TM2
1
i
TJ-563
JP10
JMP2_1
T3
3
C76
0.1u
8
7
6
5
NC
NC
Vin
Vout
Vcont PCL
NC
GND
1
2
3
4
R43
0
+
C77
0.1u
TK73618AME
3
AK4958-DVDD
C78
10u
5V => 1.8V
GND
TP13
TM3
i
1
TP(Black)
1
GND
TJ-563
4
4
CL1, CL2:
Wire Short
CL1
1
CL2
2
W ire Short
1
2
W ire Short
5
5
Title
Size
A3
- 86 A
B
C
Date:
D
AKD4958ECB-B
Document Number
POWER
W ednesday, February 13, 2013
Rev
1
Sheet
E
5
of
5
- 87 -
- 88 -
- 89 -
- 90 -
- 91 -
- 92 -
- 93 -
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