AK4414 English Datasheet

[AK4414]
AK4414
High Performance 120dB 32-Bit 4ch DAC
GENERAL DESCRIPTION
AK4414 is a 32-bit DAC, which corresponds to BD systems. An internal circuit includes newly developed
32bit Digital Filter for better sound quality achieving low distortion characteristics and wide dynamic
range. The AK4414 has full differential SCF outputs, removing the need for AC coupling capacitors and
increasing performance for systems with excessive clock jitter. The AK4414 accepts 216kHz PCM data
and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD.
FEATURES
• 128x Over sampling
• Sampling Rate: 30kHz ∼ 216kHz
• 32Bit 8x Digital Filter
- Ripple: ±0.005dB, Attenuation: 80dB
- High Quality Sound Short Delay Option; GD=7/fs and GD=5.5/fs
- Sharp Roll-Off Filter
- Slow Roll-Off Filter
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD data input
• Digital De-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (255 levels and 0.5dB step)
• Stereo Mode
• THD+N: -107dB
• DR, S/N: 120dB (Stereo mode: 123dB)
• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD, TDM
• Master Clock:
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
• Power Supply: DVDD=AVDD=2.7 ∼ 3.6V, VDD1/2=4.75 ∼ 5.25V
• Digital Input Level: CMOS
• Package: 44pin LQFP
MS1476-E-01
2013/01
-1-
[AK4414]
■ Block Diagram
DVDD
DVSS
PDN
AVDD AVSS
Bias
BICK/DCLK
LRCK/DSDR2
SDTI1/DSDL1
8X
Interpolator
PCM
Data
Interface
SCF
AOUTLP1
AOUTLN1
SDTI2/DSDL2
ΔΣ
Modulator
DATT
Soft Mute
VCOM1
Vref
VREFH1
VREFL1
DSD
Data
Interface
SCF
AOUTRP1
AOUTRN1
TDM1/DSDR1
VDD1
VSS1
8X
Interpolator
SCF
AOUTLP2
AOUTLN2
VCOM2
ΔΣ
Modulator
DATT
Soft Mute
Vref
VREFH2
VREFL2
SCF
AOUTRP2
AOUTRN2
SLOW
VDD2
VSS2
TDM0
CSN/SMUTE
Control
Register
CCLK/DEM0
Clock
Divider
CDTI/DEM1
CAD0/SD
CAD1/DIF0
PSN
DZF1/DIF1
DIF
ACKS/DZF2
MCLK
Block Diagram
MS1476-E-01
2013/01
-2-
[AK4414]
■ Ordering Guide
−10 ∼ +70°C
44pin LQFP (0.8mm pitch)
Evaluation Board for AK4414
AK4414EQ
AKD4414
VSS1
VREFL1
VREFH1
AOUTR1N
AOUTR1P
NC
AOUTL2P
AOUTL2N
VREFH2
VREFL2
VSS2
33
32
31
30
29
28
27
26
25
24
23
■ Pin Layout
VDD1
34
22
VDD2
AOUTL1N
35
21
AOUTR2N
AOUTL1P
36
20
AOUTR2P
VCM1
37
19
VCM2
TSTO1
38
18
TEST
TSTO2
39
17
SLOW
AVDD
40
16
TDM0
15
ACKS/DZF2
AK4414
Top View
7
8
9
10
11
SD/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0/CAD1
DIF1/DZF1
SMUTE/CSN
12
6
44
LRCK/DSDR2
DVDD
5
DIF2
TDM1/DSDR1
13
4
43
SDATA2/DSDL2
DVSS
3
PSN
SDATA1/DSDL1
14
2
42
BICK/DCLK
MCLK
1
41
PDN
AVSS
MS1476-E-01
2013/01
-3-
[AK4414]
PIN/FUNCTION
No.
Pin Name
I/O
1
PDN
I
BICK
DCLK
SDATA1
DSDL1
SDATA2
DSDL2
TDM1
DSDR1
LRCK
DSDR2
I
2
3
4
5
6
I
I
I
I
I
I
I
SMUTE
I
I
13
CSN
SD
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
CAD1
DIF1
DZF1
DIF2
I
I
I
I
I
I
I
I
O
I
14
PSN
I
ACKS
I
16
17
DZF2
TDM0
SLOW
O
I
I
18
TEST
-
19
VCM2
-
20
21
22
23
24
25
26
27
AOUTR2P
AOUTR2N
VDD2
VSS2
VREFL2
VREFH2
AOUTL2N
AOUTL2P
O
O
I
I
O
O
28
NC
-
7
8
9
10
11
12
15
Function
Power-Down Mode
When at “L”, the AK4414 is in power-down mode and is held in reset.
The AK4414 should always be reset upon power-up.
Audio Serial Data Clock in PCM Mode
DSD Clock Pin in DSD mode
Audio Serial Data Input in PCM Mode
Audio Serial Data Input in DSD Mode
Audio Serial Data Input in PCM Mode
Audio Serial Data Input in DSD Mode
TDM I/F Format Mode in PCM Mode
Audio Serial Data Input in DSD Mode
L/R Clock in PCM Mode
Audio Serial Data Input in DSD Mode
Soft Mute in Parallel Control Mode
When this pin goes to “H”, soft mute cycle is initiated.
When returning to “L”, the output mute releases.
Chip Select in Serial Control Mode
Digital Filter setting pin in Parallel Control mode
Chip Address 0 in Serial Control Mode
(Internal pull-down pin)
De-emphasis Enable 0 in Parallel Control Mode
Control Data Clock in Serial Control Mode
De-emphasis Enable 1 in Parallel Control Mode
Control Data Input in Serial Control Mode
Digital Input Format 0 in PCM Mode
Chip Address 1 in Serial Control Mode
Digital Input Format 1 in PCM Mode
Zero Input Detect in Serial Control Mode
Digital Input Format 2 in PCM Mode
Parallel/Serial Select
(Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
Auto Clock Setting Mode in Parallel Control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Zero Input Detect in Serial Control Mode
TDM I/F Format Mode in Parallel Control mode
Digital filter setting pin
No internal bonding.
Connect to DVSS.
Common Voltage 2
Normally connected to VSS with a 10uF electrolytic cap.
Right Channel Positive Analog Output 2
Right Channel Negative Analog Output 2
Analog Power Supply, 4.75 to 5.25V
Ground (connected to DVSS, AVSS, VSS1 ground)
Low Level Voltage Reference Input 2
High Level Voltage Reference Input 2
Left Channel Negative Analog Output 2
Left Channel Positive Analog Output 2
No internal bonding.
Connect to GND.
MS1476-E-01
2013/01
-4-
[AK4414]
No.
29
30
31
32
33
34
35
36
Pin Name
AOUTR1P
AOUTR1N
VREFH1
VREFL1
VSS1
VDD1
AOUTL1N
AOUTL1P
I/O
O
O
I
I
O
O
Function
Right Channel Positive Analog Output 1
Right Channel Negative Analog Output 1
High Level Voltage Reference Input 1
Low Level Voltage Reference Input 1
Connected to DVSS, AVSS, VSS2 Ground
Analog Power Supply Pin, 4.75 ∼ 5.25V
Left Channel Negative Analog Output 1
Left Channel Positive Analog Output 1
Common Voltage 1
37 VCM1
Normally connected to VSS with a 10uF electrolytic cap.
Test Output pin. “Hi-Z” at Normal Operation.
38 TSTO1
I
Connect to AVSS.
Test Output pin. “Hi-Z” at Normal Operation.
39 TSTO2
I
Connect to AVSS.
40 AVDD
Analog Power Supply, 2.7 to 3.6V
41 AVSS
Analog Ground Pin
42 MCLK
I
Master Clock Input
43 DVSS
Digital Ground Pin
44 DVDD
Digital Power Supply, 3.0 ∼ 3.6V
Note: All input pins except internal pull-up/down pins should not be left floating.
MS1476-E-01
2013/01
-5-
[AK4414]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
(1) Parallel Mode (PCM Mode only)
Classification
Pin Name
Setting
These pins must be open.
These pins must be open.
These pins must be open.
These pins must be open.
Analog
AOUTL1P, AOUTL1N
AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N
AOUTR2P, AOUTR2N
Analog
TSTO1,TSTO2
This pin must be connected to AVSS
Digital
TEST
This pin must be connected to DVSS
(2) Serial Mode
1. PCM Mode
Classification
Pin Name
Analog
AOUTL1P, AOUTL1N
AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N
AOUTR2P, AOUTR2N
Setting
These pins must be open.
These pins must be open.
These pins must be open.
These pins must be open.
Analog
TSTO1,TSTO2
This pin must be connected to AVSS
Digital
DIF2,PSN,TDM0,SLOW,TEST This pin must be connected to DVSS
DZF1, DZF2
These pins must be open.
2. DSD Mode
Classification Pin name
Analog
AOUTL1P, AOUTL1N
AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N
AOUTR2P, AOUTR2N
Setting
These pins must be open.
These pins must be open.
These pins must be open.
These pins must be open.
Analog
TSTO1,TSTO2
This pin must be connected to AVSS
Digital
DIF2,PSN,TDM0,SLOW,TEST
DZF1, DZF2
This pin must be connected to DVSS
These pins must be open.
MS1476-E-01
2013/01
-6-
[AK4414]
ABSOLUTE MAXIMUM RATINGS
(VSS1-2=AVSS =DVSS =0V; Note 1)
Parameter
Symbol
Analog
Analog
Digital
|AVSS − DVSS|
AVDD
VDD1/2
DVDD
ΔGND
Power Supplies:
min
−0.3
−0.3
−0.3
−0.3
−10
−65
Input Current, Any Pin Except Supplies
IIN
Digital Input Voltage
VIND
Ambient Temperature (Power applied)
Ta
Storage Temperature
Tstg
Note 1. All voltages with respect to ground.
Note 2. AVSS, VSS1/2, DVSS must be connected to the same analog ground plane.
max
4.6
6.0
4.6
0.3
±10
DVDD+0.3
70
150
Unit
V
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-2=AVSS =DVSS =; Note 1)
Parameter
Symbol
min
typ
max
Unit
V
3.6
3.0
2.7
AVDD
Analog
Power Supplies
V
5.25
5.0
4.75
VDD1/2
Analog
(Note 3)
V
3.6
3.0
2.7
DVDD
Digital
V
VDD1
VDD1−0.5
VREFH1
“H” voltage reference
Voltage
V
VDD2
VDD2-0.5
VREFH2
“H” voltage reference
Reference
V
AVSS
VREFL1
“L” voltage reference
(Note 4)
V
AVSS
VREFL2
“L” voltage reference
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, VDD1/2 and DVDD is not critical.
Note 4. The analog output voltage scales with the voltage of (VREFH1/2 − VREFL1/2).
Connect a resistor of 20ohm or less and a capacitor of 100uF or more to the VREFH1/2 pin. (Figure 24)
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS1476-E-01
2013/01
-7-
[AK4414]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.0V, VDD1/2=5.0V; AVSS=VSS1/2=DVSS=0V; VREFH1/2=VDD1/2, VREFL1/2=
AVSS; Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 27; unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
Dynamic Characteristics
(Note 5)
0dBFS
-107
-98
dB
fs=44.1kHz
THD+N
BW=20kHz
−60dBFS
-57
dB
0dBFS
-104
dB
fs=96kHz
BW=40kHz
−60dBFS
-54
dB
0dBFS
-104
dB
fs=192kHz
BW=40kHz
−60dBFS
-54
dB
BW=80kHz
-51
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
113
120
dB
S/N (A-weighted)
(Note 7)
113
120
dB
Interchannel Isolation (1kHz)
100
110
dB
DC Accuracy
Interchannel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 8)
20
ppm/°C
Output Voltage
(Note 9)
±2.65
±2.8
±2.95
Vpp
Load Capacitance
10
pF
Load Resistance
(Note 10)
1
kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
VDD1+VDD2
41
60
mA
AVDD
1
1.5
mA
7
11
mA
DVDD (fs ≤ 44.1kHz)
12
18
mA
DVDD (fs=96kHz)
18
27
mA
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
(Note 11)
AVDD+VDD1/2+DVDD
10
100
μA
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. Figure 27 External LPF Circuit Example 2. 100dB for 16-bit data.
Note 7. Figure 27 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 8. The voltage on (VREFH1/2 − VREFL1/2) is held +5V externally.
Note 9. Full scale voltage (0dB). Output voltage scales with the voltage of (VREFH1/2 − VREFL1/2).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5.
Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 27). DC load is 1.5 kΩ (min)
without a DC cut capacitor (Figure 26). The load resistance value is with respect to ground. Analog
characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load
must be minimized.
Note 11. In the power down mode. The PSN pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held DVSS.
MS1476-E-01
2013/01
-8-
[AK4414]
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 12)
SB
24.1
kHz
Passband Ripple
PR
-0.0032
0.0032
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
29
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-0.2
0.2
dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 12)
SB
52.5
kHz
Passband Ripple
PR
-0.0032
0.0032
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
29
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-0.3
0.3
dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”.
SD bit=“0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 12)
SB
105
kHz
Passband Ripple
PR
-0.0032
0.0032
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
29
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-1
0.1
dB
Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs, SB=0.546×fs.
Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data
of both channels to input register to the output of analog signal.
MS1476-E-01
2013/01
-9-
[AK4414]
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”,
SD bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.04dB
PB
0
8.1
kHz
−3.0dB
18.2
kHz
Stopband
(Note 14)
SB
39.2
kHz
Passband Ripple
PR
-0.043
0.043
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
6
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
-5
0.1
dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode DEM=OFF; SLOW bit=“1”,
SD bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.04dB
PB
0
17.7
kHz
−3.0dB
39.6
kHz
Stopband
(Note 14)
SB
85.3
kHz
Passband Ripple
PR
-0.043
0.043
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
6
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
-4
0.1
dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”,
SD bit = “0”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 14) ±0.04dB
PB
0
35.5
kHz
−3.0dB
79.1
kHz
Stopband
(Note 14)
SB
171
kHz
Passband Ripple
PR
-0.043
0.043
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 13)
GD
6
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
-5
0.1
dB
Note 14. The passband and stopband frequencies scale with fs. For example, PB=0.185×fs, SB=0.888×fs.
MS1476-E-01
2013/01
- 10 -
[AK4414]
SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
20.0
kHz
−6.0dB
22.05
kHz
Stopband
(Note 12)
SB
24.1
kHz
Passband Ripple
PR
-0.0031
0.0031
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz
-0.2
0.2
dB
SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
43.5
kHz
−6.0dB
48.0
kHz
Stopband
(Note 12)
SB
52.5
kHz
Passband Ripple
PR
-0.0031
0.0031
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz
-0.3
0.3
dB
SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
87.0
kHz
−6.0dB
96.0
kHz
Stopband
(Note 12)
SB
105
kHz
Passband Ripple
PR
-0.0031
0.0031
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz
-1
0.1
dB
MS1476-E-01
2013/01
- 11 -
[AK4414]
SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “1”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
11.1
kHz
−6.0dB
22.3
kHz
Stopband
(Note 12)
SB
38.1
kHz
Passband Ripple
PR
-0.05
0.05
dB
Stopband Attenuation
SA
82
dB
Group Delay
(Note 13)
GD
5.5
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz
-5
0.1
dB
SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “1”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
24.2
kHz
−6.0dB
44.6
kHz
Stopband
(Note 12)
SB
83.0
kHz
Passband Ripple
PR
-0.05
0.05
dB
Stopband Attenuation
SA
82
dB
Group Delay
(Note 13)
GD
5.5
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz
-5
0.1
dB
SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”,
SD bit=“1”)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
48.4
kHz
−6.0dB
89.2
kHz
Stopband
(Note 12)
SB
165.9
kHz
Passband Ripple
PR
-0.05
0.05
dB
Stopband Attenuation
SA
82
dB
Group Delay
(Note 13)
GD
5.5
1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz
-5
0.1
dB
MS1476-E-01
2013/01
- 12 -
[AK4414]
DC CHARACTERISTICS
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
typ
max
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
30%DVDD
High-Level Output Voltage
(Iout=−100μA)
VOH
DVDD−0.5
Low-Level Output Voltage
(Iout=100μA)
VOL
0.5
Input Leakage Current
(Note 15)
Iin
±10
Note 15. The PSN pin has an internal pull-up device nominally 100kΩ. Therefore the PSN pin is not included.
MS1476-E-01
Unit
V
V
V
V
μA
2013/01
- 13 -
[AK4414]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Frequency (Note 16)
Normal Mode (TDM0= “L”, TDM1= “L”)
1152fs, 512fs or 768fs
8
fsn
256fs or 384fs
54
fsd
128fs or 192fs
108
fsq
Duty Cycle
45
Duty
TDM256 mode (TDM0= “H”, TDM1= “L”)
Normal Speed Mode High time
fsn
8
Low time
tLRH
1/256fs
tLRL
1/256fs
TDM128 mode (TDM0= “H”, TDM1= “H”)
Normal Speed Mode
fsn
8
Double Speed Mode
54
fsd
Quad Speed Mode
108
fsq
High time
1/128fs
tLRH
Low time
1/128fs
tLRL
PCM Audio Interface Timing
Normal Mode (TDM0= “L”, TDM1= “L”)
BICK Period
1/128fsn
tBCK
1152fs, 512fs or 768fs
1/64fsd
tBCK
256fs or 384fs
1/64fsq
tBCK
128fs or 192fs
14
tBCKL
BICK Pulse Width Low
14
tBCKH
BICK Pulse Width High
14
tBLR
BICK “↑” to LRCK Edge
(Note 17)
14
tLRB
LRCK Edge to BICK “↑”
(Note 17)
5
tSDH
SDATA Hold Time
5
tSDS
SDATA Setup Time
TDM256 mode (TDM0= “H”, TDM1= “L”)
BICK Period
Normal Speed Mode
tBCK
1/256fsn
BICK Pulse Width Low
tBCKL
14
BICK Pulse Width High
tBCKH
14
tBLR
BICK “↑” to LRCK Edge
(Note 17)
14
tLRB
14
LRCK Edge to BICK “↑”
(Note 17)
tSDH
5
SDATA1/2 Hold Time
tSDS
5
SDATA1/2 Setup Time
MS1476-E-01
typ
max
Unit
41.472
60
MHz
%
54
108
216
55
kHz
kHz
kHz
%
54
kHz
ns
ns
54
108
216
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2013/01
- 14 -
[AK4414]
TDM128 mode (TDM0= “H”, TDM1= “H”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
(Note 17)
LRCK Edge to BICK “↑”
(Note 17)
SDATA1/2 Hold Time
SDATA1/2 Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL1/R1/L2/R2 (Note 18)
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
tDCK
tDCKL
tDCKH
tDDD
160
160
−20
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/64fs
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width
(Note 19)
tPD
150
ns
Note 16. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4414 should be reset by the
PDN pin or RSTN bit.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. DSD data transmitting device must meet this time.
Note 19. The AK4414 can be reset by bringing the PDN pin “L” to “H” upon power-up.
MS1476-E-01
2013/01
- 15 -
[AK4414]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tLRH
tLRL
Duty=tLRH x fs, tLRL x fs
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA1/2
VIL
Audio Interface Timing (PCM Mode)
MS1476-E-01
2013/01
- 16 -
[AK4414]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
tDDD
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS1476-E-01
2013/01
- 17 -
[AK4414]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS1476-E-01
2013/01
- 18 -
[AK4414]
OPERATION OVERVIEW
■ D/A Conversion Mode
In serial mode, the AK4414 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4414
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4414 performs for
only PCM data.
DP bit
Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4414, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator.
The AK4414 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes AVDD/2 (typ). When MCLK and LRCK are input again, the AK4414 exit
reset state and starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the
AK4414 is in power-down mode until MCLK and LRCK are supplied.
(1) Parallel Mode (PSN pin = “H”)
1. Manual Setting Mode
In manual setting mode (ACKS pin = “L”) only Normal Speed mode is supported with the sample rate range shown in
Table 2. The AK4414 automatically configures itself to operate with the supported MCLK frequencies which are required
to be provided as input and are shown in Table 3.
Sampling Rate (fs)
Normal Speed Mode
8kHz ∼ 54kHz
Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
BICK
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
N/A
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
2.0480MHz
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
2.8224MHz
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
3.0720MHz
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode), (N/A: Not available)
MS1476-E-01
2013/01
- 19 -
[AK4414]
2. Auto Setting Mode (ACKS pin = “H”)
In this mode, sampling speed and MCLK frequency are detected automatically (Table 4). The MCLK must be supplied at
correct frequency according to the Table 5.
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
N/A
(8.1920*) (12.2880*)
16.3840
24.5760
36.8640
N/A
N/A
(11.2896*) (16.9344*)
22.5792
33.8688
N/A
N/A
N/A
(12.2880*) (18.4320*)
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
N/A
N/A
Table 5. System Clock Example (Auto Setting Mode @Parallel Mode), (N/A: Not available)
Sampling
Speed
Normal/
(Double*)
Double
Quad
MCLK= 256fs/384fs supports sampling rate of 32kHz~96kHz (Table 6). However, when the sampling rate is
32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
120dB
H
256fs/384fs
117dB
H
512fs/768fs
120dB
Table 6. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
3. Digital Filter Setting
SD pin
0
0
1
1
SLOW pin
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay sharp roll-off
1
Short delay slow roll-off
Table 7. Digital Filter Setting (Parallel Mode)
MS1476-E-01
2013/01
- 20 -
[AK4414]
(2) Serial Mode (PSN pin = “L”)
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling rate is set by DFS1-0 bits (Table 8). The MCLK frequency
corresponding to each sampling speed should be provided externally (Table 9). The AK4414 is set to Manual Setting
Mode at power-up (PDN pin = “L” →“H”). When DFS1-0 bits are changed, the AK4414 should be reset by RSTN bit.
DFS1 bit DFS0 bit
Sampling Rate (fs)
(default)
0
0
Normal Speed Mode
30kHz ∼ 54kHz
0
1
Double Speed Mode
54kHz ∼ 108kHz
1
0
Quad Speed Mode
120kHz ∼ 216kHz
Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
11.2896
12.2880
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
16.9344
22.5792
33.8688
N/A
N/A
N/A
18.4320
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 9. System Clock Example (Manual Setting Mode @Serial Mode)
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
11.2896MHz
12.2880MHz
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 10) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided externally (Table 11).
MCLK
1152fs
Sampling Speed
Normal (fs≤32kHz)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
(8.1920*) (12.2880*)
16.3840
24.5760
36.8640
N/A
(11.2896*) (16.9344*)
22.5792
33.8688
N/A
N/A
(12.2880*) (18.4320*)
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
Table 11. System Clock Example (Auto Setting Mode @Serial Mode)
MS1476-E-01
Sampling
Speed
Normal/
(Double*)
Double
Quad
2013/01
- 21 -
[AK4414]
MCLK= 256fs/384fs supports sampling rate of 32kHz~96kHz (Table 12). However, when the sampling rate is
32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
120dB
H
256fs/384fs
117dB
H
512fs/768fs
120dB
Table 12. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
3. Digital Filter Setting
SD bit
0
0
1
1
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay sharp roll-off (default)
1
Short delay slow roll-off
Table 13. Digital Filter Setting (Serial Mode)
[2] DSD Mode
The external clocks, which are required to operate the AK4414, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4414 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),
and the analog output becomes AVDD/2 voltage (typ).
DCKS bit
0
1
MCLK Frequency
DCLK Frequency
512fs
64fs
768fs
64fs
Table 14. System Clock (DSD Mode)
MS1476-E-01
(default)
2013/01
- 22 -
[AK4414]
■ Audio Interface Format
[1] PCM Mode
(1) Parallel Control Mode (PSN pin = “H”)
Twenty formats are selectable by DIF1-0 and TDM2-0 pins (Table 15). In this mode, register settings are ignored. In all
formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used
for 20 and 16 MSB justified formats by zeroing the unused LSBs.
If TDM1-0 pins = “LH” the audio interface is TDM256 mode (Table 15) and all eight channels of DAC data are input to
the SDTI1 pin. The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, “H” time and “L” time of LRCK should
be 1/256fs at least. The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK.
Only the first four channels of DAC data may be selected to be converted into four channels of DAC analog output.
If TDM1-0 pins = “HH” the audio interface is TDM128 mode (Table 15) and the serial data of DAC (four channels: L1,
R1, L2, R2) is input to the SDTI1 pin.
Mode
Normal
TDM256
TDM128
TDM1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
-
0
1
TDM0
DIF2 DIF1 DIF0 SDTI Format
0
0
0
16-bit LSB justified
0
0
1
20-bit LSB justified
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
0
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
0
0
0
N/A
0
0
1
N/A
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
1
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
0
0
0
N/A
0
0
1
N/A
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
1
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
Table 15. Audio Interface Format (Parallel mode)
MS1476-E-01
LRCK
H/L
H/L
H/L
L/H
H/L
H/L
H/L
L/H
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
≥64fs
≥64fs
≥64fs
↑
↓
↑
↑
↑
↓
256fs
256fs
256fs
256fs
256fs
256fs
↑
↓
↑
↑
↑
↓
128fs
128fs
128fs
128fs
128fs
128fs
2013/01
- 23 -
[AK4414]
(2) Serial Control Mode (PSN pin = “L”)
Twenty formats are selected by setting DIF2-0 and TDM1-0 bits (Table 16). The initial setting of DIF2-0 bits is “010”. In
this mode, the DIF1 pin setting is ignored.
The audio I/F format is TDM256 mode (Table 16) and all the serial data of eight DAC channels are input to the SDTI1 pin
(Figure 15). The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, high and low amplitude of LRCK is
1/256fs (min). The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK. The
eight channels of DAC data may be mapped to two pieces of AK4414 (Table 17).
In TDM128 mode, the serial data of DAC (four channels: L1, R1, L2, R2) is input to the SDTI1 pin and other serial data
of DAC (four channels: L3, R3, L4, R4) are input to the SDTI2 pin (Figure 14). BICK is fixed to 128fs. The data format is
MSB first and 2’s complement and the input data to SDTI1-2 pins are latched on the rising edge of BICK. The eight
channels of DAC data may be mapped to two pieces of AK4414 (Table 17).
Mode
Normal
TDM256
TDM128
TDM1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
-
0
1
TDM0
DIF2 DIF1 DIF0 SDTI Format
0
0
0
16-bit LSB justified
0
0
1
20-bit LSB justified
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
0
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
0
0
0
N/A
0
0
1
N/A
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
1
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
0
0
0
N/A
0
0
1
N/A
0
1
0
24-bit MSB justified
0
1
1
24-bit I2S compatible
1
1
0
0
24-bit LSB justified
1
0
1
32-bit LSB justified
1
1
0
32-bit MSB justified
1
1
1
32-bit I2S compatible
Table 16. Audio Interface Format (Serial mode)
MS1476-E-01
LRCK
H/L
H/L
H/L
L/H
H/L
H/L
H/L
L/H
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
≥64fs
≥64fs
≥64fs
↑
↓
↑
↑
↑
↓
256fs
256fs
256fs
256fs
256fs
256fs
↑
↓
↑
↑
↑
↓
128fs
128fs
128fs
128fs
128fs
128fs
2013/01
- 24 -
[AK4414]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA1/2
Mode 0
15
0
14
6
1
5
14
4
15
3
2
16
1
17
0
15
31
0
14
6
1
5
14
4
15
3
16
2
1
17
0
31
15
0
14
1
BICK
(64fs)
SDATA1/2
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
0
1
BICK
(64fs)
SDATA1/2
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA1/2
Mode 4
Don’t care
23
22 21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDATA1/2
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
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2013/01
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[AK4414]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDATA1/2
23
1
22
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA1/2
Mode 5,6
31
30
1
0
31
30
1
0
31
30
32:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 5/6 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
0
31
2
3
23
24
25
31
0
1
0
31
BICK
(64fs)
SDATA1/2
31 30
1
30
1
30
32:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 7 Timing
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[AK4414]
256 BICK
LRCK
BICK (256fs)
SDATA1
Mode8
SDATA1
Mode11,12
23 22
0
31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
23
23
Figure 7. Mode 8/11/12 Timing
256 BICK
LRCK
BICK (256fs)
SDATA1
Mode9
SDATA1
Mode13
23
0
23
31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
0 31 30
0
0 31 30
0
0 31 30
0
0 31 30
23
0 31
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 8. Mode 9/13 Timing
256 BICK
LRCK
BICK(256fs)
SDATA
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23
Figure 9. Mode 10 Timing
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[AK4414]
128 BICK
LRCK
BICK(128fs)
SDATA
Mode14
23 22
SDATA
Mode17,18
31 30
0
23 22
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 10. Mode 14/17/18 Timing
128 BICK
LRCK
BICK(128fs)
SDATA1
Mode15
23 22
SDATA1
Mode19
31 30
0
0
23 22
0
23 22
0 31 30
23 22
0 31 30
0
23
0 31 30
0 31 3
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 11. Mode 15/19 Timing
128 BICK
LRCK
BICK(128fs)
SDATA
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 12. Mode 16 Timing
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[AK4414]
One data cycle of SDATA1 and SDATA2 for each format are defined as below. SDS2-1 bits control playback channel of
each DAC.
LRCK
SDATA1
L1
R1
SDATA2
L2
R2
Figure 13. Data Slot in Normal Mode
128 BICK
LRCK
SDATA1
L1
R1
L2
R2
SDATA2
L3
R3
L4
R4
Figure 14. Data Slot in TDM128 Mode
256 BICK
LRCK
SDATA1
L1
R1
L2
R2
L3
R3
L4
R4
Figure 15. Data Slot in TDM256 Mode
AK4414 Data Select
Normal
TDM128
TDM256
SDS1
SDS2
0
DAC1
DAC2
Lch
Rch
Lch
Rch
0
L1
R1
L2
R2
0
1
L1
R1
L1
R1
1
0
L2
R2
L2
R2
1
1
L2
R2
L1
R1
0
0
L1
R1
L2
R2
0
1
L1
R1
L4
R4
1
0
L3
R3
L2
R2
1
1
L3
R3
L4
R4
0
0
L1
R1
L2
R2
0
1
L1
R1
L4
R4
1
0
L3
R3
L2
R2
1
1
L3
R3
L4
R4
Table 17. Data Select
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[AK4414]
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D3
D2
Figure 16. DSD Mode Timing
■ D/A Conversion Mode Switching Timing
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 17. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 18. D/A Mode Switching Timing (DSD to PCM)
Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty
range at the SACD format book (Scarlet Book).
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[AK4414]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or
disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is
always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are
switched.
[1] Parallel Mode
The DEM1 and DEM0 pins control de-emphasis mode of DAC1 and DAC2. This setting is common for both of DAC’s.
In parallel mode, the filter setting cannot be applied independently.
DEM1
DEM0
Mode
L
L
44.1kHz
L
H
OFF
(default)
H
L
48kHz
H
H
32kHz
Table 18. De-emphasis Control (Parallel Mode)
[2] Serial Mode
DEM1-0 bits and DEM3-2 bits control de-emphasis mode of DAC1 and DAC2, respectively. DEM3-0 bits settings are
invalid in DSD mode. The register settings are maintained when switching the mode between PCM and DSD modes.
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 19. DAC1 De-emphasis Control (Serial Mode)
DEM3
DEM2
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 20. DAC2 De-emphasis Control (Serial Mode)
■ Output Volume
The AK4414 includes channel independent digital output volumes (ATT) with 255 levels at 0.5dB step including MUTE.
This volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When
changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions. It
takes 7424/fs from FFH (0dB) to 00H (Mute). The attenuation level is reset to FFH (0dB) by initial reset. By RSTN bit =
“0”, the attenuation level is initialized to FFH, and the attenuation level returns to the setting value by RSTN bit = “1”.
Transition Time
0dB to MUTE
fs=44.1kHz
168.3ms
fs=96kHz
77.3ms
fs=192kHz
38.6ms
Table 21. ATT Transition Time
Sampling Speed
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- 31 -
[AK4414]
■ Zero Detection (PCM mode, DSD mode)
The AK4414 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L”
if the input data of each channel is not zero. If the RSTN bit is “0”, the DZF pins of both channels go to “H”. The DZF pins
of both channels go to “L” after 4 ~ 5/fs when RSTN bit returns to “1”. The DZFB bit can invert the polarity of the DZF
pin. In parallel control mode, the zero detect function is disabled.
Pin
DZF1
DZF2
Comment
Zero Detection flag output of the channels set by register 08H.
Zero Detection flag output of the channels set by register 09H.
Table 22. DZF pin function
■ Mono Output
Input and output signal combination of the AK4414 can be set by MONO bit and SELLR bit. Monaural output mode is
enabled when MONO bit = “1”. The output signal phase of DAC is controlled by INVL and INVLR bits. These settings
are available for any audio format.
(L1/2 is the output signal of the AOUTL1N/2N and AOUTL1P/2P pins. R1/2 is the output signal of AOUTR1N/2N and
AOUTR1P/2P pins)
MONO bit
SELLR1 bit
0
0
0
1
1
0
1
1
INVL1 bit
INVR1 bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
L1
R1
(AOUTL1N, AOUTL1P pins)
(AOUTR1N, AOUTR1P pins)
L1
L1 Invert
L1
L1 Invert
R1
R1 Invert
R1
R1 Invert
L1
L1 Invert
L1
L1 Invert
R1
R1 Invert
R1
R1 Invert
R1
R1
R1 Invert
R1 Invert
L1
L1
L1 Invert
L1 Invert
L1
L1
L1ch In Invert
L1 Invert
R1
R1
R1 Invert
R1 Invert
Table 23. Output Select for DAC1
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[AK4414]
MONO bit
SELLR2 bit
0
0
0
1
1
0
1
1
INVL2 bit
INVR2 bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
L2
R2
(AOUTL2N, AOUTL2P pins)
(AOUTR2N, AOUTR2P pins)
L2
L2 Invert
L2
L2 Invert
R2
R2 Invert
R2
R2 Invert
L2
L2 Invert
L2
L2 Invert
R2
R2 Invert
R2
R2 Invert
R2
R2
R2 Invert
R2 Invert
L2
L2
L2 Invert
L2 Invert
L2
L2
L2 Invert
L2 Invert
R2
R2
R2 Invert
R2 Invert
Table 24. Output Select for DAC2
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[AK4414]
■ Soft Mute Operation
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,
the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the
SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before
attenuating −∞, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
S M U T E pin or
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
D ZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in
Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel
goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.
Figure 19. Soft Mute Function
■ System Reset
The AK4414 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the
device. The AK4414 exits this system reset (power-down mode) by MCLK after the PDN pin = “H”, and the analog block
exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK for 4/fs.
MS1476-E-01
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[AK4414]
■ Power ON/OFF timing
The AK4414 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. The analog
outputs are floating (Hi-Z). Since a click noise occurs at the edge of the PDN pin signal, the analog output should be
muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs go to VCM1/2. Since a click noise occurs at the edge of RSTN signal, the analog output should be muted
externally if click noise aversely affect system performance.
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
(3)
Reset
(2)
(4)
GD
(4)
(3)
(5)
Clock In
MCLK,LRCK,BICK
Don’t care
Don’t care
(7)
DZFL/DZFR
External
Mute
(6)
Mute ON
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(7) DZF1/2 pins are “L” in the power-down mode (PDN pin = “L”).
Figure 20. Power-down/up Sequence Example
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[AK4414]
■ Reset Function
(1) RESET by RSTN bit = “0”
When the RSTN bit = “0”, the AK4414’s digital block is powered down, but the internal register values are not initialized.
In this time, the analog outputs go to VCM1/2 voltage and DZF1/2 pins are “H”. Figure 21 shows an example of reset by
RSTN bit.
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN bit
Internal
State
Normal Operation
P
D/A In
(Digital)
d
“0 ” data
(1)
D/A Out
(Analog)
Normal O peration
D igital Block
GD
GD
(3)
(2)
(3)
(1)
2/ fs(4)
DZF
(6)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes
“1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance
Figure 21. Reset Sequence Example 1
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[AK4414]
(2) RESET by MCLK or LRCK Stop
The AK4414 is automatically placed in reset state when MCLK or LRCK is stopped during PCM mode (RSTN pin
=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4414 exits reset state
and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4414 is in
reset state when MCLK is stopped.
AVDD pin
DVDD pin
RSTB pin
(1)
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal Operation
Normal Operation
(3)
GD
D/A Out
(Analog)
Digital Circuit Power-down
(2)
GD
(4)
Hi-Z
(5)
(2)
(4)
(4)
(5)
Clock In
MCLK, LRCK Stop
MCLK, LRCK
External
MUTE
(6)
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK and LRCK are input again can be reduced by inputting
“0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
noise occurs even when “0” data is input.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 22. Reset Sequence Example 2
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[AK4414]
■ Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4414. In parallel control
mode, the register setting is ignored, and in serial control mode the pin settings are ORed if the pin is not repurposed.
When the state of the PSN pin is changed, the AK4414 should be reset by the PDN pin. The serial control interface is
enabled by the PSN pin = “L”. In this mode, pin settings must be all “L”. Internal registers may be written to
through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits,
C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The
AK4414 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data
is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max).
Function
Parallel mode
Serial mode
Auto Setting Mode
Y
Y
Manual Setting Mode
Y
Y
Audio Format
Y
Y
De-emphasis
Y
Y
SMUTE
Y
Y
TDM Mode
Y (4-ch only)
Y
Digital Filter Option
Y
Y
DSD Mode
Y
Zero Detection
Y
Digital Attenuator
Y
Table 25. Function List1 (Y: Available, -: Not available)
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is
reset by the RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 23. Control I/F Timing
* The AK4414 does not support the read command.
* When the AK4414 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control
registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is
“L”.
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[AK4414]
Function List
Function
Attenuation Level
Audio Data Interface Modes
Data Zero Detect Enable
Minimum delay Filter Enable
Slow Rolloff Filter Enable
Short delay Filter Enable
De-emphasis Response
Default
0dB
24bit MSB Justified
Disable
Sharp roll-off filter
Address
03H
04H
06H
07H
00H
08H
09H
01H
02H
01H
0AH
01H
02H
OFF
Bit
PCM
DSD
ATT7-0
Y
Y
DIF2-0
Y
-
L1/R1/L2/R2
Y
Y
SD
SLOW
Y
Y
Y
-
DEM3-0
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Soft Mute Enable
Normal Operation
SMUTE
DSD/PCM Mode Select
PCM mode
D/P
Master Clock Frequency Select at
512fs
02H
DCKS
DSD mode
MONO mode Stereo mode select
Stereo
02H
MONO
Inverting Enable of DZF
“H” active
02H
DZFB
02H
The data selection of L channel and
SELLR1/2
R channel
05H
R channel
The data selection of DAC1 and
Normal
0AH
SDS1/2
DAC2
Data Invert Mode
OFF
05H
INVL1/L2/R1/R2
Table 26. Function List2 (Y: Available, -: Not available)
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[AK4414]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
Register Name
Control 1
Control 2
Control 3
L1ch ATT
R1ch ATT
Control 4
L2ch ATT
R2ch ATT
DZF1 Control
DZF2 Control
Control 5
D7
ACKS
0
DP
ATT7
ATT7
INVL1
ATT7
ATT7
L1
L1
TDM1
D6
0
0
0
ATT6
ATT6
INVR1
ATT6
ATT6
R1
R1
TDM0
D5
0
SD
DCKS
ATT5
ATT5
INVL2
ATT5
ATT5
L2
L2
SDS1
D4
0
DFS1
DCKB
ATT4
ATT4
INVR2
ATT4
ATT4
R2
R2
SDS2
D3
DIF2
DFS0
MONO
ATT3
ATT3
SELLR2
ATT3
ATT3
0
0
PW2
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
ATT2
ATT2
0
0
PW1
D1
DIF0
DEM0
SELLR1
ATT1
ATT1
0
ATT1
ATT1
0
0
DEM3
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
0
ATT0
ATT0
0
0
DEM2
Notes:
Data must not be written into addresses from 0BH to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4414 should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
ACKS
0
D6
0
0
D5
0
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
Internal clock timings are reset but registers are not reset.
DIF2-0: Audio Data Interface Modes (Table 16)
Initial value is “010” (Mode 2: 24-bit MSB justified).
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable : Manual Setting Mode (default)
1: Enable : Auto Setting Mode
When ACKS bit = “1”, the sampling frequency and MCLK frequency are detected automatically.
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[AK4414]
Addr Register Name
01H Control 2
Default
D7
0
0
D6
0
0
D5
SD
1
D4
DFS1
0
D3
DFS0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0: DAC1 De-emphasis Response (Table 19)
Initial value is “01” (OFF).
SD:
Short delay Filter Enable. This setting is ORed with the pin setting.
0: Sharp roll-off filter
1: Short delay filter (default)
SD
0
0
1
1
DFS1-0:
SLOW
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay sharp roll-off
1
Short delay slow roll-off
Table 27. Digital Filter setting
(default)
Sampling Speed Control (Table 8)
The default values are “00”. A click noise occurs when changing DFS1-0 bits.
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[AK4414]
Addr Register Name
02H Control 3
Default
SLOW:
D7
DP
0
D6
0
0
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR1
0
D0
SLOW
0
Slow Roll-off Filter Enable. This setting is ORed with the pin setting.
0: (default)
1: Slow roll-off filter
SD
0
0
1
1
SLOW
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay sharp roll-off
1
Short delay slow roll-off
Table 28. Digital Filter setting
(default)
SELLR1: The data selection of L channel and R channel, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
1: All channel output R channel data, when MONO mode.
It is enabled when MONO bit is “1”, and outputs Lch date to both channels when “0”,outputs Rch data to
both channels when “1”.
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4414 should be reset by RSTN bit.
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[AK4414]
Addr Register Name
03H L1ch ATT
04H R1ch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
255 levels, 0.5dB step
Data
FFH
FEH
FDH
:
:
02H
01H
00H
Attenuation
0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-∞)
The transition between set values is soft transition of 7425 levels. It takes 7424/fs ([email protected]=44.1kHz) from
FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH
when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is
independent of soft mute function.
Addr Register Name
05H Control 4
Default
D7
INVL1
0
D6
INVR1
0
D5
INVL2
0
D4
INVR2
0
D3
SELLR2
0
D2
0
0
D1
0
0
D0
0
0
SELLR2: The data selection of AOUTL2-R2, when MONO mode
0: AOUTL2-R2 output L channel data, when MONO mode. (default)
1: AOUTL2-R2 output R channel data, when MONO mode.
When MONO bit is set to “1”, Lch data is output by SELLR2 bit = “0” and Rch data is output by SELLR2
bit = “1”.
INVR2:
AOUTR2 output phase invert bit
0: Disable (default)
1: Enable
INVL2:
AOUTL2 output phase invert bit
0: Disable (default)
1: Enable
INVR1:
AOUTR1 output phase invert bit
0: Disable (default)
1: Enable
INVL1:
AOUTL1 output phase invert bit
0: Disable (default)
1: Enable
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[AK4414]
Addr Register Name
06H L2ch ATT
07H R2ch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
255 levels, 0.5dB step
Data
FFH
FEH
FDH
:
:
02H
01H
00H
Attenuation
0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-∞)
The transition between set values is soft transition of 7425 levels. It takes 7424/fs ([email protected]=44.1kHz) from
FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH
when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is
independent of soft mute function.
Addr Register Name
08H DZF1 Control
09H DZF2 Control
Default
D7
L1
L1
0
D6
R1
R1
0
D5
L2
L2
0
D4
R2
R2
0
D3
0
0
0
D2
0
0
0
D1
0
0
0
D0
0
0
0
D4
SDS2
0
D3
PW2
1
D2
PW1
1
D1
DEM3
0
D0
DEM2
1
L1-2, R1-2: Zero Detect Flag Enable Bit for the DZF1-2 pins
0: Disable
1: Enable
Addr Register Name
0AH Control 5
Default
D7
TDM1
0
D6
TDM0
0
D5
SDS1
0
DEM3-2: DAC2 De-emphasis Response (Table 20)
Initial value is “01” (OFF).
PW2-1: Power Down control for DAC
PW2: Power management for DAC2
0: DAC2 power OFF
1: DAC2 power ON (default)
PW1: Power management for DAC1
0: DAC1 power OFF
1: DAC1 power ON (default)
SDS1-2: DAC1and DAC2 data select
0: Normal Operation
1: Outputs other slot data
Refer to Table 17 for details.
TDM0-1: TDM Mode Select
Mode
Normal
TDM256
TDM128
TDM1
0
0
1
TDM0
0
1
1
BICK
32fs∼
256fs fixed
128fs fixed
MS1476-E-01
SDTI
1-2
1
1-2
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Normal, Double, Quad Speed
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[AK4414]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. Figure 26, Figure 27 and Figure 28 show the analog output circuit
examples. The evaluation board (AKD4414) demonstrates the optimum layout, power supply arrangements and
measurement results.
Digital 3.0V
Analog 3.0V
10u
VDD1 34
36
35
AOUTL1N
VCM1 37
AOUTL1P
0.1u
BICK
VREFL1
3
SDATA1
VREFH1 31
4
SDATA2
AK4414EQ
PDN
2
TDM1
32
NC
Micro-
8
SD
AOUTL2P 26
Controller
9
DEM0
VREFH2 25
AOUTL2N 27
R1ch
Mute
R1ch Out
L2ch
LPF
L2ch
Mute
L2ch Out
24
0.1u
R2ch
LPF
R2ch
Mute
R2ch Out
R=10
+
100u
VSS2 23
0.1u
22 VDD2
19 VCM2
18 TEST
17 SLOW
16 TDM0
11 DIF0
21 AOUTR2N
VREFL2
20 AOUTR2P
10 DEM1
15 ACKS
R1ch
LPF
100u
+
R=10
28
LRCK
SMUTE
14 P/S
0.1u
AOUTR1P 30
6
13 DFI2
L1ch Out
+
10u
AOUTR1N 29
7
12 DIF1
L1ch
Mute
VSS1 33
1
5
L1ch
LPF
0.1u
TSTO2 39
MCLK 42
DSP
DVSS 43
DVDD 44
0.1u
AVSS 41
0.1u
TSTO1 38
+
AVDD 40
10u
Analog 5.0V
10u
+
0.1u
Digital
Ground
Analog
Ground
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.
- VSS1-2, DVSS and AVSS must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 24. Typical Connection Diagram (AVDD=3.0V, VDD1/2=5V, DVDD=3.0V, Serial Control Mode)
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[AK4414]
36
35
34
AOUTL1N
VDD1
VCM1 37
AOUT L1P
TSTO1 38
TSTO2 39
AVSS 41
AVDD 40
DVSS 43
PDN
2
BICK
VREFL1
3
SDATA1
VREFH1 31
4
SDATA2
5
TDM1
6
LRCK
7
SMUTE
8
SD
AOUT L2N 26
9
DEM0
VREFH2 25
AK4414EQ
Controller
VSS1 33
1
AOUT R1N 30
AOUTR1P 29
NC
28
AOUTL2P 27
19 VCM2
18 TEST
17 SLOW
16 TDM0
15 ACKS
14 P/S
12 DIF1
21 AOUTR2N
VREFL2
20 AOUT R2P
10 DEM1
11 DIF0
13 DFI2
32
24
VSS2 23
22 VDD2
System
MCLK 42
Analog Ground
DVDD 44
Digital Ground
Figure 25. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDD1/2 and DVDD
respectively. AVDD and VDD1/2 are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDD1/2 and DVDD should be distributed separately from the point with low impedance of
regulator etc. The power up sequence between AVDD, VDD1/2 and DVDD is not critical. VSS1-2, DVSS and AVSS
must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed
as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFH1/2 and VREFL1/2 sets the analog output range. The VREFH1/2 pin is normally
connected to AVDD, and the VREFL1/2 pin is normally connected to VSS1/VSS2/AVSS. VREFH1/2 and VREFL1/2
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCM1/2 pin. All signals, especially clocks, should be kept away from the
VREFH1/2 and VREFL1/2 pins in order to avoid unwanted noise coupling into the AK4414.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH1/2 − VREFL1/2 = 5V) centered around AVDD/2.
The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If the
summing gain is 1, the output range is 5.6Vpp (typ, VREFH1/2 − VREFL1/2 = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
Figure 26 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 27 shows an example of differential outputs and LPF circuit example by three op-amps.
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[AK4414]
AK4414
2.4k
AOUT-
2.4k
150
680p
+Vop
3.3n
2.4k
AOUT+
2.4k
Analog
Out
150
680p
-Vop
Figure 26. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
Frequency Response
Gain
20kHz
−0.036dB
40kHz
−0.225dB
80kHz
−1.855dB
Table 29. Frequency Response of External LPF Circuit Example 1 for PCM
+15
3.3n
+
10k
330
180
0.1u
7
3
2 +
4
3.9n
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
3.9n
100
6
Lch
1.0n NJM5534D
10u
6
NJM5534D
1.2k
330
2 - 4
+
3
7
0.1u
7
3
+
2 4
+
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
560
100u
AOUTL- +
-15
10u
680
+
0.1u
10u
+
10u
0.1u
Figure 27. External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 30. Frequency Response of External LPF Circuit Example 2 for PCM
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[AK4414]
It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4414 can achieve this filter
response by combination of the internal filter (Table 31) and an external filter (Figure 28).
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 31. Internal Filter Response at DSD Mode
2.0k
AOUT-
1.8k
4.3k
1.0k
270p
2.4Vpp
2200p
+Vop
3300p
1.8k
2.0k
-
1.0k
AOUT+
+
4.3k
2.4Vpp
270p
Analog
Out
5.42Vp p
-Vop
Figure 28. External 3rd Order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 32. 3rd Order LPF (Figure 28) Response
4. Measurement Example
Figure 29 shows the relationship between THD+N and Frequency.
Measurement condition
Ta=25°C; AVDD=DVDD=3.3V, VDD1/2=5.0V; AVSS=VSS1/2=DVSS=0V; VREFH1/2=VDD1/2, VREFL1/2= AVSS;
Mono bit = “1”; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz
Measured by Audio Precision System Two.
C=470uF
C=2200uF
C=220uF
C=10uF
C=1000uF
Figure 29. THD+N vs. Frequency
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[AK4414]
PACKAGE
44pin LQFP (Unit: mm)
1.60max
12.0
1.40 ±0.05
0.10±0.05
10.0
23
33
1.00
0.80
12.0
22
10.0
34
12
44
1
11
0.37 +0.08
–0.07
0.20
M
0.145±0.055
0°∼7°
S
0.6±0.15
0.10
S
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
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[AK4414]
MARKING
AK4414EQ
XXXXXXX
AKM
1
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK4414
5) Audio 4 pro Logo
REVISION HISTORY
Date (Y/M/D)
12/11/16
13/01/15
Revision
00
01
Reason
First Edition
Error
Correction
Page
Contents
41
■ Register Definitions
DEM1-0: The table number was corrected.
A0H, Control 5
D3: The default value was changed. (0 → 1)
D0: The default value was changed. (0 → 1)
DEM3-2: Description was changed.
PW2-1: Description was added.
SYSTEM DESIGN
4. Measurement Example
Measurement Condition was changed.
44
48
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[AK4414]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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