Data Sheet

ASAHI KASEI
[AK5356]
AK5356
Low Power 20-Bit ADC with MIC-Amp & PGA
GENERAL DESCRIPTION
The AK5356 is a low voltage 20bit A/D converter for digital audio system. The AK5356 also includes
microphone amplifier and analog input PGA, making it suitable for microphone applications or low-input
signal levels. As digital power supply of the AK5356 corresponds to 1.8V, the interface with
microprocessor can operate at low voltage. The AK5356 is housed in a space-saving 28-pin QFN
package.
FEATURES
1. MIC Block
• MIC Power
• Pre-Amplifier (+13dB / +18dB / +28dB / +33dB)
2. 20bit 2ch ADC
• 2-Input Stereo Selector
• Analog Input PGA: +28dB ∼ - 52dB, Mute
• S/(N+D): 84dB
• DR, S/N: 89dB
• Monaural Mixing
• Digital HPF for DC-offset cancellation ([email protected]=44.1kHz)
3. 3-wire Serial Control I/F
4. Master Clock: 256fs/384fs
5. Audio Data Format: MSB First, 2’s compliment
• 16/20bit MSB justified or 16/20bit I2S compatible
6. Power Supply Voltage
• AVDD: 2.0 ∼ 3.3V
• MVDD: 2.4 ∼ 3.3V
• DVDD: 1.8 ∼ 3.3V
7. Power Supply Current
• MIC Block: 3.4mA
• IPGA+ADC: 6mA
8. Ta = - 40 ∼ 85°C
9. Package: 28pin QFN
MS0171-E-00
2002/08
-1-
ASAHI KASEI
[AK5356]
LIN
MICL
AVDD
AVSS
VCOM
PREL
Pre-Amp
MRF
MIC Power Supply
MCLK
MPWR
LRCK
MVDD
MVSS
Audio I/F
Controller
ADC
BCLK
MVCM
SDTO
PMMIC
DVDD
PRER
DVSS
PMADC
Control Register I/F
PDN
CSN
CCLK
CDTI
MICR
Power Management
RIN
Figure 1. AK5356 Block Diagram
MS0171-E-00
2002/08
-2-
ASAHI KASEI
[AK5356]
n Ordering Guide
AK5356VN
AKD5356
-40 ∼ +85°C
28pin QFN (0.5mm pitch)
Evaluation Board for AK5356
LIN
MPWR
MRF
MVCM
MVSS
MVDD
MICR
28
27
26
25
24
23
22
n Pin Layout
RIN
1
21
PREOR
VCOM
2
20
PRENR
AVDD
3
19
PRER
AVSS
4
18
PREL
DVSS
5
17
PRENL
DVDD
6
16
PREOL
SDTO
7
15
MICL
8
9
10
11
12
13
14
BCLK
MCLK
LRCK
CDTI
CCLK
CSN
PDN
Top View
MS0171-E-00
2002/08
-3-
ASAHI KASEI
[AK5356]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name
RIN
VCOM
AVDD
AVSS
DVSS
DVDD
SDTO
BCLK
MCLK
LRCK
CDTI
CCLK
CSN
I/O
I
O
O
I
I
I
I
I
I
14
PDN
I
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MICL
PREOL
PRENL
PREL
PRER
PRENR
PREOR
MICR
MVDD
MVSS
MVCM
MRF
MPWR
LIN
I
O
I
I
I
I
O
I
O
O
O
I
Function
Rch Line Input Pin
ADC Common Voltage Output Pin
Analog Power Supply Pin, +2.5V
Analog Ground Pin
Digital Ground Pin
Digital Power Supply Pin, +2.5V
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Master Clock Input Pin
Input/Output Channel Clock Pin
Control Data Input Pin
Control Clock Input Pin
Chip Select Pin
Reset & Power Down Pin
“L”: Reset & Power down, “H”: Normal operation
Lch MIC Input Pin
Lch Pre-Amp Output Pin
Lch Pre-Amp Negative Input Pin
Lch Pre-Amp Positive Input Pin
Rch Pre-Amp Positive Input Pin
Rch Pre-Amp Negative Input Pin
Rch Pre-Amp Output Pin
Rch MIC Input Pin
MIC Block Power Supply Pin, +2.7V
MIC Block Ground Pin
MIC Block Common Voltage Output Pin
MIC Power Supply Ripple Filter Pin
MIC Power Supply Pin
Lch Line Input Pin
Note: All digital input pins should not be left floating.
MS0171-E-00
2002/08
-4-
ASAHI KASEI
[AK5356]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, MVSS=0V; Note 1)
Parameter
Symbol
min
Power Supply
Analog
AVDD
-0.3
MIC
MVDD
-0.3
Digital
DVDD
-0.3
| DVSS – AVSS | (Note 2)
∆GND1
| MVSS – AVSS | (Note 2)
∆GND2
Input Current (Any Pin Except Supplies)
IIN
Analog Input Voltage (Note 3)
VINA1
-0.3
(Note 4)
VINA2
-0.3
Digital Input Voltage (Note 5)
VIND
-0.3
Ambient Temperature (power applied)
Ta
-40
Storage Temperature
Tstg
-65
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS and MVSS must be connected to the same analog ground plane.
Note 3. MICL, MICR, LIN and RIN pins
Note 4. PREL, PRER, PRENL and PRENR pins
Note 5. MCLK, BCLK, LRCK, CSN, CCLK, CDTI and PDN pins
max
4.6
4.6
4.6
0.3
0.3
±10
AVDD+0.3
MVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
V
V
mA
V
V
V
°C
°C
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, MVSS=0V; Note 1)
Parameter
Power Supply Analog
MIC
Digital
Note 1. All voltages with respect to ground
Symbol
AVDD
MVDD
DVDD
min
2.0
2.4
1.8
typ
2.5
2.7
2.5
max
3.3
3.3
AVDD
Units
V
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0171-E-00
2002/08
-5-
ASAHI KASEI
[AK5356]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.5V, MVDD=2.7V; AVSS, DVSS, MVSS=0V; fs=44.1kHz; Signal Frequency =1kHz;
Measurement Frequency=10Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Pre-Amp Characteristics:
Positive Input Pin (Note 6)
50
100
200
kΩ
Input Resistance
Negative Input Pin (Note 7)
100
190
400
Ω
Gain Error (+13dB, +18dB, +28dB, +33dB)
-1.5
0
+1.5
dB
Maximum Output Voltage(Gain=+13dB,+18dB,+28dB,+33dB)
-3
-1.5
dBV
(THD+N ≤ 0.1%) (Note 8)
Gain = +33dB
54
60
dB
S/(N+D) (Vout = -29.2dBV)
Gain = +28dB
65
dB
−
−
Gain = +18dB
74
dB
−
−
Gain = +13dB
78
dB
−
−
Gain
=
+33dB
-91
-86
dBV
Output Noise Voltage
Gain = +28dB
-96
dBV
−
−
(No Input, Rg = 600Ω, A-weighted)
Gain = +18dB
-105
dBV
−
−
Gain = +13dB
-109
dBV
−
−
Interchannel Gain Mismatch
0.5
dB
(Gain = +13dB, +18dB, +28dB, +33dB)
Gain = +33dB
75
90
dB
Interchannel Isolation
Gain = +28dB, +18dB, +13dB
100
dB
−
−
Load Resistance
5
kΩ
Load Capacitance
10
pF
Gain = +33dB
46
dB
−
−
Power Supply Rejection (Note 9)
Gain = +28dB
52
dB
−
−
Gain = +18dB
64
dB
−
−
Gain = +13dB
73
dB
−
−
MIC Power Characteristics:
Output Voltage (No Load) (Note 10)
2.05
2.16
2.27
V
Output Power Supply Current
1
mA
IPGA Characteristics:
Input Resistance (LIN, RIN, MICL, MICR pins)
6.3
9
15
kΩ
+28dB
-8dB
0.1
0.5
1
dB
∼
Step Size
-8dB ∼ -16dB
0.1
1
2
dB
-16dB ∼ -32dB
0.1
2
4
dB
-32dB ∼ -40dB
2
dB
-40dB ∼ -52dB
4
dB
ADC Characteristics: (Note 11)
Resolution
20
bits
Input Voltage (Note 12)
1.35
1.5
1.65
Vpp
IPGA = 0dB
74
84
dB
S/(N+D) (-0.5dBFS Input)
IPGA= +28dB
70
dB
−
−
IPGA = 0dB
82
89
dB
D-Range (-60dBFS Input, A-weighted)
IPGA= +28dB
79
dB
−
−
IPGA = 0dB
82
89
dB
S/N
(A-weighted)
IPGA= +28dB
79
dB
−
−
IPGA = 0dB
90
100
dB
Interchannel Isolation (Note 13)
IPGA= +28dB
75
dB
−
−
IPGA = 0dB
0.5
dB
Interchannel Gain Mismatch
IPGA= +28dB
0.5
dB
−
−
MS0171-E-00
2002/08
-6-
ASAHI KASEI
[AK5356]
Parameter
Power Supplies
min
Power Supply Voltage:
Normal Operation (PDN=“H”) (Note 14)
MVDD (Note 15)
AVDD+DVDD
Power-Down Mode (PDN=“L”) (Note 16)
MVDD + AVDD + DVDD
typ
max
Units
3.4
6
5
9
mA
mA
10
100
µA
Note 6. PREL and PRER pins
Note 7. PRENL and PRENR pins. Gain of Pre-Amp is +33dB. Input resistance of Pre-Amp is changed by gain.
Gain = +13dB: 1.9kΩ(typ), Gain = +18dB: 1.1kΩ(typ), Gain = +28dB: 340Ω(typ)
Note 8. A maximum output voltage is the value which fills “THD+N ≤ 0.1%”. It is almost in proportion to MVDD voltage.
-1.5dBV = 2.38Vpp = (MVDD x 0.88)Vpp (typ)
Note 9. PSR is applied to MVDD with 1kHz, 50mVpp.
Note 10. Output voltage is proportional to MVDD voltage and it is typically (MVDD x 0.8) V.
Note 11. ADC is input from MICL/MICR or LIN/RIN and it measures included in IPGA. Internal HPF cancels the offset
of IPGA and ADC.
Note 12. Analog input voltage (Full-scale voltage: IPGA = 0dB) is proportional to AVDD voltage.
IPGA = ADC = (0.6 x AVDD) Vpp (typ)
Note 13. This value is interchannel isolation between LIN and RIN or between MICL and MICR.
Note 14. All blocks in the AK5356 are powered-up. (PMMIC=PMADC= “1”)
Note 15. MPWR pin supplies 0mA.
Note 16. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held at
DVDD or DVSS. PDN pin is held at DVSS.
MS0171-E-00
2002/08
-7-
ASAHI KASEI
[AK5356]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD=2.0 ∼ 3.3V, DVDD=1.8 ∼ 3.3V, MVDD=2.4∼ 3.3V, fs=44.1kHz)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (LPF):
Passband
(Note 17) ±0.1dB
PB
0
17.4
kHz
-1.0dB
20.0
kHz
-3.0dB
21.1
kHz
Stopband
(Note 17)
SB
27.0
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
65
dB
Group Delay
(Note 18)
GD
17.0
1/fs
Group Delay Distortion
0
∆GD
µs
ADC Digital Filter (HPF):
Frequency Response (Note 17) -3dB
FR
3.4
Hz
-0.5dB
10
Hz
-0.1dB
22
Hz
Note 17. The passband and stopband frequencies scale with fs (sampling frequency).
For example, PB=0.454 x fs (@ -1.0dB).
Note 18. The calculated delay time caused by digital filtering. This time from the input of an analog signal to setting the
20bit data of both channels to the output register of the ADC and includes the group delay of the HPF.
DC CHARACTERISTICS
(Ta=25°C; AVDD=2.0 ∼ 3.3V, DVDD=1.8 ∼ 3.3V, MVDD=2.4∼ 3.3V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
75%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage Iout = -80µA
VOH
DVDD-0.4
Low-Level Output Voltage Iout = 80µA
VOL
Input Leakage Current
Iin
-
MS0171-E-00
typ
-
max
25%DVDD
0.4
±10
Units
V
V
V
V
µA
2002/08
-8-
ASAHI KASEI
[AK5356]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=2.0 ∼ 3.3V, DVDD=1.8 ∼ 3.3V; CL=20pF)
Parameter
Symbol
Master Clock Timing (MCLK)
256fs: Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
384fs: Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Timing
Frequency
fs
Duty Cycle
Duty
Serial Interface Timing
BCLK Period
tBLK
BCLK Pulse Width Low
tBLKL
Pulse Width High
tBLKH
BCLK “↓” to LRCK edge
tBLR
LRCK to SDTO (MSB) (Note 19)
tDLR
BCLK “↓” to SDTO
tDSS
Control Interface Timing
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDTI Setup Time
tCDS
CDTI Hold Time
tCDH
CSN “H” Time
tCSW
CSN “↓” to CCLK “↑”
tCSS
CCLK “↑” to CSN “↑”
tCSH
Power-down & Reset Timing
PDN Pulse Width
tPW
PDN“↑” to SDTO Delay (Note 20)
tPWV
min
typ
max
Units
2.048
28
28
3.072
23
23
11.2896
12.8
16.9344
19.2
MHz
ns
ns
MHz
ns
ns
44.1
50
55
kHz
%
tBLKL-50
80
80
ns
ns
ns
ns
ns
ns
8
45
312.5
130
130
-tBLKH+50
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
150
4128
ns
1/fs
Note 19. Except for I2S mode.
Note 20. This is the number of LRCK rising after PDN pin is pulled high.
MS0171-E-00
2002/08
-9-
ASAHI KASEI
[AK5356]
n Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
tBLK
VIH
VIL
BCLK
tBLKH
tBLKL
Figure 2. Clock Timing
VIH
VIL
LRCK
tBLR
VIH
VIL
BCLK
tDLR
tDSS
SDTO
D19 (MSB)
50%DVDD
Figure 3. Audio Data Output Timing (Audio I/F = No.0)
VIH
VIL
CSN
tCCKL tCCKH
tCSS
VIH
VIL
CCLK
tCDS
CDTI
op2
tCDH
op1
op0
A4
VIH
VIL
Figure 4. WRITE Command Input Timing
MS0171-E-00
2002/08
- 10 -
ASAHI KASEI
[AK5356]
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
D3
D2
VIH
VIL
D0
D1
Figure 5. WRITE Data Input Timing
tPW
PDN
VIL
tPWV
SDTO
50%DVDD
Figure 6. Power Down & Reset Timing
MS0171-E-00
2002/08
- 11 -
ASAHI KASEI
[AK5356]
OPERATION OVERVIEW
n System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs, 40fs∼). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The Frequency of MCLK can be
input at 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling
frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5356 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5356 should be placed in
power-down mode.
n Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s compliment. The data format is set using the DIF bit. SDTO is latched by a falling edge of BCLK.
No.
DIF bit
0
0
1
1
SDTO (ADC)
LRCK
16bit MSB justified Lch: “H”, Rch: “L”
20bit MSB justified Lch: “H”, Rch: “L”
16bit I2S compatible Lch: “L”, Rch: “H”
20bit I2S compatible Lch: “L”, Rch: “H”
Table 1. Audio Data Format
BCLK
= 32fs
≥ 40fs
= 32fs
≥ 40fs
Default
LRCK
0
1
2
12
13
14
19
20
21
31
0
1
2
12
13
14
19
20
21
31
0
1
BCLK(I:64fs)
SDTO(o)
19 18
0
1
8
2
7
3
6
9
0
10
11
19 18
12
13
15
14
0
1
8
2
7
6
9
3 3
0
10
11
19
12
13
14
15
0
1
BCLK(i:32fs)
SDTO (o)
19 18 17
11
10
9
8
7
6
5
4
19 18 17
11
10
9
8
7
6
5
4
19
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Audio Data Timing (No.0)
MS0171-E-00
2002/08
- 12 -
ASAHI KASEI
[AK5356]
LRCK(i)
0
1
2
3
17
18
19
20
21
31
0
1
2
3
17
18
19
20
21
31
0
15
0
1
BCLK(i:64fs)
SDTO(o)
19 18
0
1
2
4
3
3
9
8
2
10
1
11
0
12
19 18
14
13
15
0
1
2
4
3
8
3
9
2
10
1
11
0
12
14
13
1
BCLK(i:32fs)
SDTO (o)
4
19 18
12
11 10
9
8
7
6
5
4
19 18
Lch Data
12
11 10
9
8
7
6
5
4
Rch Data
19:MSB, 0:LSB
Figure 8. Audio Data Timing (No.1)
n Digital High Pass Filter
The AK5356 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the IPGA and ADC. The cut-off frequency
of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs). And the HPF can select
ON/OFF by HPF bit.
MS0171-E-00
2002/08
- 13 -
ASAHI KASEI
[AK5356]
n MIC Block
1. Pre-Amp
The Pre-Amp is non-inverting amplifier and internally biased to MVCM voltage with 100kΩ (typ.). Gain of the
Pre-Amp can select +13dB, +18dB, +28dB or +33dB by PREG1-0 bits.
Pre-Amp gain value of L/R channels change by zero crossing detection or timeout independently. Timeout cycle is fixed
to 2048/fs (=46.8ms @ fs = 44.1kHz). Zero crossing detection is done by IPGA block. When PMADC bit is “0”, gain of
Pre-Amp changes immediately.
An external capacitor is needed to cancel DC gain. The cut-off frequency is determined by an internal resistor (Ri) and
an external capacitor (C1).
C1
+
To MICL/MICR pins
Rf
Ri
PREL pin
PRER pin
+
Pre-Amp
Figure 9. Pre-Amp
2. Power Supply for MIC
The power supply for microphone device is supplied from MPWR pin. The output voltage is typically 2.16V(= 0.8 x
MVDD at MVDD=2.7V). MPWR pin can supply the current up to 1mA. When PMMIC bit is “0”, the output current is
not supplied.
MS0171-E-00
2002/08
- 14 -
ASAHI KASEI
[AK5356]
n System Reset
The AK5356 is placed in the power-down mode by bringing PDN pin “L”. The control registers are also reset at the same
time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down
mode. The output data SDTO becomes available after 4128 cycles of LRCK clocks. During initialization, the ADC digital
data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the
input signal at the end of initialization (Settling time equals the group delay time approximately.).
As a normal initialization cycle may not be executed, nothing writes at address 01H during
initialization cycle after exiting power-down by PDN pin.
Power Supply
PDN pin
PDN pin may be “L” at power-up.
ADC Internal
State
PD
4128/fs
4128/fs
Normal
INIT -1
GD
PM
INIT -1
Normal
GD (1)
GD
AIN
SDTO
Control register
W rite to register
External clocks
(2)
(3) “0”data
Idle Noise
“0”data
INIT -2
(1)
Normal
Inhibit
Normal
(4)
The clocks m ay be stopped.
(5)
Figure 10. Power-Up / Power-Down Timing Example
• PD:
• PM:
• INIT-1:
• INIT-2:
• Inhibit:
Power-down state. ADC is output “0”.
Power-down state by Power Management bit. ADC is output “0”.
Initialization cycle of ADC
Initializing all control registers.
Inhibits writing to all control registers.
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to the analog input is delayed by the Group Delay amount (GD). Output signal
gradually comes to settle to input signal during a group delay.
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of
a internal.
(3). ADC output data is “0” at power-down.
(4). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5356 should be placed in the
power-down state.
(5). When external clocks are not supplied, inhibits writing to all control registes.
MS0171-E-00
2002/08
- 15 -
ASAHI KASEI
[AK5356]
n Timing of Control Register
The internal registers are written by the 3-wire µP interface pins: CSN, CCLK, CDTI. These data are included by Chip
Address (2bit, The AK5356 is fixed to “10”.), Read/Write (1bit), Address (MSB-first, 5bit) and Control data (MSB-first,
8bit). A side of transmitted data is output to each bit by “↓” of CCLK, a side of receiving data is input by “↑” of CCLK.
Writing of data becomes effective by “↑” of CSN. The clock speed of CCLK is 5MHz (max). The value of internal
registers is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
Read/Write (Fixed to “1”; Write only)
Register Address
Control Data
Figure 11. Control Data Timing
MS0171-E-00
2002/08
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ASAHI KASEI
[AK5356]
n Register Map
Addr
00H
01H
02H
03H
Register Name
Input Select
Power Management Control
Mode Control
IPGA Control
D7
0
0
MONO1
ZEIP
D6
PREG1
0
MONO0
IPGA6
D5
PREG0
0
ZTM1
IPGA5
D4
HPF
0
ZTM0
IPGA4
D3
RIN
0
0
IPGA3
D2
MICR
0
0
IPGA2
D1
LIN
PMADC
DIF
IPGA1
D0
MICL
PMMIC
0
IPGA0
D2
MICR
1
D1
LIN
0
D0
MICL
1
All registers are reset at PDN = “L”, then inhibits writing to all registers.
For address from 04H to 1FH, data must not be written.
Unused bits must contain a “0” value.
n Register Definition
Input Select
Addr
00H
Register Name
Input Select
Default
D7
0
0
D6
PREG1
1
D5
PREG0
0
D4
HPF
0
D3
RIN
0
PREG1-0: Select gain of Pre-Amp
00: +13dB
01: +18dB
10: +28dB (Default)
11: +33dB
Pre-Amp gain value of L/R channels change by zero crossing detection or timeout independently. Timeout
cycle is fixed to 2048/fs (=46.8ms @ fs = 44.1kHz). Zero crossing detection is done by IPGA block. When
PMADC bit is “0”, gain of Pre-Amp changes immediately.
HPF:
Select ON/OFF of the digital HPF (0: ON, 1: OFF)
RIN:
Select ON/OFF of Rch LINE input
Select ON/OFF of Rch MIC input
Select ON/OFF of Lch LINE input
Select ON/OFF of Lch MIC input
MICR:
LIN:
MICL:
(0: OFF, 1: ON)
(0: OFF, 1: ON)
(0: OFF, 1: ON)
(0: OFF, 1: ON)
Power Management Control
Addr
01H
Register Name
Power Management Control
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
PMADC
1
D0
PMMIC
1
PMADC: Power Management of IPGA and ADC
0: Power OFF
1: Power ON (Default)
PMMIC: Power Management of MIC Block (Pre-Amp, MIC Power and MVCM)
0: Power OFF
1: Power ON (Default)
When PDN pin goes “L”, all circuit in the AK5356 can be powered-down in no relation to PMADC and PMMIC bits.
When PMADC and PMMIC bits go “0”, all circuit in the AK5356 can be also powered-down. However, the contents
of control registers are held.
Except the case of PMADC=PMMIC= “0” or PDN pin = “L”, MCLK, BCLK and LRCK should not be stopped.
MS0171-E-00
2002/08
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ASAHI KASEI
[AK5356]
Mode Control
Addr
02H
Register Name
Mode Control
Default
D7
MONO1
0
D6
MONO0
0
D5
ZTM1
1
D4
ZTM0
1
D3
0
0
D2
0
0
D1
DIF
0
D0
0
0
MONO1-0: Monaural Mixing
00: Stereo (Default)
01: (L+R)/2
10: LL
11: RR
SW1
Selector
Lch
ADC
HPF
Lch
+
SW2
x 0.5
Selector
Rch
ADC
HPF
Rch
Figure 12. Monaural mixing block
Mode
Stereo Recording
Monaural Recording
Stereo Input
Monaural Recording
Lch Input
Monaural Recording
Rch Input
SW1
Lch
SW2
Rch
MONO1
0
MONO0
0
(L+R)/2
(L+R)/2
0
1
Lch
Lch
1
0
Rch
Rch
1
1
Table 2. Monaural Mode Setting
ZTM1-0:
Setting of Zero Crossing Timeout for IPGA
00: 256/fs
01: 512/fs
10: 1024/fs
11: 2048/fs (Default)
DIF: Select Digital Interface Format
No.
DIF bit
0
0
1
1
SDTO (ADC)
LRCK
16bit MSB justified
Lch: “H”, Rch: “L”
20bit MSB justified
Lch: “H”, Rch: “L”
16bit I2S Compatible
Lch: “L”, Rch: “H”
20bit I2S Compatible
Lch: “L”, Rch: “H”
Table 3. Audio Data Format
MS0171-E-00
BCLK
= 32fs
≥ 40fs
= 32fs
≥ 40fs
Default
2002/08
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ASAHI KASEI
[AK5356]
Input Analog PGA Control
Addr
03H
Register Name
Input Analog PGA Control
Default
ZEIP:
D7
ZEIP
0
D6
IPGA6
D5
IPGA5
D4
IPGA4
D3
IPGA3
28H
D2
IPGA2
D1
IPGA1
D0
IPGA0
Select IPGA zero crossing operation
0: Disable (Default)
1: Enable
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing detection
or timeout independently.
In the timeout cycle, it is possible to set in ZTM1-0 bit. When ZTM1-0 is “11”, timeout cycle is
2048/fs = 46.4ms (@fs=44.kHz). When ZEIP is “0”, IPGA changes immediately.
IPGA6-0: Input Analog PGA, 97 levels; 00H=MUTE
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
DATA
GAIN(dB)
Step
Level
60H
5FH
5EH
•
28H
27H
•
19H
18H
+28.0
+27.5
+27.0
•
+0.0
-0.5
•
-7.5
-8.0
0.5dB
73
17H
16H
•
11H
10H
-9.0
-10.0
•
-15.0
-16.0
1dB
8
0FH
0EH
•
05H
04H
-18.0
-20.0
•
-38.0
-40.0
2dB
12
03H
02H
01H
00H
-44.0
4dB
-48.0
-52.0
MUTE
Table 4. Input Gain Setting
3
1
[ Writing to IPGA register at ZEIP = “1” continuously ]
When writing control register continuously, the change of IPGA should be written after zero crossing timeout. If
IPGA is changed by writing to control register before zero crossing detection, IPGA value of L/R channels may not
give a difference level.
MS0171-E-00
2002/08
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ASAHI KASEI
[AK5356]
SYSTEM DESIGN
Figure 13 shows the system connection diagram. An evaluation board [AK5356] is available which demonstrates the
application circuit, optimum layout, power supply arrangement and measurement results.
2.4∼3.3V Analog Power Supply
C1: 0.1µ
C2: 10µ
6.8k
6.8k
C2
+
+ C2
47µ +
1.8∼3.3V Digital Power Supply
+
4.7µ
MICR 22
MVSS 24
MVDD 23
MVCM 25
C1
1 RIN
PREOR 21
2 VCOM
PRENR 20
3 AVDD
PRER 19
C1
4 AVSS
C2
C1
MRF 26
LIN 28
2.2µ C1
+
C2
2.0∼3.3V Analog Power Supply
+
MPWR 27
1µ +
PREL 18
Top View
C1
5 DVSS
PRENL 17
6 DVDD
PREOL 16
7 SDTO
MICL 15
+47µ
0.33µ
0.33µ
MIC
Device
+47µ
Audio
Micro
Controller
Controller
14 PDN
13 CSN
12 CCLK
11 CDTI
10 LRCK
8 BCLK
9 MCLK
4.7µ
Figure 13. System Connection Diagram Example
NOTE: Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
MS0171-E-00
2002/08
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ASAHI KASEI
[AK5356]
PACKAGE
5.2 ± 0.20
5.0 ± 0.10
28
22
22
15
10
14
8
- 0.00
0.80 + 0.20
- 0.28
0.78 + 0.17
0.05 M
0.02 + 0.03
0.05
0.
7
14
0.50
±
45
15
0.21 ± 0.05
0.22 ± 0.05
25
- 0.02
8
28
1
45
7
0.
21
21
5.2 ± 0.20
5.0 ± 0.10
1
0.60 ± 0.10
2
-C
0.
6
0.
4
+
0
- 0 .10
.2
0
28pin QFN (Unit: mm)
Note) The part of black at four corners on reverse side must not be soldered and must be open.
n Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate (Pb free)
MS0171-E-00
2002/08
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ASAHI KASEI
[AK5356]
MARKING
5356
XXXX
1
XXXX : Date code identifier (4 digits)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0171-E-00
2002/08
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