AKM AKD4393

ASAHI KASEI
[AK4393]
AK4393
Advanced Multi-Bit 96kHz 24-Bit ∆Σ DAC
GENERAL DESCRIPTION
The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a
24bit digital filter. The AK4393 introduces the advanced multi-bit system for ∆Σ modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. In the AK4393, the analog outputs are filtered in the analog
domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs are full
differential output, so the device is suitable for hi-end applications. The operating voltages support analog
5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC.
FEATURES
• 128x Oversampling
• Sampling Rate up to 108kHz
• 24Bit 8x Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling
• Soft Mute
• THD+N: -100dB
• DR, S/N: 120dB
• I/F format :
MSB justified, 16/20/24bit LSB justified, I2S
• Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
• Power Supply: 4.75 to 5.25V (Analog), 3 to 5.25V (Digital)
• Small Package: 28pin VSOP
DIF0
LRCK
BICK
SDATA
PDN
SMUTE
DIF1
DIF2
DVDD
DVSS
DEM0
DEM1
AVDD AVSS
BVSS
De-emphasis
Control
Audio Data
Interface
VCOM
De-emphasis
Soft Mute
8x
Interpolator
∆Σ
Modulator
SCF
De-emphasis
Soft Mute
8x
Interpolator
∆Σ
Modulator
SCF
AOUTL+
AOUTLAOUTR+
AOUTR-
DFS
Control Register
CSN
CCLK
CDTI
Clock Divider
P/S
MCLK
CKS0
M0039-E-02
CKS1
CKS2 VREFH VREFL
2003/09
-1-
ASAHI KASEI
[AK4393]
„ Ordering Guide
AK4393VF
AKD4393
-40 ~ +85 °C
28pin VSOP (0.65mm pitch)
Evaluation Board
„ Pin Layout
DVSS
1
28
CKS2
DVDD
2
27
CKS1
MCLK
3
26
CKS0
PDN
4
25
P/S
BICK
5
24
VCOM
SDATA
6
23
AOUTL+
LRCK
7
22
AOUTL-
SMUTE/CSN
8
21
AOUTR+
DFS
9
20
AOUTR-
DEM0/CCLK
10
19
AVSS
DEM1/CDTI
11
18
AVDD
DIF0
12
17
VREFH
DIF1
13
16
VREFL
DIF2
14
15
BVSS
Top
View
M0039-E-02
2003/09
-2-
ASAHI KASEI
[AK4393]
PIN/FUNCTION
No.
1
2
3
Pin Name
DVSS
DVDD
MCLK
PDN
I/O
I
I
4
BICK
I
SDATA
I
LRCK
SMUTE
I
I
CSN
DFS
I
I
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DEM0
CCLK
DEM1
CDTI
DIF0
DIF1
DIF2
BVSS
VREFL
VREFH
AVDD
AVSS
AOUTRAOUTR+
AOUTLAOUTL+
VCOM
P/S
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
26
27
28
CKS0
CKS1
CKS2
I
I
I
5
6
7
8
9
10
11
Function
Digital Ground Pin
Digital Power Supply Pin, 3.3V or 5.0V
Master Clock Input Pin
Power-Down Mode Pin
When at “L”, the AK4393 is in power-down mode and is held in reset.
The AK4393 should always be reset upon power-up.
Audio Serial Data Clock Pin
The clock of 64fs or more than is recommended to be input on this pin.
Audio Serial Data Input Pin
2’s complement MSB-first data is input on this pin.
L/R Clock Pin
Soft Mute Pin in parallel mode
When this pin goes "H", soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in serial mode
Double Speed Sampling Mode Pin
(Internal pull-down pin)
“L”: Normal Speed , “H”: Double Speed
De-emphasis Enable Pin in parallel mode
Control Data Clock Pin in serial mode
De-emphasis Enable Pin in parallel mode
Control Data Input Pin in serial mode
Digital Input Format Pin
Digital Input Format Pin
Digital Input Format Pin
Substrate Ground Pin, 0V
Low Level Voltage Reference Input Pin
High Level Voltage Reference Input Pin
Analog Power Supply Pin, 5.0V
Analog Ground Pin, 0V
Rch Negative analog output Pin
Rch Positive analog output Pin
Lch Negative analog output Pin
Lch Positive analog output Pin
Common Voltage Output Pin, 2.6V
Parallel/Serial Select Pin
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
Master Clock Select Pin
Master Clock Select Pin
Master Clock Select Pin
Note: All input pins except internal pull-up/down pins should not be left floating.
M0039-E-02
2003/09
-3-
ASAHI KASEI
[AK4393]
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS = 0V; Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
-0.3
Digital
DVDD
-0.3
| BVSS-DVSS |
(Note 2)
∆ GND
Input Current , Any pin Except Supplies
IIN
Input Voltage
VIND
-0.3
Ambient Operating Temperature
Ta
-40
Storage Temperature
Tstg
-65
Notes: 1. All voltages with respect to ground.
2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.
max
6.0
6.0
0.3
±10
DVDD+0.3
85
150
Units
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
4.75
5.0
(Note 3)
Digital
DVDD
3.0
3.3
Voltage Reference
“H” voltage reference
VREFH
AVDD-0.5
(Note 4)
“L” voltage reference
VREFL
AVSS
VREFH-VREFL
3.0
∆ VREF
Notes: 3. The power up sequence between AVDD and DVDD is not critical.
4. Analog output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
max
5.25
5.25
AVDD
AVDD
Units
V
V
V
V
V
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0039-E-02
2003/09
-4-
ASAHI KASEI
[AK4393]
ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;
RL ≥ 600Ω; External circuit: Figure 11; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
Dynamic Characteristics
24
(Note 5)
THD+N
fs=44.1kHz
0dBFS
BW=20kHz
-60dBFS
fs=96kHz
0dBFS
BW=40kHz
-60dBFS
Dynamic Range
fs=44.1kHz (Note 6)
(-60dBFS with A-weighted)
(Note 7)
fs=96kHz
(Note 7)
S/N
Bits
(A-weighted
112
111
112
111
100
fs=44.1kHz (Note 8)
(Note 7)
fs=96kHz
(Note 7)
Interchannel Isolation (1kHz)
-100
-53
-97
-51
117
120
116
118
117
120
116
118
120
-90
-86
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.15
20
±2.4
0.3
±2.55
dB
ppm/°C
Vpp
Ω
mA
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Resistance
Output Current
(Note 9)
(Note 10)
(Note 11)
±2.25
600
3.5
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
60
mA
DVDD(fs=44.1kHz)
3
mA
DVDD(fs=96kHz)
5
mA
AVDD + DVDD
90
mA
Power-Down Mode (PDN = “L”)
10
50
µA
AVDD + DVDD
(Note 12)
Power Supply Rejection
(Note 13)
50
dB
Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.
At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the eva board manual.
6. 101dB at 16bit data and 116dB at 20bit data.
7. By Figure12. External LPF Circuit Example 2.
8. S/N does not depend on input bit length.
9. The voltage on (VREFH-VREFL) is held +5V externally.
10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
11. For AC-load. 1kΩ for DC-load.
12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK
and LRCK) are held DVSS.
13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
M0039-E-02
2003/09
-5-
ASAHI KASEI
[AK4393]
FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF)
Parameter
Symbol
min
(Note 14)
PB
(Note 14)
SB
PR
SA
GD
0
24.1
typ
max
Units
22.05
20.0
-
kHz
kHz
kHz
dB
dB
1/fs
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 15)
± 0.005
75
-
28
-
Digital Filter + SCF
Frequency Response 0 ∼ 20.0kHz
dB
± 0.2
Note: 14. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.
15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF)
Parameter
Symbol
min
typ
max
Digital Filter
Passband
(Note 14)
PB
0
43.5
±0.01dB
-6.0dB
48.0
Stopband
(Note 14)
SB
52.5
Passband Ripple
PR
± 0.005
Stopband Attenuation
SA
75
Group Delay
(Note 15)
GD
28
Digital Filter + SCF
Frequency Response 0 ∼ 40.0kHz
± 0.3
DC CHARACTERISTICS
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
Input Leakage Current
(Note 16)
Iin
Note: 16. DFS and P/S pins have internal pull-down or pull-up devices, nominally 100kΩ.
M0039-E-02
max
30%DVDD
± 10
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Units
V
V
µA
2003/09
-6-
ASAHI KASEI
[AK4393]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; CL = 20pF)
Parameter
Symbol
min
Master Clock Timing
(Note 17)
Normal Speed: 256fs, Double Speed: 128fs
fCLK
7.7
Pulse Width Low
tCLKL
28
28
Pulse Width High
tCLKH
Normal Speed: 384fs, Double Speed: 192fs
fCLK
11.5
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
Normal Speed: 512fs, Double Speed: 256fs
fCLK
15.4
Normal Speed: 768fs, Double Speed: 384fs
fCLK
23.0
Pulse Width Low
tCLKL
7
Pulse Width High
tCLKH
7
LRCK Frequency
(Note 18)
Normal Speed Mode (DFS = “L”)
fsn
30
Double Speed Mode (DFS = “H”)
fsd
60
Duty Cycle
Duty
45
Serial Interface Timing
BICK Period
tBCK
140
BICK Pulse Width Low
tBCKL
60
Pulse Width High
tBCKH
60
BICK “↑” to LRCK Edge
(Note 19)
tBLR
20
LRCK Edge to BICK “↑”
(Note 19)
tLRB
20
SDATA Hold Time
tSDH
20
SDATA Setup Time
tSDS
20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN High Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 20)
tPW
150
typ
max
Units
13.824
MHz
ns
ns
MHz
ns
ns
MHz
MHz
ns
ns
20.736
27.648
41.472
44.1
88.2
54
108
55
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 17. For Double Speed mode please see Appendix A for relationship of MCLK and BCLK/LRCK.
18. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4393 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
M0039-E-02
2003/09
-7-
ASAHI KASEI
[AK4393]
„ Timing Diagram
1/fCLK
50%DVDD
MCLK
tCLKH
tCLKL
1/fns,1/fds
50%DVDD
LRCK
tBCK
50%DVDD
BICK
tBCKH
tBCKL
Clock Timing
For Double Speed mode timing please see Appendix A for relationship of MCLK and BCLK/LRCK.
LRCK
50%DVDD
tBLR
tLRB
50%DVDD
BICK
tSDS
tSDH
50%DVDD
SDATA
Audio Interface Timing
M0039-E-02
2003/09
-8-
ASAHI KASEI
[AK4393]
CSN
50%DVDD
tCSS
tCCKL tCCKH
CCLK
50%DVDD
tCDS
CDTI
C1
tCDH
C0
R/W
50%DVDD
A4
WRITE Command Input Timing
tCSW
50%DVDD
CSN
tCSH
CCLK
CDTI
50%DVDD
D3
D2
D1
D0
50%DVDD
WRITE Data Input Timing
tPW
PDN
30%DVDD
Power-down Timing
M0039-E-02
2003/09
-9-
ASAHI KASEI
[AK4393]
OPERATION OVERVIEW
„ System Clock
The external clocks, which are required to operate the AK4393, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. However, in Double Speed Mode, the phase
relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A). The MCLK is used to operate the
digital interpolation filter and the delta-sigma modulator. The sampling speed is set by DFS (Table 1). The sampling rate
(LRCK), CKS0/1/2 and DFS determine the frequency of MCLK (Table 2).
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation
mode (PDN = “H”). If these clocks are not provided, the AK4393 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4393 should be in the power-down mode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4393 is in power-down mode
until MCLK and LRCK are input.
DFS
0
1
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
30kHz~54kHz
60kHz~108kHz
Default
Table 1. Sampling Speed
Mode
CKS2
CKS1
CKS0
Normal
Double
0
1
0
0
0
0
0
1
256fs
256fs
128fs
256fs
2
0
1
0
384fs
3
0
1
1
384fs
192fs
384fs
4
5
6
7
1
1
1
1
0
0
1
1
0
1
0
1
512fs
512fs
768fs
768fs
256fs
N/A
384fs
N/A
Default
Table 2. System Clocks
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System clock example (Normal Speed Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 4. System clock example (Double Speed Mode)
M0039-E-02
2003/09
- 10 -
ASAHI KASEI
[AK4393]
„ Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising
edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
Mode
0: 16bit LSB Justified
1: 20bit LSB Justified
2: 24bit MSB Justified
3: I2S Compatible
4: 24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Table 5. Audio Data Formats
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
6
1
5
14
4
15
3
16
2
17
1
0
31
15
0
14
6
1
5
14
4
15
3
16
2
17
1
15
0
31
0
14
1
BICK
(64fs)
SDATA
Mode 0
15
Don’t care
14
15 14
Don’t care
0
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
9
8
10
11
12
31
0
1
9
8
10
11
12
31
0
1
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
M0039-E-02
2003/09
- 11 -
ASAHI KASEI
[AK4393]
LRCK
0
1
2
22
24
23
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
24
23
31
25
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
„ De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with the DEM0, DEM1 and DFS input pins.
DEM1
DEM0
DFS
Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
Default
Table 6. De-emphasis filter control
M0039-E-02
2003/09
- 12 -
ASAHI KASEI
[AK4393]
„ Soft mute operation
Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞
during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SM UTE
1024/fs
0dB
1024/fs
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AO UT
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
Figure 5. Soft mute operation
M0039-E-02
2003/09
- 13 -
ASAHI KASEI
[AK4393]
„ System Reset
The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 is in the
power-down mode until MCLK and LRCK are input.
„ Power-Down
The AK4393 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 6. Power-down/up sequence example
„ Click Noise from analog output
Click noise occurs from analog output in the following cases.
1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,
2) When switching serial data mode by DIF0, DIF1 and DIF2 pins,
3) When going and exiting power down mode by PDN pin,
4) When switching normal speed and double speed by DFS pin,
However in case of 1) & 2), If the input data is “0” or the soft mute is enabled (after 1024 LRCK cycles from SMUTE
= “H”), no click noise occur except for switching DFS pin.
M0039-E-02
2003/09
- 14 -
ASAHI KASEI
[AK4393]
„ Mode Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0,
CKS2-0 and DFS, the setting of pin and register are “ORed” internally. So, even serial control mode, pin setting can also
control these functions.
The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers
may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address
(2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB
first, 8bits). The AK4393 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge.
The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz(max). The CSN and CCLK must be
fixed to “H” when the register does not be accessed.
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4393 should be reset
by PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (Fixed to “01”)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 7. Control I/F Timing
*The AK4393 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4393 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
*For setting the registers, the following sequence is recommended.
y Control 1 register
(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.
y Control 2 register
This writing sequence has no limitation like control 1 register.
*When RSTN = “0”, the click noise is output from AOUT pins.
*If the mode setting is done without setting RSTN = “0”, large noise may be output from AOUT pins. (Especially when
CKS0/1/2 are changed.)
M0039-E-02
2003/09
- 15 -
ASAHI KASEI
[AK4393]
„ Register Map
Addr
00H
01H
02H
Register Name
Control 1
Control 2
Test
D7
D6
D5
D4
D3
D2
D1
D0
0
0
TEST7
CKS2
0
TEST6
CKS1
0
TEST5
CKS0
0
TEST4
DIF2
DFS
TEST3
DIF1
DEM1
TEST2
DIF0
DEM0
TEST1
RSTN
SMUTE
TEST0
Notes:
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only
internal timing is reset and the registers are not initialized to their default values. DIF2-0, CKS2-0 and DFS bits are
ORed with pins respectively.
„ Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
0
CKS2
CKS1
CKS0
DIF2
DIF1
DIF0
RSTN
default
0
0
0
0
0
0
0
1
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 5)
Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.
CKS2-0: Master Clock Frequency Select (see Table 2)
Initial: “000”, Mode 0
Register bits are ORed with CKS2-0 pins if P/S = “L”.
Addr
01H
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
Register Name
0
0
0
0
DFS
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
0
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis response (see Table 6)
Initial: “00”, 44.1kHz
DFS: Sampling speed control (see Table 1)
0: Normal speed
1: Double speed
Register bit is ORed with DFS pin if P/S = “L”.
Addr
02H
Register Name
Test
default
D7
D6
D5
D4
D3
D2
D1
D0
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
0
0
0
0
0
0
0
0
TEST7-0: Test mode. Do not write any data to 02H.
M0039-E-02
2003/09
- 16 -
ASAHI KASEI
[AK4393]
SYSTEM DESIGN
Figure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
Digital
Supply
10u 0.1u
+
1
DVSS
CKS2
28
2
DVDD
CKS1
27
Master Clock
3
MCLK
CKS0
26
Reset & Power down
4
PDN
P/S
25
64fs
5
BICK
VCOM
24
24bit Audio Data
6
SDATA
AOUTL+
23
Lch
7
LRCK
AOUTL-
22
LPF
8
CSN
AOUTR+
21
Micro-
9
DFS
AOUTR-
20
Rch
LPF
controller
10
CCLK
AVSS
11
CDTI
AVDD
12
DIF0
VREFH
13
DIF1
VREFL
14
DIF2
BVSS
fs
Digital Ground
AK4393
0.1u
19
0.1u
18
10u
+
17
0.1u
16
+
10u
10u
+
Lch Out
Rch Out
Analog
Supply 5V
15
Analog Ground
Figure 8. Typical Connection Diagram (Serial mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
M0039-E-02
2003/09
- 17 -
ASAHI KASEI
[AK4393]
Digital
Supply
10u 0.1u
+
1
DVSS
CKS2
28
Master
2
DVDD
CKS1
27
Clock
Select
Master Clock
3
MCLK
CKS0
26
Reset & Power down
4
PDN
P/S
25
64fs
5
BICK
VCOM
24
24bit Audio Data
6
SDATA
AOUTL+
23
Lch
7
LRCK
AOUTL-
22
LPF
8
SMUTE
AOUTR+
21
9
DFS
AOUTR-
20
Rch
LPF
10
DEM0
AVSS
11
DEM1
AVDD
12
DIF0
VREFH
13
DIF1
VREFL
14
DIF2
BVSS
fs
Mode
setting
Digital Ground
AK4393
0.1u
19
0.1u
18
+ 10u
17
0.1u
16
+
10u
10u
+
Lch Out
Rch Out
Analog
Supply 5V
15
Analog Ground
Figure 9. Typical Connection Diagram (Parallel mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
Digital Ground
Analog Ground
System
Controller
1
DVSS
CKS2
28
2
DVDD
CKS1
27
3
MCLK
CKS0
26
4
PDN
P/S
25
5
BICK
VCOM
24
6
SDATA
AOUTL+
23
7
LRCK
AOUTL-
22
8
SMUTE
AOUTR+
21
9
DFS
AOUTR-
20
10
DEM0
AVSS
19
11
DEM1
AVDD
18
12
DIF0
VREFH
17
13
DIF1
VREFR
16
14
DIF2
BVSS
15
AK4393
Figure 10. Ground Layout
M0039-E-02
2003/09
- 18 -
ASAHI KASEI
[AK4393]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and
DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS must be connected
to analog ground plane. System analog ground and digital ground should be connected together near to where the
supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as
possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4393.
3. Analog Outputs
The analog outputs are full differential outputs and 2.4Vpp ([email protected]=5V) centered around VCOM. The differential
outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1,
the output range is 4.8Vpp ([email protected]=5V). The bias voltage of the external summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and
a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
Figure 11 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 12 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4393
AOUT-
1k
1k
1k
1n
+Vop
3.3n
AOUT+
1k
Analog
Out
1k
1k
1n
-Vop
Figure 11. External LPF Circuit Example 1
M0039-E-02
2003/09
- 19 -
ASAHI KASEI
[AK4393]
+15
+
10n
300
620
AOUTL- +
300
7
3
2 +
4
10n
-15
10u
0.1u
6
NJM5534D
+
10u
0.1u
300
220
3
2
2 - 4
3 + 7
620
10n
47u
7
3
+
2 4
620
300
300
10n
10u
100
6
Lch
430
4.7n NJM5534D
0.1u
6
NJM5534D
0.1u
+
+
10u
10u
0.1u
300
220
100
620
AOUTL+ +
+10u
4.7n
1
+
0.1u
430
100
47u
Figure 12. External LPF Circuit Example 2
M0039-E-02
2003/09
- 20 -
ASAHI KASEI
[AK4393]
PACKAGE
28pin VSOP (Unit: mm )
*9.8±0.2
1.25±0.2
0.675
28
A
7.6±0.2
*5.6±0.2
15
14
1
0.65
0.22±0.1
+0.1
0.15-0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound:
Epoxy
Lead frame material:
Cu
Lead frame surface treatment:
Solder plate
M0039-E-02
2003/09
- 21 -
ASAHI KASEI
[AK4393]
MARKING
AKM
AK4393VF
XXXBYYYYC
XXXXBYYYYC data code identifier
XXXB:
YYYYC:
Lot number (X : Digit number, B : Alpha character )
Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE
• These products and their specif ications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales off ice or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of lif e or in
significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
M0039-E-02
2003/09
- 22 -
ASAHI KASEI
[AK4393]
Appendix A
In Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase
relationship happens during this prohibited period, it is possible to occur the inverse of output channel. The phase
relationship must be set to avoid the prohibited period when the AK4393 operates at Double Speed Mode. The prohibited
period is specified by the combination of digital power supply voltage (DVDD), MCLK frequency and audio data format
(Table 5). When the audio data formats are 16/20/24bit LSB Justified (Mode 0,1,4) and 24bit MSB Justified (Mode 2), the
phase relationship (tLRM: Figure 11) between the rising edge of LRCK and the rising edge of MCLK has the prohibited
period of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship between the falling edge of BICK
and the rising edge of MCLK has the prohibited period (tBCM: Figure 12)
Sampling
Mode
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Double Speed
Digital Power
Supply, DVDD
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
3.0 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
4.75 to 5.25V
MCLK
Frequency
128fs
192fs
256fs
256fs
384fs
384fs
128fs
192fs
256fs
256fs
384fs
384fs
Mode Setting
CKS2
CKS1
CKS0
DFS
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Prohibited Period
min
max
0.4
1.7
-0.5
0.8
-0.7
0.7
-0.7
0.7
-1.7
-0.3
-1.7
-0.3
0.8
1.5
-0.2
0.5
-0.3
0.4
-0.3
0.4
-1.0
-0.3
-1.0
-0.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7. Prohibited Period
LRCK
50%DVDD
tLRM
MCLK
50%DVDD
Figure 11. 16/20/24bit LSB Justified, 24bit MSB Justified
BICK
50%DVDD
tBCM
MCLK
50%DVDD
Figure 12. I2S Compatible
M0039-E-02
2003/09
- 23 -