AKM AK4563A

ASAHI KASEI
[AK4563A]
AK4563A
Low Power 16bit 4ch ADC & 2ch DAC with ALC
GENERAL DESCRIPTION
The AK4563A is low power operation, 16bit CODEC that include 4ch ADC and 2ch DAC. The AK4563A
also includes ALC (Automatic Level Control) circuit, therefore is suitable for microphone application and
etc. As the ALC circuit can be stopped by controlling µP, IPGA can also be used as the manual volume.
Digital I/F can be input/output from 1.5V to 3.0V by external power supply. The AK4563A can be
powered-down by each block, therefore the AK4563A is suitable to low power dissipation in system.
FEATURES
1. Resolution : 16bits
2. Recording Functions
• 4ch Analog Input PGA (Programmable Gain Amplifier)
• Digital ALC (Automatic Level Control) circuit
• FADEIN / FADEOUT
• Digital HPF for DC-offset cancellation ([email protected]=48kHz)
• Peak-Meter Output (2ch)
3. Playback Function
• Digital De-emphasis Filter (tc = 50/15µs, fs=32k, 44.1k and 48kHz)
4. Power Management
5. CODEC (ADC: 4ch, DAC: 2ch)
• Single-ended Inputs/Outputs
• Input / Output Level: [email protected]=2.5V (= 0.6 x VREF)
• S/(N+D): 83dB(ADC), 86dB(DAC) @VREF=2.5V
• DR, S/N: 87dB(ADC), 91dB(DAC) @VREF=2.5V
6. Master Clock: 256fs/384fs
7. Sampling Rate: 8kHz ∼ 50kHz
8. Audio Data Interface Format: MSB-First, 2’s compliment (AK4516A Compatible)
• ADC: 16bit MSB justified, 16bit LSB justified, I2S
• DAC: 16bit MSB justified, 16bit LSB justified, I2S
9. Power Supply
• CODEC, PGA: 2.3 ∼ 3.0V (typ.2.5V)
• Digital I/F: 1.5 ∼ 3.0V(typ.2.5V)
10. Power Supply Current
• ALL Power ON: 18mA
• (ALC + ADC) x 4ch: 13.5mA
• DAC: 5.5mA
11. Ta = -20 ∼ 85 ºC
12. Package: 28pin VSOP
MS0067-E-02
2004/12
-1-
ASAHI KASEI
INTL0
EXTL
LIN
[AK4563A]
IPGA0
ADC0
HPF
INTR0
EXTR
RIN
Audio I/F
Controller
INTL1
IPGA1
LRCK
BCLK
SDTO0
SDTO1
SDTI
HPF
ADC1
INTR1
VD
VT
DGND
PDN
LOUT
De-emp
DAC
ROUT
VCOM
VREF
VA
AGND
Control Register I/F
CSN
CCLK
CDTI
Clock Divider
CDTO
MCLK
Figure 1. AK4563A Block Diagram
MS0067-E-02
2004/12
-2-
ASAHI KASEI
[AK4563A]
„ Ordering Guide
AK4563AVF
AKD4563A
-20 ∼ +85°C
28pin VSOP (0.65mm pitch)
Evaluation board for AK4563A
„ Pin Layout
LOUT
1
28
PDN
ROUT
2
27
CCLK
INTL1
3
26
CSN
INTR1
4
25
CDTI
INTL0
5
24
CDTO
INTR0
6
23
BCLK
EXTL
7
22
MCLK
EXTR
8
21
LRCK
LIN
9
20
SDTI
RIN
10
19
SDTO1
VCOM
11
18
SDTO0
AGND
12
17
VT
VA
13
16
DGND
VREF
14
15
VD
AK4563A
Top
View
MS0067-E-02
2004/12
-3-
ASAHI KASEI
[AK4563A]
PIN / FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
Pin Name
LOUT
ROUT
INTL1
INTR1
INTL0
INTR0
EXTL
EXTR
LIN
RIN
I/O
O
O
I
I
I
I
I
I
I
I
11
VCOM
O
12
13
AGND
VA
-
14
VREF
I
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VD
DGND
VT
SDTO0
SDTO1
SDTI
LRCK
MCLK
BCLK
CDTO
CDTI
CSN
CCLK
PDN
O
O
I
I
I
I
O
I
I
I
I
Function
Lch Analog Output Pin
Rch Analog Output Pin
Lch INT #1 Input Pin
Rch INT #1 Input Pin
Lch INT #0 Input Pin
Rch INT #0 Input Pin
Lch EXT Input Pin
Rch EXT Input Pin
Lch Line Input Pin
Rch Line Input Pin
Common Voltage Output Pin, 0.45 x VA
Bias voltage of ADC inputs and DAC outputs
Analog Ground Pin
Analog Power Supply Pin, +2.3 ∼ 3.0V
ADC & DAC Voltage Reference Input Pin, VA
Used as a voltage reference of ADC & DAC. VREF is connected externally to
fltered VA.
Digital Power Supply Pin, +2.3 ∼ 3.0V
Digital Ground Pin
Digital I/F Power Supply Pin, +1.5 ∼ 3.0V
Audio Serial Data #0 Output Pin
Audio Serial Data #1 Output Pin
Audio Serial Data Input Pin
Input/Output Channel Clock Pin
Master Clock Input Pin
Audio Serial Data Clock Pin
Control Data Output Pin
Control Data Input Pin
Chip Select Pin
Control Data Clock Pin
Power Down & Reset Pin, “L”: Power Down & Reset, “H”: Normal Operation
Note: All digital input pins should not be left floating.
MS0067-E-02
2004/12
-4-
ASAHI KASEI
[AK4563A]
ABSOLUATE MAXIMUM RATING
(AGND, DGND=0V; Note 1)
Parameter
Symbol
min
Power Supply
Analog (VA pin)
VA
-0.3
Digital 1 (VD pin)
VD
-0.3
Digital 2 (VT pin)
VT
-0.3
| DGND – AGND | (Note 2)
∆GND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage
VINA
-0.3
INTL1-0, INTR1-0, EXTL, EXTR, LIN, RIN, VREF
Digital Input Voltage
VIND
-0.3
Ambient Temperature
Ta
-20
Storage Temperature
Tstg
-65
max
4.6
4.6
4.6
0.3
±10
Units
V
V
V
V
mA
VA+0.3
V
VT+0.3
85
150
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AGND and DGND should be the same voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter
Symbol
min
typ
Power Supply Analog (VA pin)
VA
2.3
2.5
Digital 1 (VD pin) (Note 3)
VD
2.3 or VA-0.3
2.5
Digital 2 (VT pin)
VT
1.5
2.5
Reference
Analog Reference Voltage
VREF
Voltage
(VREF pin) (Note 4)
Note 1. All voltages with respect to ground.
Note 3. Minimum value is the high value either 2.3V or VA-0.3V.
Note 4. VREF and VA should be same voltage.
max
3.0
VA
VD
Units
V
V
V
VA
V
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0067-E-02
2004/12
-5-
ASAHI KASEI
[AK4563A]
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD, VT=2.5V; fs=48kHz; Signal Frequency =1kHz; Measurement frequency = 10Hz ∼ 20kHz;
S/(N+D), D-Range and S/N are value against Full-scale; Unless otherwise specified)
Parameter
min
typ
max
Units
Input PGA Characteristics (IPGA):
Input Voltage
1.35
1.5
1.65
Vpp
(INTL1-0, INTR1-0, EXTL, EXTR, LIN, RIN pins) (Note 5)
Input Resistance: MIC (INTL1-0,INTR1-0,EXTL,EXTR pins)
6.5
10
14.5
kΩ
LINE (LIN, RIN pins)
80
125
176
MIC
LINE
Step Size
0.1
0.5
0.9
dB
+28dB
∼
-8dB
+6dB
∼ -30dB
(Note 6)
0.1
1
1.9
dB
-8dB ∼ -16dB
-30dB ∼ -38dB
0.1
2
3.9
dB
-16dB ∼ -32dB
-38dB ∼ -54dB
2
dB
-32dB ∼ -40dB
-54dB ∼ -62dB
4
dB
-40dB ∼ -52dB
-62dB ∼ -74dB
ADC Analog Input Characteristics: (Note 7)
Resolution
16
Bits
S/(N+D)
(-2dBFS Input)
74
83
dB
D-Range
(EIAJ)
81
87
dB
S/N
(EIAJ)
81
87
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DAC Analog Output Characteristics: Measured by LOUT/ROUT
Resolution
16
Bits
S/(N+D)
(0dBFS Input)
77
86
dB
D-Range
(EIAJ)
85
91
dB
S/N
(EIAJ)
85
91
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Output Voltage (Note 8)
1.35
1.5
1.65
Vpp
Load Resistance
10
kΩ
Load Capacitance
20
pF
Power Supplies
Power Supply Current: VA+VD+VT
Normal Operation (PDN= “H”)
18
27
mA
All Power ON (PM4-0= “1”)
13.5
mA
IPGA0+ADC0+IPGA1+ADC1 (PM3-0= “1”)
5.5
mA
DAC (PM4= “1”)
Power-down mode (PDN= “L”) (Note 9)
10
100
µA
Note 5. Full-scale voltage of analog inputs when IPGA0 and IPGA1 bits are “0” and are set to 0dB. Its voltage is
proportional to VREF. Vin = 0.6 x VREF.
Note 6. IPGA1 does not have a gain table of LINE side.
Note 7. ADC0 is input from INTL0/INTR0 or EXTL/EXTR or LIN/RIN and it measures included in IPGA0. The gain of
IPGA0 is set 0dB. ADC1 is input from INTL1/INTR1 and it measures included in IPGA1. The gain of IPGA1 is
set 0dB.
DC-offset in “IPGA0+ADC0” and “IPGA1+ADC1” are cancelled by internal HPF.
Note 8. Analog output voltage is proportional to VREF. Vout = 0.6 x VREF.
Note 9. All digital input pins except for PDN pin are held VT or DGND, and PDN pin is held DGND.
MS0067-E-02
2004/12
-6-
ASAHI KASEI
[AK4563A]
FILTER CHARCTERISTICS
(Ta=25°C; VA, VD=2.3 ∼ 3.0V; VT=1.5∼ 3.0V; fs=48kHz; De-emphasis = OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 10)
±0.1dB
PB
0
18.9
kHz
-1.0dB
21.8
kHz
-3.0dB
23.0
kHz
Stopband (Note 10)
SB
29.4
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
65
dB
Group Delay (Note 11)
GD
17.0
1/fs
Group Delay Distortion
0
∆GD
µs
ADC Digital Filter (HPF):
Frequency Response (Note 10) -3.0dB
FR
3.7
Hz
-0.56dB
10
Hz
-0.15dB
20
Hz
DAC Digital Filter:
Passband (Note 10)
±0.1dB
PB
0
21.7
kHz
-6.0dB
24.0
kHz
Stopband (Note 10)
SB
26.2
kHz
Passband Ripple
PR
dB
±0.06
Stopband Attenuation
SA
43
dB
Group Delay (Note 11)
GD
14.8
1/fs
Group Delay Distortion
0
∆GD
µs
DAC Digital Filter + Analog Filter:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±0.5
Note 10. The passband and stopband frequencies scale with fs. For example, ADC: PB=0.454 x fs(@-1.0dB), DAC:
PB=0.454 x fs(@-0.1dB).
Note 11. The calculating delay time which occurred by digital filtering. The time is from the input of analog signal to
setting the 16bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 16bit data of both channels on input register to the output of analog signal.
DC CHARACTERISTICS
(Ta=25°C; VA, VD=2.3 ∼ 3.0V, VT=1.5 ∼ 3.0V)
Parameter
Symbol
min
Input High Level Voltage
VIH
80%VT
Input Low Level Voltage
VIL
VOH
VT-0.4
Output High Level Voltage: Iout=-400µA
VOL
Output Low Level Voltage: Iout=400µA
Input Leakage Current
Iin
-
MS0067-E-02
typ
-
max
20%VT
0.4
±10
Units
V
V
V
V
µA
2004/12
-7-
ASAHI KASEI
[AK4563A]
SWITCHING CHARASTERISTICS
(Ta=25°C; VA, VD=2.3 ∼ 3.0V, VT=1.5 ∼ 3.0V; CL=20pF)
Parameter
Symbol
min
Control Clock Frequency
Master Clock(MCLK) 256fs: Frequency
fCLK
2.048
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
384fs: Frequency
fCLK
3.072
Pulse Width Low
tCLKL
23
Pulse Width High
tCLKH
23
Channel Selection Clock (LRCK) frequency
fs
8
Duty
45
Audio Interface Timing
BCLK Period
tBLK
312.5
BCLK Pulse Width Low
tBLKL
130
Pulse Width High
tBLKH
130
BCLK “↓” to LRCK
tBLR
-tBLKH+50
LRCK to SDTO(MSB) (Except IIS mode)
tDLR
BCLK “↓” to SDTO
tDSS
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High 1
Pulse Width High 2
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Output Delay Time
CSN “↑” to CDTO(Hi-Z)(Note 13)
tCCK
tCCKL
tCCKH
tCKH2
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200(Note 12)
80
80
80
50
50
150(Note 12)
50(Note 12)
50
Reset/Calibration Timing
PDN Pulse Width
PDN “↑” to SDTO0/SDTO1 valid
tPDW
tPDV
150
typ
max
Units
12.288
12.8
18.432
19.2
48
50
50
55
MHz
ns
ns
MHz
ns
ns
kHz
%
tBLKL-50
80
80
70
70
4128
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note 12. fs ≥ 22.4kHz.
In the case of fs < 22.4kHz, these three parameters must meet a relationship of
(tCSW + tCSS + 6 × tCCK) > 1/(32 × fs) in addition to these specifications. For example, when tCCK=200ns
and tCSS=50ns at fs=8kHz, tCSW(min) is 2657ns. When tCSW=150ns and tCSS=50ns fs=8kHz, tCCK(min) is
618ns.
When 08H or 09H address is read and fs < 39.1kHz, tCCK must meet a relationship tCCK > 1/(128 × fs) in
addition to these specifications. For example, when fs=8kHz, tCCK(min) is 977ns.
Note 13. RL=1kΩ/10% Change (Pulled-up operates for VT.)
MS0067-E-02
2004/12
-8-
ASAHI KASEI
[AK4563A]
„ Timing Diagram
LRCK
tBLR
50%VT
tBLKH
tBLKL
BCLK
50%VT
tDLR
tDSS
SDTO0,1
50%VT
D15 (MSB)
tSDS
SDTI
tSDH
LSB
50%VT
Figure 2. Audio Data Input/Output Timing (Audio I/F Format: No.0)
CSN
50%VT
tCSS
tCCKL tCCKH
CCLK
50%VT
tCDH
tCDS
CDTI
op0
op1
op2
A0
50%VT
Hi-Z
CDTO
Figure 3. WRITE/READ Command Input Timing
tCSW
CSN
50%VT
tCSH
CCLK
CDTI
CDTO
50%VT
D4
D5
D6
D7
50%VT
Hi-Z
Figure 4. WRITE Data Input Timing
MS0067-E-02
2004/12
-9-
ASAHI KASEI
[AK4563A]
CSN
50%VT
tCKH2
CCLK
CDTI
50%VT
A3
A4
50%VT
tDCD
Hi-Z
CDTO
D0
D1
D2
50%VT
Figure 5. READ Data Output Timing 1
tCSW
CSN
50%VT
tCSH
CCLK
50%VT
CDTI
50%VT
tCCZ
CDTO
D4
D5
D6
D7
50%VT
Figure 6. READ Data Input Timing 2
tPDW
PDN
50%VT
tPDV
SDTO0,1
50%VT
Figure 7. Reset Timing
MS0067-E-02
2004/12
- 10 -
ASAHI KASEI
[AK4563A]
OPERATION OVERVIEW
„ System Clock Input
The clocks which are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC or DAC is in operation. If these
clocks are not provided, the AK4563A may draw excess current and it is not possible to operate properly because utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4563A should be in the power-down
mode.
„ System Reset
AK4563A should be reset once by bringing PDN pin “L” upon power-up. After the system reset operation, the all internal
AK4563A registers are initial value.
The initial cycle is [email protected]=48kHz. During offset calibration, the ADC digital data outputs of both channels
are forced to a 2’s compliment “0”. Output data of settles data equivalent for analog input signal after offset calibration.
This cycle is not for DAC.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
MS0067-E-02
2004/12
- 11 -
ASAHI KASEI
[AK4563A]
Power Supply
PDN pin
PDN pin may be “L” at power-up.
ADC Internal
PD
State
4128/fs
4128/fs
PM
Normal
INIT
GD
INIT
Normal
GD (1)
GD
AIN
SDTO0,1
DAC Internal
State
(2)
(3) “0”data
Idle Noise
“0”data
PD
Normal
(1)
PM
SDTI
Normal
“0”data
GD (1)
GD (1)
AOUT
GD (1)
(4)
(4)
Control register
INIT-1
INIT-2
Inhibit-1
Inhibit-2
Normal
INIT-2
Normal
W rite to register
Normal
Read from register
Inhibit-1
Normal
External clocks
(5)
The clocks may be stopped.
Figure 8. Power-up/Power-down Timing Example
• INIT:
Initializing. At this time, STAT bit is “0”. When this flag becomes “1”, INIT process has completed.
IPGA0 and IPGA1 are MUTE state.
• PD:
Power-down state. ADC is output “0”, analog output of DAC goes floating.
• PM:
Power-down state by operating Power Management bit
• INIT-1:
Initializing all registers.
• INIT-2:
Initializing read only registers in control registers.
• Inhibit-1: Inhibits writing and reading to all control registers.
• Inhibit-2: Inhibits writing to all control registers.
Note: Please refer to “explanation of register” about the condition of each register.
(1) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(2) If the analog signal does not be input, the digital outputs have the op-amp of input and some noise in ADC.
(3) ADC data is “0” data at power-down.
(4) A few noise occurs at the “↓ ↑” of PDN signal. Please mute the analog output externally if the noise influences
the system application.
(5) When the external clocks are stopped, the AK4563A should be in the power-down mode (PDN pin = “L” or
PM5-0 bit = “0”) .
MS0067-E-02
2004/12
- 12 -
ASAHI KASEI
[AK4563A]
„ Digital High Pass Filter (HPF)
The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.7Hz (@fs=48kHz) and it is -0.15dB at
20Hz. It also scales with the sampling frequency (fs).
„ Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO0, 1 pins using BCLK and LRCK inputs. Four serial data are selected by the DIF0
and DIF1 pins as shown in Table 1. In all modes, the serial data is MSB-first, 2's compliment format and it is latched by
“↑” of BCLK.
When DIF1= “0” and DIF0=”1”, only BCLK=64fs is acceptable.
No.
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO0/SDTO1(ADC)
SDTI(DAC)
MSB justified
LSB justified
LSB justified
LSB justified
MSB justified
MSB justified
I2S compatible
I2S compatible
Table 1. Audio Data Format
BCLK
≥ 32fs
= 64fs
≥ 32fs
≥ 32fs
Figure
Figure 9
Figure 10
Figure 11
Figure 12
RESET
LRCK
0
1
2
8
3
9
10
11
12
13
14
15
0
1
2
8
3
9
10
11
12
13
14
15
0
1
BCLK(32fs)
SDTO(o)
SDTI(i)
15 14 13
0
1
2
8
7
3
6
14
5
15
4
16
3
17
2
1
18
0
31
15 14 13
0
1
2
8
7
3
6
14
5
15
4
16
3
17
2
1
18
0
31
15
0
1
BCLK(64fs)
SDTO0,1(o)
15 14 13
SDTI(i)
13 2
1
0
15 14 13
Don’t Care
15 14
1
1
2
1
0
15
Don’t Care
0
15 14
1
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Audio Data Timing (No.0)
LRCK
0
1
2
15
16
17
18
19
20
31
0
1
2
15
16
17
18
19
20
31
0
1
BCLK(64fs)
SDTO0,1(o)
SDTI(i)
15
15 14 13 12
Don’t Care
15 14 13 12
15:MSB, 0:LSB
4
1
0
1
0
15
Don’t Care
Lch Data
15 14 13
12
1
0
15 14 13 12
1
0
19
Rch Data
Figure 10. Audio Data Timing (No.1)
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
LRCK
0
1
2
8
9
10
11
12
13
14
15
0
1
2
8
9
10
11
12
13
14
15
0
1
BCLK(32fs)
SDTO0,1(o)
SDTI(I)
15 14
0
1
8
2
7
3
6
14
5
15
4
16
3
17
2
1
18
0
31
15 14
0
1
8
2
7
3
14
6
14
5
15
4
16
3
17
2
1
18
0
31
15
0
1
BCLK(64fs)
SDTO0,1(o)
15 14 13
13 2
1
0
SDTI(i)
15 14 13
13 2
1
0
Don’t Care
15 14 13 14
2
1
0
15 14 13 14
2
1
0
15
Don’t Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Audio Data Timing (No.2)
LRCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
4
9
10
11
12
13
14
15
0
1
BCLK(32fs)
SDTO0,1(o)
SDTI(I)
0
0
15
1
14 13
2
3
4
7
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1
2
3
7
44
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
1
BCLK(64fs)
SDTO0,1(o)
15 14 13
2
1
0
SDTI(i)
15 14 13
2
1
0
15:MSB, 0:LSB
Don’t Care
15 14 13
2
2
1
0
15 14 13
2
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 12. Audio Data Timing (No.3)
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
„ Control Register R/W Timing
The data on the 4 wires serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The transmitting data is output to each bit by “↓” of CCLK, the receiving data is latched by “↑” of CCLK. Writing
data becomes effective by “↑” of CSN. Reading data becomes Hi-z (Floating) by “↑” of CSN. CSN should be held to “H”
at no access. In case of connecting between CDTI and CDTO, the I/F can be also contolled by 3-wires.
CCLK always needs 16 edges of “↑” during CSN = “L”. Reading/Writing of the address except 00H ∼ 09H are inhibited.
Reading/Writing of the control registers by except op0 = op1 = “1” are invalid.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
WRITE
CDTI
op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
“1” “1” “1”
Hi-Z
CDTO
CDTI
READ
CDTO
op0 op1 op2 A0 A1 A2 A3 A4
“1” “1” “0”
Hi-Z
D0 D1 D2 D3 D4 D5 D6 D7
Hi-Z
op0-op2: Op code (110:READ, 111:WRITE)
A0-A4: Register Address
D0-D7: Control data
Figure 13. Control Data Timing
MS0067-E-02
2004/12
- 15 -
ASAHI KASEI
[AK4563A]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Input Select
Power Management
Mode Control
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Operation Mode
Input PGA Control
Peak Hold Lch
Peak Hold Rch
D7
0
0
0
D6
0
0
0
FDTM1
FDTM0
0
0
0
0
PHL7
PHR7
0
REF6
0
IPGA6
PHL6
PHR6
D5
0
PM5
0
ZTM1
D4
0
PM4
FS
ZTM0
LMAT1
LMAT0
REF5
ZELMN
IPGA5
PHL5
PHR5
REF4
FR
IPGA4
PHL4
PHR4
D3
LINE
PM3
DIF1
WTM1
FDATT
REF3
STAT
IPGA3
PHL3
PHR3
D2
EXT
PM2
DIF0
WTM0
RATT1
REF2
FDIN
IPGA2
PHL2
PHR2
D1
INT1
PM1
DEM1
LTM1
RATT0
REF1
IPGA1
PHL1
PHR1
D0
INT0
PM0
DEM0
LTM0
LMTH
REF0
ALC
IPGA0
PHL0
PHR0
D3
LINE
D2
EXT
D1
INT1
D0
INT0
0
0
1
1
FDOUT
„ Register Definitions
The following condition can not read and write all registers.
* PDN pin = “L”
Addr
00H
Register Name
Input Select
R/W
RESET
D7
0
D6
0
D5
0
D4
0
0
0
0
0
R/W
INT0: Select ON/OFF of INTL0 and INTR0 (0: OFF, 1: ON)
INT1: Select ON/OFF of INTL1 and INTR1 (0: OFF, 1: ON)
EXT: Select ON/OFF of EXTL and EXTR (0: OFF, 1: ON)
LINE: Select ON/OFF of LIN and RIN (0:OFF, 1:ON)
When LINE bit is “1”, INT0, INT1 and EXT bits are ignored.
Gain tables of IPGA0 and IPGA1 are changed by LINE bit.
When LINE bit is “1”, gain table of IPGA becomes LINE side. But IPGA1 becomes mute state because it does not
have a LINE table.
When INT0 and EXT bits change into “1” at the same time, input signals are mixed by Gain 0dB.
MS0067-E-02
2004/12
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ASAHI KASEI
Addr
01H
[AK4563A]
Register Name
Power Management
R/W
RESET
D7
0
D6
0
D5
PM5
D4
PM4
0
0
0
1
D3
PM3
D2
PM2
D1
PM1
D0
PM0
1
1
1
1
R/W
PM5-0: Power Management (0: Power down, 1: Power up)
PM1-0: IPGA and ALC circuit power control.
After exiting PM1-0 = “00”, IPGA goes reset value. (refer to “Operation of IPGA” description)
PM1
PM0
IPGA1
IPGA0
0
0
OFF
OFF
0
1
OFF
ON
1
0
Lch ON
ON
1
1
ON
ON
Table 2. IPGA and ALC circuit power control
PM3-2: Power control of ADC
PM3
PM2
ADC1
ADC0
0
0
OFF
OFF
0
1
OFF
ON
1
0
Lch ON
ON
1
1
ON
ON
Table 3. ADC power control
RESET
RESET
When the number of ADC channels is changed, PM3-2 bits should be via “00” (ADC0 and
ADC1 are powerd-down.).
For example, in case of changing from 2ch mode (PM3-2 bits = “01”) to 4ch mode (PM3-2 bit
= “11”), PM3-2 bit should change into “11” via “00”.
All Power-down
2ch Mode
(PM3-2 = “00”)
(PM3-2 = “01”)
3ch Mode
4ch Mode
(PM3-2 = “10”)
(PM3-2 = “11”)
Figure 14. ADC Power-up/down Sequence by Power Management bit
In case of exiting all power-down mode (PM3-2 = “00”), the initializing cycle (4128/fs) is
started. Then all outputs of ADC become “0”.
In case of 3ch mode (PM1-0 = “10”, PM3-2 = “10”), right channel of IPGA1 and ADC1 is
powered-down. Then right channel of ADC1 is output “0”.
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
PM4: Power control of DAC
PM5: Used both as power control of analog loopback circuit and as selection of MUX. (0: DAC, 1:
Analog loopback)
When PM5 goes “1”, input for output-AMP is selected to analog loopback circuit from DAC
output. Output MUX and AMP are powered-down when PDN = “L” or PM4 = PM5 = “0”.
The loopback output and the MUX selecting DAC output is a MIXER with the switch in
practice. Therefore, when both PM4 and PM5 select ON, the analog loopback signal and DAC
output are mixed by Gain 1.
PM5-0 bits can be partially powered-down by ON/OFF (“1”/ “0”) of PM5-0 bits. When PDN pin
goes “L”, all the circuit in AK4563A can be powered-down regardless of PM5-0 bits.
When the AK4563A is powered-down by PM5-0 bits, contents of registers are kept.
However IPGA gain is reset when PM1-0 bits are “00”. (refer to “Operation of IPGA”
description)
VCOM circuit is powered-down when PM bit is all “0”.
MCLK, BCLK and LRCK should not stopped except the case of PM0 = PM1 = PM2 = PM3 =
PM4 = PM5 = “0” or PDN= “L”.
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
Organization of Power Management bit
1) All Power
PM0: 1
PM1: 1
PM2: 1
PM3: 1
PM4: 1
PM5: 0
2) 2ch REC Mode
PM0: 1
PM1: 0
PM2: 1
PM3: 0
PM4: 0
PM5: 0
3) 2ch REC monitor
PM0: 1
PM1: 0
PM2: 1
PM3: 0
PM4: 0
PM5: 1
PM5
PM1-0
PM3-2
PM4
IPGA0
ALC
ADC0
DAC
IPGA1
ALC
ADC1
PM1-0
PM3-2
PM4
IPGA0
ALC
ADC0
DAC
IPGA1
ALC
ADC1
PM1-0
PM3-2
IPGA0
ALC
ADC0
MUX
AMP
MUX
AMP
PM5
PM1-0
PM3-2
IPGA0
ALC
ADC0
4) 3ch REC Mode
PM0: 0
PM1: 1
PM2: 0
PM3: 1
PM4: 0
PM5: 0
PM1-0
PM3-2
IPGA0
ALC
ADC0
IPGA1 Lch
ALC
ADC1
5) 4ch REC Mode
PM0: 1
PM1: 1
PM2: 1
PM3: 1
PM4: 0
PM5: 0
PM1-0
PM3-2
IPGA0
ALC
ADC0
IPGA1
ALC
ADC1
MUX
AMP
Lch
6) Play
PM0: 0
PM1: 0
PM2: 0
PM3: 0
PM4: 1
PM5: 0
PM4
DAC
7) Analog-Through Mode
PM0: 1
PM1: 0
PM1-0
PM2: 0
IPGA0
PM3: 0
ALC
PM4: 0
PM5: 1
MUX
AMP
PM5
MUX
AMP
Figure 15. Power Management
MS0067-E-02
2004/12
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ASAHI KASEI
Addr
02H
Register Name
Mode Control
R/W
RESET
[AK4563A]
D7
0
D6
0
D5
0
D4
FS
0
0
0
1
D3
DIF1
D2
DIF0
D1
DEM1
D0
DEM0
0
0
0
1
R/W
DEM1-0: Select De-emphasis frequency
The AK4563A includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. The filter
corresponds to three sampling frequencies (32kHz, 44,1kHz and 48kHz). The de-emphasis filter
selected by DEM0 and DEM0 bits are enabled for input audio data.
DEM1
DEM0
Mode
0
0
44.1kHz
RESET
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 4. Select De-emphasis frequency
DIF1-0: Select Audio Serial Interface Format (AK4516A compatible)
No.
DIF1
DIF0 SDTO0/SDTO1(ADC)
SDTI(DAC)
0
0
0
MSB justified
LSB justified
1
0
1
LSB justified
LSB justified
2
1
0
MSB justified
MSB justified
3
1
1
I2S compatible
I2S compatible
Table 5. Select Audio Serial Interface Format
BCLK
≥ 32fs
=64fs
≥ 32fs
≥ 32fs
Figure
Figure 9
Figure 10
Figure 11
Figure 12
RESET
FS: Select Sampling Frequency
0:fs=32kHz
1:fs=48kHz (RESET)
FS bit can set limiter period (LTM1-0 bit), recovery period (WTM1-0 bit), zero crossing timeout
(ZTM1-0 bit) and FADEIN/FADEOUT period (FDTM1-0 bit) the same period at fs=32kHz and
48kHz.
MS0067-E-02
2004/12
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ASAHI KASEI
Addr
03H
Register Name
Timer Select
R/W
RESET
[AK4563A]
D7
D6
FDTM1
FDTM0
D5
ZTM1
0
0
0
D4
D3
ZTM0 WTM1
R/W
0
0
D2
WTM0
D1
LTM1
D0
LTM0
0
0
1
LTM1-0: ALC Limiter Period
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is
done by the period specified by LTM1-0 bit.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
LTM1
LTM0
Period
0
0
63µs
RESET
0
1
125µs
1
0
250µs
1
1
500µs
Table 6. ALC Limiter Operation Period
WTM1-0: ALC Recovery Waiting Period
A period of recovery operation when any limiter operation does not during ALC operation.
Recovery operation is done at period set by WTM1-0 bits.
When the input signal level exceeds auto recovery waiting counter reset level set by LMTH bit, the auto
recovery waiting counter is reset.
The waiting timer starts when the input signal level becomes below the auto recovery waiting counter
reset level.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
WTM1
WTM0
Period
RESET
0
0
8ms
0
1
16ms
1
0
64ms
1
1
512ms
Table 7. ALC Recovery Operation Waiting Period
ZTM1-0: Zero crossing timeout at writing operation by µP and ALC recovery operation
When IPGA of each L/R channels do zero crossing or timeout independently, the IPGA value is
changed by µP WRITE operation or ALC recovery operation.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
ZTM1
ZTM0
Period
RESET
0
0
8ms
0
1
16ms
1
0
64ms
1
1
512ms
Table 8. Zero Crossing Timeout
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
FDTM1-0: FADEIN/OUT Period Setting
The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT bits are
set “1”. When IPGA of each L/R channel do zero crossing or timeout independently, the IPGA value is
changed.
These period are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
FDTM1
FDTM0
Period
RESET
0
0
24ms
0
1
32ms
1
0
48ms
1
1
64ms
Table 9. FADEIN/OUT Period
MS0067-E-02
2004/12
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ASAHI KASEI
Addr
04H
[AK4563A]
Register Name
ALC Mode Control 1
R/W
RESET
D7
0
D6
0
D5
D4
LMAT1
LMAT0
D3
FDATT
R/W
0
0
0
0
0
D2
RATT1
D1
RATT0
D0
LMTH
0
0
0
LMTH: Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level
LMTH
ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
0
ADC Input ≥ –4.0dB
-4.0dB > ADC Input ≥ -6.0dB
1
ADC Input ≥ –2.0dB
-2.0dB > ADC Input ≥ -4.0dB
Table 10. Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level
RESET
RATT1-0: ALC Recovery GAIN Step
During the ALC recovery operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 30H, RATT1= “0”, RATT0= “1” are set, IPGA changes to
32H by the auto limiter operation, the input signal level is gained by 1dB (=0.5dB x 2).
When the IPGA value exceeds the reference level (REF6-0), the IPGA value does not increase.
RATT1
RATT0
GAIN Step
0
0
1
0
1
2
1
0
3
1
1
4
Table 11. ALC Recovery GAIN Step
RESET
FDATT: FADEIN/OUT ATT Step
During the FADEIN/OUT operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 30H, FDATT = “1” are set, IPGA changes to 32H (FADEIN)
or 2EH (FADEOUT) by the FADEIN/OUT operation, the input signal level is gained by 1dB(=0.5dB x
2).
When the IPGA value exceeds the reference level (REF6-0) or 00H, the IPGA value does not increase.
FDATT
ATT Step
RESET
0
1
1
2
Table 12. FADEIN/OUT ATT Step
LMAT1-0: ALC Limiter ATT Step
During the ALC limiter operation, when input signal exceeds the ALC limiter detection level set by
LMTH, the number of steps attenuated from current IPGA value is set. For example, when the current
IPGA value is 68H in the state of LMAT1-0 = “11”, it becomes IPGA=64H by the ALC limiter
operation, the input signal level is attenuated by 2dB (=0.5dB x 4).
The ALC limiter period is set by LTM1-0 bits at ZELMN = “1” and ZTM1-0 bits at ZELMN = “0”.
When the attenuation value exceeds IPGA = “00H” (MUTE), it clips to “00”.
LMAT1
LMAT0
ATT Step
0
0
1
0
1
2
1
0
3
1
1
4
Table 13. ALC Limiter ATT Step
MS0067-E-02
RESET
2004/12
- 23 -
ASAHI KASEI
Addr
05H
[AK4563A]
Register Name
ALC Mode Control 2
R/W
RESET
D7
0
D6
REF6
D5
REF5
D4
REF4
D3
REF3
D2
REF2
D1
REF1
D0
REF0
R/W
0
28H
REF6-0: Set the Reference value at ALC Recovery Operation
During the ALC recovery operation, when IPGA value becomes the reference value set by REF6-0, the
gain of the ALC recovery operation exceeds the reference value. The reference value is set commonly as
for Lch and Rch of IPGA0 and IPGA1.
During the ALC recovery operation, if IPGA value exceeds the setting reference value by GAIN operation,
IPGA does not become the larger than the reference value.
For example, when REF6-0 = 30H, RATT = 2 step and IPGA = 2FH, IPGA will become 2FH + 2 step =
31H by the ALC recovery operation, but IPGA value becomes 30H as REF value is 30H.
IPGA should be certainly set to the same value or smaller than REF value before entering ALC mode
(including the FADEIN/OUT operation).
DATA
GAIN(dB)
Step
Level
+6.0
+5.5
+5.0
•
-22.0
-22.5
•
-29.5
-30.0
0.5dB
73
-9.0
-10.0
•
-15.0
-16.0
-31.0
-32.0
•
-37.0
-38.0
1dB
8
-18.0
-20.0
•
-38.0
-40.0
-40.0
-42.0
•
-60.0
-62.0
2dB
12
MIC
LINE
60H
5FH
5EH
•
28H
27H
•
19H
18H
+28.0
+27.5
+27.0
•
+0.0
-0.5
•
-7.5
-8.0
17H
16H
•
11H
10H
0FH
0EH
•
05H
04H
03H
-44.0
-66.0
4dB
3
02H
-48.0
-70.0
01H
-52.0
-74.0
00H
MUTE
MUTE
1
Table 14. Setting Reference Value at ALC Recovery Operation
MS0067-E-02
2004/12
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ASAHI KASEI
Addr
06H
Register Name
[AK4563A]
D7
D6
D5
D4
D3
D2
D1
D0
ZELM
N
FR
STAT
FDIN
FDOUT
ALC
0
RD
0
0
R/W
0
0
Operation Mode
0
0
R/W
RESET
0
0
R/W
0
ALC: ALC Enable Flag
0: ALC Disable (RESET)
1: ALC Enable
FDOUT: FADEOUT Enable Flag
0: FADEOUT Disable (RESET)
1: FADEOUT Enable
FDIN: FADEIN Enable Flag
0: FADEIN Disable (RESET)
1: FADEIN Enable
STAT: Status Flag
0: ALC (including FADEIN and FADEOUT) operation or initializing operation (RESET)
1: Manual Mode
STAT bit is “0” during initializing operation after exiting power-down by PDN pin. After the finish of the
initializing operation, STAT bit becomes “1”.
During the ALC operation, STAT bit becomes “1” after the max “1” ATT/GAIN operation is completed by
internal state.
FR: Select ALC operation Mode
0: The ALC operation corresponds to impulse noise. (RESET)
1: The ALC operation is the same as AK4516A
ZELMN: Enable zero crossing detection at ALC Limiter operation
0: Enable (RESET)
1: Disable
In case of ZELMN = “0”, IPGA of each L/R channel do zero crossing or timeout independently, the IPGA
value is changed by the ALC operation. Zero crossing timeout is the same as the ALC recovery operation. In
case of ZELMN = “1”, the IPGA value is changed immediately.
MS0067-E-02
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ASAHI KASEI
Addr
07H
[AK4563A]
Register Name
Input PGA Control
R/W
RESET
D7
0
D6
IPGA6
D5
IPGA5
0
D4
D3
IPGA4 IPGA3
R/W
28H
D2
IPGA2
D1
IPGA1
D0
IPGA0
IPGA6-0: Input Analog PGA; 97 levels; Commonly Lch and Rch of IPGA0 and IPGA1.
The IPGA value should be the same or smaller than REF value before the ALC1 operation including the
FADEIN/FADEOUT operation.
When IPGA gain is changed, IPGA6-0 bits should be written while PM1-0 bits are not “00” and ALC bit is
“0”. (refer to “Operation of IPGA” description)
GAIN(dB)
DATA
Step
Level
+6.0
+5.5
+5.0
•
-22.0
-22.5
•
-29.5
-30.0
0.5dB
73
-9.0
-10.0
•
-15.0
-16.0
-31.0
-32.0
•
-37.0
-38.0
1dB
8
-18.0
-20.0
•
-38.0
-40.0
-40.0
-42.0
•
-60.0
-62.0
2dB
12
MIC
LINE
60H
5FH
5EH
•
28H
27H
•
19H
18H
+28.0
+27.5
+27.0
•
+0.0
-0.5
•
-7.5
-8.0
17H
16H
•
11H
10H
0FH
0EH
•
05H
04H
03H
02H
01H
00H
-44.0
-66.0
4dB
-48.0
-70.0
-52.0
-74.0
MUTE
MUTE
Table 15. Input Gain Setting
3
1
There is not LINE table in IPGA1
IPGA value is reset at PM1-0 = “00”.
MS0067-E-02
2004/12
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ASAHI KASEI
[AK4563A]
„ Operation of IPGA
[Reading operation]
When the IPGA value is read by µP, the IPGA value is the written value finally. Therefore, the actual value may differ
to the IPGA value which is read by µP.
[Writing operation at ALC Enable]
During the ALC operation including the FADEIN/OUT operation, if the IPGA value is written by uP, the IPGA value
does not reflect the present value.
[Writing operation at ALC Disable]
The zero crossing detection of IPGA is done to L/R channels independently. Zero crossing timeout is set by ZTM1-0
bits.
When the control register is written from µP, the zero crossing counter for L/R channels commonly is reset and its
counter starts. When the signal detects zero crossing or zero crossing timeout, the written value from µP becomes a valid
for the first time.
In case of writing to the control register continually, the control register should be written by an interval more than zero
crossing timeout. If an appointed interval is written, there is possible to the different value the IPGA value of L/R
channels. For example, when the present IPGA value is updated by zero crossing detection in a channel of one side and
other channel is not updated, if the new data is written in IPGA, the updated channel is keeping the last IPGA value and
other channel is updated to a new IPGA value by the last zero crossing counter. Therefore, zero crossing counter does
not reset when the zero crossing detection is waiting.
[IPGA Gain after completing ALC operation]
The IPGA gain changed by ALC operation is not reflected to the IPGA register. Therefore, when completing ALC
operation (ALC bit; “1” Æ “0”), the IPGA register is different from the actual gain of IPGA. The value should be
re-written to the IPGA register in order to set the actual gain of IPGA with a register value.
[Operation of IPGA at power-down by the control register]
Gain of IPGA0 and IPGA1 is reset when PM1-0 bits are “00”, and then IPGA operation starts from the default value
after exiting PM1-0 bits = “00”. When IPGA6-0 bits are read, the register values written by the last write operation are
read out regardless the actual gain.
[Operation of IPGA when the number of IPGA channels is changed]
When the number of IPGA channels is changed, PM1-0 bits should be done via “00”. If PM1-0 bits are not done via
“00”, there is a possibility that gain between IPGA0 and IPGA1 is different. However, powered-up all channels become
the same gain when IPGA value is written at ALC disabled state (ALC bit = “0”) or the ALC Limiter/Recovery
operation is done.
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ASAHI KASEI
Addr
08H
09H
[AK4563A]
Register Name
Lch Peak Hold
Rch Peak Hold
R/W
RESET
D7
PHL7
PHR7
D6
PHL6
PHR6
D5
PHL5
PHR5
D4
PHL4
PHR4
D3
PHL3
PHR3
D2
PHL2
PHR2
D1
PHL1
PHR1
D0
PHL0
PHR0
RD
00H
PHL7-0: Lch Peak Hold (Absolute Value)
PHR7-0: Rch Peak Hold (Absolute Value)
The peak data is output from ADC0, it is held L/R independently.
These registers are reset by reading from µP.
20 x log 10 [(Data) / 256)] < Peak Level [dB] ≤ 20 x log 10 [(Data+1) / 256)]
Data
FFH
FEH
FDH
•
02H
01H
00H
Peak Level
0.0dB ∼ -0.034 dB
-0.034dB ∼ -0.068dB
-0.068dB ∼ -0.102dB
•
-38.62dB ∼ -42.14dB
-42.14dB ∼ -48.16dB
-48.16dB ∼ -∞(infinity)
Table 16. Peak Level
These registers are reset on the following any conditions.
- PDN pin = “L”
- PM2 = PM3 = “0”
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ASAHI KASEI
[AK4563A]
FUNCTION DETAIL
„ ALC Operation
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch in IPGA0 and IPGA1 exceed ALC limiter detection level
(LMTH), IPGA value is attenuated by ALC limiter ATT step (LMAT1-0) automatically. Then the IPGA value is changed
commonly for L/R channels in IPGA0 and IPGA1. Timeout period is set by LTM1-0 bits. The operation for attenuation is
done continuously until the input signal level becomes LMTH or less. After finishing the operation for attenuation, if
ALC bit does not change into “0”, the operation of attenuation repeats when the input signal level exceed LMTH.
When FR bit is “0”, the ALC operation corresponds to the impulse noise in additional to the ALC operation of AK4516A.
Then if the impulse noise is supplied at ZELMN = “0”, the ALC recovery operation becomes the faster period than a set
of ZTM1-0 bits. In case of ZELMN = “1”, it becomes the same period as LTM1-0 bits.
When FR bit is “1”, the ALC operation in AK4563A is the same as AK4516A’s.
[Explanation for ALC operation]
Limiter starts
ATT Level (LMAT1-0)
ATT Level (LMAT1-0)
ATT Level (LMAT1-0)
Limiter Detection Level(LMTH)
(1) 2dB
Recovery Waiting Counter
Reset Level (LMTH)
Limiter Update Period (LTM1-0)
Limiter finish
Figure 16. Disable ALC zero crossing detection (ZELMN = “1”)
(1) When the signal is input between 2dB, the AK4563A does not operate the ALC limiter and recovery.
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ASAHI KASEI
[AK4563A]
(3) Zero crossing timeout (ZTM1-0)
ATT level (LMAT1-0)
Limiter detection level (LMTH)
(1)
(2)
(2)
Recovery waiting counter reset level (LMTH)
(1)
Limiter detection level (LMTH)
ATT level (LMAT1-0)
(3) Zero crossing timeout (ZTM1-0)
Figure 17. In case of continuing the limiter operation (ZELMN = “0”)
(1) When the input level exceeds the ALC limiter detection level, the ALC limiter operation starts. Zero crossing counter
starts at the same time.
(2) Zero crossing detection. When the input signal is detected, the IPGA value is attenuated until the value set by
LMAT1-0 and the ALC limiter operation is finished.
(3) Zero crossing timeout is set by ZTM1-0 bits. But the first zero crossing timeout cycle after starting the limiter
operation may be the short cycle by the state of the last zero crossing counter. (For example, in case of doing the
limiter operation during the recovery operation)
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ASAHI KASEI
[AK4563A]
2. ALC Recovery Operation
The ALC recovery operation waits until a time of setting WTM1-0 bits after completing the ALC limiter. If the input
signal does not exceed “ALC recovery waiting counter reset level (LMTH)”, the ALC recovery operation is done. The
IPGA value increases automatically by this operation up to the set reference level (REF6-0 bits). Then the IPGA value is
set for L/R commonly. The ALC recovery operation is done at a period set by WTM1-0 bits.
When L/R channels in IPGA0 and IPGA1 are detected by zero crossing operation during WTM1-0, the ALC recovery
operation waits until WTM1-0 period and the next recovery operation is done.
During the ALC recovery operation or the recovery waiting, when either input signal level of L/R channels in IPGA0 and
IPGA1 exceed the ALC limiter detection level (LNTH), the ALC recovery operation changes into the ALC limiter
operation immediately
In case of “ALC recovery waiting counter reset level (LMTH) ≤ Input Signal < ALC limiter detection level (LMTH)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. Therefore, in case of “ALC
recovery waiting counter reset level (LMTH) > Input Signal”, the waiting timer of ALC recovery operation starts.
If the impulse noise is supplied at FR = “0”, the ALC recovery operation becomes the faster period than a set of ZTM1-0
and WTM1-0 bits. When FR bit is “1”, the ALC operation in AK4561 is the same as AK4516A’s.
Limiter detection level (LMTH)
Recovery waiting counter
reset level (LMTH)
During recovery counter reset
Zero crossing detect
WTM counter starts
(1)
ZTM counter starts
WTM counter starts
(2)
WTM counter starts
(2)
ZTM counter starts
WTM counter starts
(2)
Figure 18. The transition from the limiter operation to the recovery operation
(1). When the input signal is below the ALC recovery waiting counter reset level, the ALC recovery operation waits the
time set by WTM1-0 bits. If the input signal does not exceed the ALC limiter detection level or the ALC recovery
waiting counter reset level, the ALC recovery operation is done only once.
(2). The IPGA value is changed by the zero crossing operation in ALC recovery operation, but the next counter of the
ALC recovery waiting timer is also starting.
Other:
When a channel of one side enters the limiter operation during the waiting zero crossing, the present ALC recovery
operation stops, according as the small value of IPGA (a channel of waiting zero crossing), the ALC limiter operation is
done.
When both channels are waiting for the next ALC recovery operation, the ALC limiter operation is done from the IPGA
value of a point in time.
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ASAHI KASEI
[AK4563A]
(1) Recovery waiting counter reset level (LMTH) or reference value of recovery operation (REF6-0)
Zero Crossing Detect
Gain Level (RATT1-0)
(2) Zero crossing timeout (ZTM1-0) & Recovery waiting time (WTM1-0)
Figure 19. The ALC Recovery Operation
(1) When the input signal exceeds the ALC recovery waiting counter reset level, the ALC recovery operation stops, the
ALC recovery operation is repeated when input signal level is below “ALC recovery waiting counter reset level
(LMTH)” again. When the IPGA value by repeating the ALC recovery operation reaches the reference level (REF6-0
bits), the ALC recovery operation stops also.
(2) ZTM1-0 bits set zero crossing timeout and WTM1-0 bits sets the ALC recovery operation period. When the ALC
recovery waiting time (WTM1-0 bits) is shorter than zero crossing timeout period of ZTM1-0 bit, the ALC recovery
is operated by the zero crossing timeout period of ZTM1-0 bit. Therefore, in this case the auto recovery operation
period is not constant.
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ASAHI KASEI
[AK4563A]
Does not change the following registers during the ALC operation.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN
Manual-Mode
WR (Power Management Control & Signal Select registers)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT1-0, RATT, LMTH)
WR (REF6-0)
WR (IPGA6-0)
* The value of IPGA should be the
same or smaller than REF’s.
WR (ALC= “1”, ZELMN)
ALC Operation
No
Finish ALC mode?
Yes
WR (ALC= “0”)
RD (STAT)
No
STAT = “1”?
Yes
Finish ALC-Mode and become manual-Mode
Figure 20. Registers set-up sequence at ALC operation
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ASAHI KASEI
[AK4563A]
„ FADEIN Mode
In FADEIN Mode, the IPGA value is increased at the value set by FDATT when FDIN bit changes from “0” to “1”.
The update period can be set by FDTM1-0 bits. The FADEIN Mode is always detected by the zero crossing operation.
This operation is kept over the REF value or until the limiter operation at once. If the limiter operation is done during
FADAIN cycle, the FADEIN operation becomes the ALC operation.
NOTE: When FDIN and FDOUT bits are “1”, FDOUT operation is enabled.
IPGA Output
ALC bit
FDIN bit
(5)
(1) (2)
(3)
(4)
Figure 21. Example for controlling sequence in FADEIN operation
(1) WR (ALC = FDIN = “0”): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written in “0”.
(2) WR (IPGA = “MUTE”): The IPGA output is muted.
(3) WR (ALC = FDIN = “1”): The FADEIN operation starts. The IPGA changes from the MUTE state to the FADEIN
operation.
(4) The FADEIN operation is done until the limiter detection level (LMTH) or the reference level (REF6-0). After
completing the FADEIN operation, the AK4563A becomes the ALC operation.
(5) FADEIN time can be set by FDTM1-0 and FDATT bits
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
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ASAHI KASEI
[AK4563A]
„ FADEOUT Mode
In FADEOUT mode, the present IPGA value is decreased until the MUTE state when FDOUT bit changes from “0” to
“1”. This operation is always detected by the zero crossing operation.
If the large signal is input to the ALC circuit during the FADEOUT operation, the ALC limiter operation is done.
However a total time of the FADEOUT operation is the same time, even if the limiter operation is done. The period of
FADEOUT is set by FDTM1-0 bits, a number of step can be set by FDATT bit.
When FDOUT bit changes into “0” during the FADEOUT operation, the ALC operation start from the preset IPGA
value.
When FDOUT and ALC bits change into “0” at the same time, the FADEOUT operation stops and the IPGA becomes the
value at that time.
NOTE: When FDIN and FDOUT bits are “1”, FDOUT operation is enabled.
IPGA Output
ALC bit
FDOUT bit
(2)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
Figure 22. Example for controlling sequence in FADEOUT operation
(1) WR (FDOUT = “1”): The FADEOUT operation starts. Then ALC bit should be always “1”.
(2) FADEOUT time can be set by FDTM1-0 and FDATT bits.
During the FADEIN operation, the zero crossing timeout period is ignored and becomes the same as the FADEIN
period.
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
(3) The FADEOUT operation is completed. The IPGA value is the MUTE state. If FDOUT bit is keeping “1”, the IPGA
value is keeping the MUTE state.
(4) Analog and digital outputs mutes externally. Then the IPGA value is the MUTE state.
(5) WR (ALC = FDOUT = “0”): Exit the ALC and FADEOUT operations
(6) WR (IPGA): The IPGA value changes the initial value (exiting MUTE state).
(7) WR (ALC = “1”, FDOUT = “0”): The ALC operation restarts. But the ALC bit should not write until completing zero
crossing operation of IPGA.
(8) Release a mute function of analog and digital outputs externally.
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ASAHI KASEI
[AK4563A]
SYSTEM DESIGN
Figure 23 shows the system connection diagram. An evaluation board (AKD4563A) is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
1
LOUT
PDN
28
2
ROUT
CCLK
27
3
INTL1
CSN
26
4
INTR1
CDTI
25
5
INTL0
CDTO
24
6
INTR0
BCLK
23
7
EXTL
MCLK
22
8
EXTR
LRCK
21
9
LIN
SDTI
20
10 RIN
SDTO1
19
11 VCOM
SDTO0
18
12 AGND
VT
17
13 VA
DGND
16
14 VREF
VD
15
AK4563A
Micro
Controller
Audio
Controller
0.1µ
2.2µ +
2.3 ∼ 3.0V
Analog Supply
+
0.1µ 10µ
+
0.1µ
10µ
1.5 ∼ 3.0V
Digital Supply
+
0.1µ
10µ
10
Figure 23. System Connection Diagram
Note:
- AGND and DGND of AK4563A should be distributed separately from the ground of external controller
etc.
- When LOUT/ROUT drives some capacitive load, some resistor should be added in series between
LOUT/ROUT and capacitive load.
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ASAHI KASEI
[AK4563A]
1. Grounding and Power Supply Decoupling
The AK4563A requires careful attention to power supply and grounding arrangements. VA is usually supplied from
analog supply in system and VD is supplied from analog supply in system via a resistor of 10 ohms. Alternatively if VA
and VD are supplied separately, the power up sequence is not taken care. VT is a power supply pin to interface with the
external ICs and is supplied from digital supply in system. AGND and DGND of the AK4563A should be connected to
analog ground plane. System analog ground and digital ground should be connected together near to where the supplies
are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4563A as possible, with the
small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected
to VA with a 0.1µF ceramic capacitor. VCOM is output to 0.45 x VA(typ.) and is a signal ground of this chip. An
electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high
frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from
the VREF and VCOM pins in order to avoid unwanted coupling into the AK4563A.
3. Analog Inputs
The analog inputs are single-ended and the input resistance is 10kΩ (typ) at MIC gain table and 125kΩ (typ) at LINE gain
table. The input signal range scales with the VREF voltage and nominally 0.6 x VREF Vpp centered in the internal
common voltage. Usually the input signal is AC coupled with capacitor. The cut-off frequency is fc = (1/2πRC). The
AK4563A can accept input voltages to (VA-0.1) Vpp. The ADC output data format is 2’s complement. The output code
is 7FFFH(@16bit) for input above a positive full scale and 8000H(@16bit) for input below a negative fill scale. The ideal
code is 0000H(@16bit) with no input signal. The DC offset including ADC own DC offset removed by the internal HPF
([email protected]=48kHz).
The AK4563A samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of
64fs. The AK4563A includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are single-ended and nominally 0.6 x VREF Vpp centered in the internal common voltage. The input
data format is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for
8000H(@16bit). The ideal output is the VCOM voltage for 0000H(@16bit). If the noise generated by the delta-sigma
modulator beyond the audio band would be the problem, the attenuation by external circuit is required.
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of a few mV + VCOM
volrage.
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ASAHI KASEI
[AK4563A]
PACKAGE
28pin VSOP (Unit: mm)
9.8±0.2(* 1)
28
5.6
15
1.15±0.10
+0.10
0.22 -0.05
0.08
0.12 M
0° ∼ 10°
0.5±0.2
0.10±0.05
0.65
+0.10
0.15 - 0.05
14
1
7.6±0.2
*1: Dimension does not include mold flash.
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate (Pb free)
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ASAHI KASEI
[AK4563A]
MARKING
AKM
AK4563AVF
XXXBYYYYC
XXXBYYYYC
data code identifier
XXXB : Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C Alpha character)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
•Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
•AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
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