AK4558 English Datasheet

[AK4558]
AK4558
108dB 216kHz 32Bit  CODEC with PLL
1. General Description
The AK4558 is a low voltage 32bit 216kHz CODEC for high performance battery powered digital audio
subsystems. An internal circuit includes newly developed 32-bit Digital Filter achieving short group delay
and high quality sound. In addition, “OSR-Doubler” technology is newly adopted, making the AK4558
capable of supporting wide range signals and achieving low out-of-band noise while realizing low power
consumption. The AK4558 is ideal for a wide range of applications that demands high sound quality
including Electronic musical instruments and Audio Interfaces. The analog inputs and outputs are
single-ended to minimize pin count and external filtering requirements. The AK4558 is housed in a very
small 28-pin QFN. It is ideal for space-sensitive applications.
2. Features
 Single-ended ADC
- Dynamic Range, S/N: [email protected]=3.3V
- S/(N+D):
[email protected]=3.3V
- Selectable HPF for DC-offset cancel (fc = 1Hz @ fs=48kHz)
- 4-types Digital Filter for High Sound Quality
 Single-ended DAC
- Dynamic Range, S/N: [email protected]=3.3V
- S/(N+D):
[email protected]=3.3V
- Digital de-emphasis for 32kHz, 44.1kHz and 48kHz sampling
- 5-types Digital Filter for High Sound Quality
- Channel Independent Digital Attenuator (256 levels, 0.5dB steps)
 Audio I/F format: MSB First, 2’s Complement
- ADC: 24/32bit MSB justified , 24/32bit I2S compatible or TDM
- DAC: 24/32bit MSB justified, 16/20/24/32bit LSB justified,
24/32bit I2S compatible or TDM
 Input/Output Voltage: ADC = 2.64Vpp @ AVDD=3.3V
DAC = 2.51Vpp @ AVDD=3.3V
 Master/Slave mode
 P I/F: I2C Bus
 Sampling Rate:
(1) PLL Mode
• PLL Slave Mode (LRCK pin): fs = 8kHz  216kHz
• PLL Slave Mode (BICK pin): fs = 8kHz  216kHz
• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz, 54kHz, 88.2kHz, 96kHz, 128kHz, 176.4kHz, 192kHz
(2) External Clock Mode
• Normal Speed: 8kHz to 54kHz
(256fs or 512fs)
8kHz to 48kHz
(384fs or 768fs)
• Double Speed: 54kHz to 108kHz
(256fs)
48kHz to 96kHz
(384fs)
• Quad Speed: 108kHz to 216kHz
(128fs)
96kHz to 192kHz
(192fs)
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 Master Clock:
(1) PLL Mode
• MCKI pin: 27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
• LRCK pin: 1fs
• BICK pin: 32fs, 64fs, 128fs(TDM), 256fs(TDM)
(2) External Clock Mode (MCKI pin)
• Slave mode: 256fs, 384fs, 512fs or 768fs (Normal Speed)
256fs or 384fs
(Double Speed)
128fs or 192fs
(Quad Speed)
• Master mode: 256fs or 512fs
(Normal Speed)
256fs
(Double Speed)
128fs
(Quad Speed)
 Power Supply:
• AVDD = 2.4 to 3.6V (typ. 3.3V)
• TVDD = 1.7 to 3.6V (typ. 1.8V)
 Power Supply Current: 18mA(fs=48kHz)
 Ta = -40 to 105°C
 Package: 28-pin QFN (0.5mm pitch)
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3. Table of Contents
1.
2.
3.
4.
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents ................................................................................................................................ 3
Block Diagram and Functions ............................................................................................................. 5
■ Block Diagram ................................................................................................................................... 5
■ Compatibility with the AK4556 ........................................................................................................... 6
5. Pin Configurations and Functions ....................................................................................................... 7
■ Ordering Guide .................................................................................................................................. 7
■ Pin Layout .......................................................................................................................................... 7
■ Pin Functions ..................................................................................................................................... 8
■ Handling of Unused Pins ................................................................................................................... 9
6. Absolute Maximum Ratings .............................................................................................................. 10
7. Recommended Operating Conditions .............................................................................................. 10
8. Analog Characteristics ...................................................................................................................... 11
9. ADC Filter Characteristics (fs=48kHz) .............................................................................................. 13
10. ADC Filter Characteristics (fs=96kHz) .......................................................................................... 14
11. ADC Filter Characteristics (fs=192kHz) ........................................................................................ 15
12. DAC Filter Characteristics (fs=48kHz) .......................................................................................... 16
13. DAC Filter Characteristics (fs=96kHz) .......................................................................................... 17
14. DAC Filter Characteristics (fs=192kHz) ........................................................................................ 18
15. DC Characteristics ......................................................................................................................... 19
16. Switching Characteristics .............................................................................................................. 20
■ Timing Diagram ............................................................................................................................... 29
17. Functional Descriptions ................................................................................................................. 34
■ Parallel / Serial Mode ...................................................................................................................... 34
■ Master Mode/Slave Mode ................................................................................................................ 34
■ System Clock ................................................................................................................................... 35
■ Parallel Mode (PS pin= “H”) ............................................................................................................ 36
■ Serial Mode (PS pin= “L”) ................................................................................................................ 38
■ PLL Mode (PMPLL bit = “1”) ............................................................................................................ 41
■ PLL Unlock State ............................................................................................................................. 46
■ PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins = “HH”) ............................................................. 46
■ PLL Slave Mode (PMPLL bit = “1”, CKS3-2 pins = “LL” or “LH” or “HL”)........................................ 47
■ De-emphasis Filter .......................................................................................................................... 48
■ Digital HPF ....................................................................................................................................... 48
■ Audio Interface Format .................................................................................................................... 49
■ TDM Cascade Mode ........................................................................................................................ 52
■ ADC/DAC Digital Filter .................................................................................................................... 61
■ Mono/Stereo Switching .................................................................................................................... 61
■ Digital Attenuator ............................................................................................................................. 62
■ Soft Mute Operation......................................................................................................................... 63
■ Out of Band Noise Reduction Filter ................................................................................................. 64
■ DAC Output (LOUT, ROUT pin) ...................................................................................................... 67
■ Control Sequence ............................................................................................................................ 70
■ Serial Control Interface .................................................................................................................... 81
■ Register Map.................................................................................................................................... 84
■ Register Definitions ......................................................................................................................... 84
18. Recommended External Circuits ................................................................................................... 89
■ Parallel Mode ................................................................................................................................... 89
■ Serial Mode ...................................................................................................................................... 90
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19. Package ......................................................................................................................................... 92
■ Materials & Lead Finish ................................................................................................................... 92
■ Marking ............................................................................................................................................ 93
20. Revision History ............................................................................................................................. 93
IMPORTANT NOTICE ............................................................................................................................ 94
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4. Block Diagram and Functions
■ Block Diagram
MCKI
PDN
VCOC
PMPLL
PLL
LRCK
BICK
PMADL
LIN
ADC
HPF
Audio I/F
RIN
ADC
SDTI
HPF
PMADR
CKS3
PMDAL
LOUT
LPF
SCF
SDTO
DAC
DATT
DEM
DAC
DATT
DEM
CKS2
CKS1
CKS0/TDMI
ROUT
LPF
SCF
PMDAR
VCOM
uP I/F(I2C)
LDO:1.8V
LDOE
AVDD VSS1
TVDD
VSS2 VDD18
PMDAL/CAD0
LOPS
PMADL/SCL
PMADR/SDA
PS
PMDAR/CAD1
Figure 1. Block Diagram
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■ Compatibility with the AK4556
Function
fs (max)
HFP Cut-off
HPF Disable
ADC
Input Level
Input Resistance
Init Cycle
S/(N+D)
DR, S/N
DF
SA
SB
GD
DAC
Output Level
Load Resistance
S/(N+D)
DR, S/N
DF
SA
GD
MCKI (Slave)
Audio I/F
ADC
DAC
Volume
Digital Filter Option
PLL
M/S mode
Parallel/Serial mode
Pop Guard
Idd
AVDD
VDD18
TVDD
Package
AK4556
216kHz
1Hz @ fs = 48kHz
Yes
AK4558
216kHz
1Hz @ fs = 48kHz
Yes
0.7 x VA
8k@ fs = 48kHz, 96kHz, 192kHz
4134/fs @ Normal Speed, Slave mode
91dB
103dB
68dB
28kHz
18/fs
0.8 x AVDD
8k@ fs = 48kHz, 96kHz, 192kHz
5200/fs @ Normal Speed, Slave mode
92dB
108dB
85dB
27.8kHz
5/fs
0.7 x VA
5k
90dB
106dB
54dB
21/fs
256/384/512/768fs @ Normal Speed
256/384fs @ Double Speed
128/192fs @ Quad Speed
2
24bit MSB justified / I S
0.76 x AVDD
5k
100dB
108dB
80dB
6.8/fs
256/384/512/768fs @ Normal Speed
256/384fs @ Double Speed
128/192fs @ Quad Speed
24/32bit MSB justified
2
24/32bit I S/TDM
24/32bit MSB justified
16/20/24/32bit LSB justified
2
24/32bit I S/TDM
0.5dB/step
Yes
Yes
Master / Slave
Yes
Yes
18.0mA (AVDD = 3.3V,TVDD=1.8V)
2.4V to 3.6V
1.7V to 1.98V
24bit MSB justified /24bit LSB justified /
2
IS
No
No
No
Master / Slave
No
No
27.5mA (Vdd = 3V)
2.4V to 3.6V
2.4V to 3.6V (Normal/Double Speed)
2.7V to 3.6V (Quad Speed)
20TSSOP
(6.5mm x 6.4mm, 0.65mm Pitch)
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1.7V to 3.6V
28QFN
(5.0mm x 5.0mm, 0.5mm Pitch)
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[AK4558]
5. Pin Configurations and Functions
■ Ordering Guide
-40  +105C
28-pin QFN (0.5mm pitch)
Evaluation Board for the AK4558
AK4558EN
AKD4558
LIN
22
RIN
23
AVDD
24
VSS1
25
VCOM
26
LOUT
ROUT
LDOE
LOPS
PMDAR/CAD1
PMDAL/CAD0
PMADR/SDA
PMADL/SCL
PDN
21
20
19
18
17
16
15
■ Pin Layout
14
VDD18
13
VSS2
12
TVDD
11
MCKI
10
SDTI
27
9
BICK
28
8
SDTO
AK4558
28pin QFN
4
5
CKS2
CKS1
7
3
CKS3
LRCK
2
PS
DMDAT
CKS0/TDMI 6
1
VCOC
Top View
Note 1. The exposed pad on the bottom surface of the package must be connected to VSS.
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■ Pin Functions
No.
Pin Name
I/O
PD State
1
VCOC
O
Hi-z
2
PS
I
Hi-z
3
4
5
CKS3
CKS2
CKS1
I
I
I
Hi-z
Hi-z
Hi-z
CKS0
I
Hi-z
TDMI
I
Hi-z
7
LRCK
I/O
8
SDTO
O
9
BICK
I/O
10
SDTI
I
Hi-z
11
12
13
MCKI
TVDD
VSS2
I
-
Hi-z
-
O
Pulldown
(500ohm)
I
Hi-z
PDN
I
Hi-z
PMADL
I
Hi-z
6
Hi-Z
/L
L
Hi-Z
/L
Function
(PS pin = “H”)
This pin should be connected to VSS.
(PS pin = “L”)
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to VSS, unless PLL Mode 15 used.
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Mode Setting Pin #3
Mode Setting Pin #2
Mode Setting Pin #1
(PS pin = “H”)
Mode Setting Pin #0
(PS pin = “L”)
TDM Data Input Pin
Input/Output Channel Clock Pin
When PDN pin is “L”, LRCK pin outputs “L” in master mode.
LRCK pin outputs “Hi-Z” in slave mode.
Audio Serial Data Output Pin
When PDN pin is “L”, SDTO pin outputs “L”.
Audio Serial Data Clock Pin
When PDN pin is “L”, BICK pin outputs “L” in master mode.
BICK pin outputs “Hi-Z” in slave mode.
Audio Serial Data Input Pin
I
Hi-z
I/O
Hi-z
PMDAL
I
Hi-z
CAD0
I
Hi-z
PMDAR
I
Hi-z
CAD1
I
Hi-z
20
LOPS
I
Hi-z
21
LDOE
I
Hi-z
22
LIN
I
Hi-z
External Master Clock Input Pin
LDO Power Supply/Digital I/F Power Supply Pin
Digital Ground Pin
(LDOE pin = “H”)
LDO Output Pin
This pin must be connected to VSS2 pin with 1F  50% capacitor in series.
(LDOE pin = “L”)
1.8V Power Input Pin
Power-Down & Reset Mode Pin
“L”: Power-down and Reset, “H”: Normal operation
The AK4558 should be reset once by bringing PDN pin = “L”.
(PS pin = “H”)
ADC Lch Power Management Pin
(PS pin = “L”)
Control Data Clock Pin
(PS pin = “H”)
ADC Rch Power Management Pin
(PS pin = “L”)
Control Data Input/Output Pin
(PS pin = “H”)
DAC Lch Power Management Pin
(PS pin = “L”)
Chip Address 0 Pin
(PS pin = “H”)
DAC Rch Power Management Pin
(PS pin = “L”)
Chip Address 1 Pin
(PS pin = “H”)
DAC Output Power Save Mode Control Pin
(PS pin = “L”)
This pin must be connected to VSS2.
LDO Enable Pin
“L”: LDO Disable, “H”: LDO Enable
Lch Analog Input Pin
23
RIN
I
Hi-z
Rch Analog Input Pin
24
AVDD
-
-
14
15
VDD18
16
SCL
PMADR
I
-
Hi-z
17
SDA
18
19
Analog Power Supply Pin
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25
VSS1
-
26
VCOM
O
27
LOUT
O
28
ROUT
O
Pulldown
(400ohm)
Pulldown
(100kohm)
Pulldown
(100kohm)
Analog Ground Pin
Common Voltage Output Pin, 0.5 x AVDD
This pin must be connected to VSS1 pin with 1µF±50% capacitor in series.
Lch Analog Output Pin
Rch Analog Output Pin
Note 2. All input pins except analog input pins (LIN and RIN) must not be allowed to float.
■ Handling of Unused Pins
Unused I/O pins must be connected appropriately.
Classification
Analog
Digital
Pin Name
LOUT, ROUT, LIN, RIN
MCKI, SDTI, CKS0/TDMI, CKS1, LOPS
SDTO
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Setting
Open
Connect to VSS2
Open
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6. Absolute Maximum Ratings
(VSS1=VSS2=0V; Note 3)
Parameter
Symbol
Min.
Max.
Unit
Power
Analog
AVDD
-0.3
6.0
V
Supplies
Digital core
VDD18
-0.3
2.5
V
Digital I/O
TVDD
-0.3
6.0
V
Input Current (Any Pin Except Supplies)
IIN
mA
10
Analog Input Voltage (LIN, RIN pin)
VINA
-0.3
AVDD+0.3
V
Digital Input Voltage (Note 4)
VIND
-0.3
TVDD+0.3
V
Ambient Temperature (power applied) (Note 5)
Ta
-40
105
C
Storage Temperature
Tstg
-65
150
C
Note 3. All voltages with respect to ground. VSS1 and VSS2 must be connected to analog ground.
Note 4. PMDAL/CAD0, PMDAR/CAD1, LOPS, CKS0/TDMI, CKS3, CKS2, CKS1, PMADL/SCL,
PMADR/SDA, SDTI, LRCK, BICK, MCKI, SDA, PS, LDOE and PDN pins. The external pull-up
resistors at the SDA and SCL pins should be connected to (TVDD+0.3) voltage or less.
Note 5. In case that PCB drawing density is more than 100%. The exposed pad on the bottom surface of
the package must be connected to VSS.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1=VSS2=0V; Note 3)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power
Analog
AVDD
2.4
3.3
3.6
V
Supplies
Digital (LDOE pin=“L”)
TVDD
VDD18
1.8
3.6
V
(Note 6)
Digital Core(LDOE pin=“L”)
VDD18
1.7
1.8
1.98
V
Digital (LDOE pin=“H”)
TVDD
2.4
3.3
3.6
Note 3. All voltages with respect to ground. VSS1 and VSS2 must be connected to analog ground.
Note 6. When the LDOE pin = “L” VDD18 must be powered up either at the same time or after TVDD is
powered up. Internal LDO generates 1.8V, when the LDOE pin =“H”. The power-up sequence with
AVDD and TVDD is not critical. The PDN pin should be held “L” prior to when power is applied.
The PDN pin is allowed to be “H” after all power supplies are applied and settled. All power pins of
the AK4558 must be supplied. Do not turn any power supply off independently (neither grounded
nor floating). When using the AK4558 with I²C bus, the power supply of the AK4558 must not be
turned off unless the power supplies of the surrounding device are turned off.
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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8. Analog Characteristics
(Ta=25C; AVDD= TVDD=3.3V; VSS1=VSS2=0V; EXT Slave Mode; fs=48kHz, 96kHz, 192kHz; Signal
Frequency=1kHz; BICK=64fs; Data=32bit, Measurement frequency=20Hz  20kHz at fs=48kHz, 20Hz 
40kHz at fs=96kHz, 20Hz  40kHz at fs=192kHz; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
ADC Analog Input Characteristics:
Resolution
32
bit
2.38
2.64
2.90
Vpp
Input Voltage
(Note 7)
S/(N+D)
fs=48kHz
1dBFS
82
92
dB
BW=20kHz
60dBFS
43
dB
fs=96kHz
1dBFS
81
91
dB
BW=40kHz
60dBFS
40
dB
fs=192kHz
1dBFS
91
dB
BW=40kHz
60dBFS
40
dB
DR
(60dBFS with A-weighted)
100
108
dB
S/N
(A-weighted)
100
108
dB
Input Resistance
7
10
k
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
100
ppm/C
Power Supply Rejection
(Note 11)
50
dB
DAC Analog Output Characteristics:
Resolution
32
bit
2.26
2.51
2.76
Vpp
Output Voltage
(Note 8)
S/(N+D)
fs=48kHz
0dBFS
90
100
dB
BW=20kHz
60dBFS
45
dB
fs=96kHz
0dBFS
88
98
dB
BW=40kHz
60dBFS
42
dB
fs=192kHz
0dBFS
98
dB
BW=40kHz
60dBFS
42
dB
DR
(60dBFS with A-weighted)
100
108
dB
S/N
(A-weighted)
100
108
dB
30
pF
Load Capacitance
(Note 9)
Load Resistance
(Note 10)
5
k
Interchannel Isolation
90
107
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
100
ppm/C
Power Supply Rejection
(Note 11)
50
dB
Note 7. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to AVDD
voltage. Vin = 0.8 x AVDD (Vpp).
Note 8. This value is the full scale (0dB) of the output voltage. Output voltage is proportional to AVDD
voltage. Vout = 0.76 x AVDD (Vpp).
Note 9. When LOUT/ROUT drives some capacitive load, a 220 resistor should be added in series
between LOUT/ROUT and capacitive load. In this case, LOUT/ROUT pins can drive a capacitor
of 400pF.
Note 10. For AC-load
Note 11. VCOM pin is connected to VSS1 pin with 1µF±50% capacitor in series.
When LDOE pin = “L”, PSR is applied to AVDD, VDD18 and TVDD with 1kHz, 50mVpp.
When LDOE pin = “H”, PSR is applied to AVDD and TVDD with 1kHz, 50mVpp.
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Ta=25℃; AVDD=3.3V, TVDD=VDD18=1.8V;
Slave Mode, MCKI=24.576MHz, ADC Single Input / DAC Single Output (LDOE pin= “L” )
Register Setting: TDM1-0 bits = “00”, DIF2-0 bits = “111”, CKS1-0 bits = “10”, DFS1-0 bits = “00”
Output Pin Load: DAC Single-end=4.7kohm, 33pF, LRCK=BICK=SDTO pins=22pF
Parameter
Min.
Typ.
Max.
Unit
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
12.0
16.0
mA
AVDD
fs=48kHz, 96kHz, 192kHz
6.0
9.0
mA
TVDD+VDD18
fs=48kHz
10.0
15.0
mA
fs=96kHz
10.0
15.0
mA
fs=192kHz
Power-down mode
1
100
µA
(PDN pin = “L”) (Note 12)
AVDD+ TVDD+VDD18
Note 12. Powered-down. All digital input pins are held VSS2.
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[AK4558]
9. ADC Filter Characteristics (fs=48kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF
(SLAD bit=“0” ; SDAD bit=“0”)
Passband (Note 13)
0dB/-0.06dB
PB
0
kHz
22.1
kHz
24.4
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
19
ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER
(SLAD bit=“0” ; SDAD bit=“1”)
Passband (Note 13)
0dB/-0.06dB
PB
0
22.1
kHz
24.4
kHz
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5.0
ADC Digital Filter (Decimation LPF): SLOW ROLL-OFF
(SLAD bit=“1” ; SDAD bit=“0”)
0dB/-0.074dB
Passband (Note 13)
PB
0
12.5
kHz
21.9
kHz
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
7.0
1/fs
ADC Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF
(SLAD bit=“1” ; SDAD bit=“1”)
0dB/-0.074dB
Passband (Note 13)
PB
0
12.5
kHz
21.9
kHz
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
1.2
1/fs
GD
Group Delay (Note 14)
GD
5.0
1/fs
ADC Digital Filter (HPF):
Frequency Response
FR
1.0
Hz
3.0dB
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The passband and stopband frequencies scales with fs (sampling frequency).
For example, PB(0dB/-0.06dB) = 0.46 x fs (@fs=48kHz) for ADC block(SHARP ROLL-OFF).
For example, PB(0dB/-0.074dB) = 0.26 x fs (@fs=48kHz) for ADC block(SLOW ROLL-OFF).
Note 14. The calculated delay time by digital filtering. This is the time from the input of an analog signal to
the output of MSB for L channel of SDTO. The error of the delay at audio interface is within
+1[1/fs].
015004500-E-01
2015/04
- 13 -
[AK4558]
10. ADC Filter Characteristics (fs=96kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF
(SLAD bit=“0” ; SDAD bit=“0”)
44.2
Passband (Note 13) 0dB/-0.06dB
0
kHz
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
19
ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER
(SLAD bit=“0” ; SDAD bit=“1”)
Passband (Note 13)
0dB/-0.06dB
0
44.2
kHz
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5.0
ADC Digital Filter (Decimation LPF): SLOW ROLL-OFF
(SLAD bit=“1” ; SDAD bit=“0”)
25
Passband (Note 13) 0dB/-0.074dB
0
kHz
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
7.0
ADC Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER
(SLAD bit=“1” ; SDAD bit=“1”)
Passband (Note 13) 0dB/-0.074dB
0
25
kHz
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
1.2
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5.0
ADC Digital Filter (HPF):
Frequency Response
FR
2.0
Hz
3.0dB
5.0
Hz
(Note 13)
13
Hz
0.1dB
Note 13. The passband and stopband frequencies scales with fs (sampling frequency).
For example, PB(0dB/-0.06dB) = 0.46 x fs (@fs=96kHz) for ADC block(SHARP ROLL-OFF).
For example, PB(0dB/-0.074dB) = 0.26 x fs (@fs=96kHz) for ADC block(SLOW ROLL-OFF).
Note 14. The calculated delay time by digital filtering. This is the time from the input of an analog signal to
the output of MSB for L channel of SDTO. The error of the delay at audio interface is within
+1[1/fs].
015004500-E-01
2015/04
- 14 -
[AK4558]
11. ADC Filter Characteristics (fs=192kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.6 1.98V, 2.4 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF
(SLAD bit=“0” ; SDAD bit=“0”)
0dB/-0.04dB
83.7
Passband (Note 13)
0
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
15
ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER
(SLAD bit=“0” ; SDAD bit=“1”)
Passband (Note 13)
0dB/-0.04dB
0
83.7
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.3
1/fs
GD
Group Delay (Note 14)
GD
1/fs
6.0
ADC Digital Filter (Decimation LPF): SLOW ROLL-OFF
(SLAD bit=“1” ; SDAD bit=“0”)
0dB/-0.1dB
Passband (Note 13)
0
31.1
kHz
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
145.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
8.0
1/fs
ADC Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER
(SLAD bit=“1” ; SDAD bit=“1”)
Passband (Note 13)
0dB/-0.1dB
0
31.1
kHz
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
145.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.6
1/fs
GD
Group Delay (Note 14)
GD
6.0
1/fs
ADC Digital Filter (HPF):
Frequency Response
FR
4.0
Hz
3.0dB
10.0
Hz
(Note 13)
26.0
Hz
0.1dB
Note 13. The passband and stopband frequencies scales with fs (sampling frequency).
For example, PB(0dB/-0.04dB) = 0.436 x fs (@fs=192kHz) for ADC block(SHARP ROLL-OFF).
For example, PB(0dB/-0.1dB) = 0.16 x fs (@fs=192kHz) for ADC block(SLOW ROLL-OFF).
Note 14. The calculated delay time by digital filtering. This is the time from the input of an analog signal to
the output of MSB for L channel of SDTO. The error of the delay at audio interface is within
+1[1/fs].
015004500-E-01
2015/04
- 15 -
[AK4558]
12. DAC Filter Characteristics (fs=48kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF): Sharp roll-off mode(DEM=OFF; SLDA bit=“0”; SDDA bit=“0”)
Passband
(Note 15) ±0.05dB
PB
0
21.8
kHz
24.0
kHz
6.0dB
Stopband
SB
26.2
kHz
Passband Ripple
PR
dB
-0.0032
0.0032
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
27.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 18)
FR
-0.3
0.2
dB
DAC Digital Filter (LPF): Short delay Sharp roll-off mode (DEM=OFF; SLDA bit=“0” ; SDDA
bit=“1”)
Passband
(Note 15) ±0.05dB
PB
0
21.8
kHz
24.0
kHz
6.0dB
Stopband
SB
26.2
kHz
Passband Ripple
PR
dB
-0.0031
0.0031
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
6.8
1/fs
DAC Digital Filter + Analog Filter:
-0.4
0.3
Frequency Response 0 ~ 20.0kHz (Note 18)
FR
dB
DAC Digital Filter (LPF): Slow roll-off mode(DEM=OFF; SLDA bit=“1” ; SDDA bit=“0”)
0
8.8
Passband
(Note 16) ±0.07dB
PB
kHz
kHz
3.0dB
19.7
Stopband
SB
kHz
42.6
Passband Ripple
PR
dB
-0.043
0.043
Stopband Attenuation
SA
dB
73
Group Delay
(Note 17)
GD
7.3
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 18)
FR
-5
0.1
dB
DAC Digital Filter (LPF): Short delay Slow roll-off mode(DEM=OFF; SLDA bit=“1” ; SDDA bit=“1”)
Passband
(Note 16) ±0.07dB
PB
0
12.1
kHz
24.3
kHz
3.0dB
Stopband
SB
41.5
kHz
Passband Ripple
PR
dB
-0.05
0.05
Stopband Attenuation
SA
82
dB
Group Delay
(Note 17)
GD
5.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 20.0kHz (Note 18)
FR
-5
0.1
dB
Note 15. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.454 x fs (@ fs=48kHz).
Note 16. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.204 x fs (@ fs=48kHz).
Note 17. The calculated delay time is resulting from digital filtering. For the DAC, this is the time from the
input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at
audio interface is within +1[1/fs].
Note 18. The reference frequency is 1kHz.
015004500-E-01
2015/04
- 16 -
[AK4558]
13. DAC Filter Characteristics (fs=96kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF): Sharp roll-off mode(DEM=OFF; SLDA bit=“0” ; SDDA bit=“0”)
±0.05dB
PB
0
43.5
kHz
Passband
(Note 15)
48.0
kHz
6.0dB
Stopband
SB
52.5
kHz
Passband Ripple
PR
dB
-0.0032
+0.0032
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
27.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 18)
FR
-0.4
0.3
dB
DAC Digital Filter (LPF): Short delay Sharp roll-off mode (DEM=OFF; SLDA bit=“0” ; SDDA
bit=“1”)
Passband
(Note 15) ±0.05dB
PB
0
43.5
kHz
48.0
kHz
6.0dB
Stopband
SB
52.5
kHz
Passband Ripple
PR
dB
-0.0031
+0.0031
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
6.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 18)
FR
-0.4
0.3
dB
DAC Digital Filter (LPF): Slow roll-off mode (DEM=OFF; SLDA bit=“1” ; SDDA bit=“0”)
0
17.7
Passband
(Note 16) ±0.07dB
PB
kHz
kHz
3.0dB
39.6
Stopband
SB
kHz
85.3
Passband Ripple
PR
dB
-0.043
+0.043
Stopband Attenuation
SA
dB
73
Group Delay
(Note 17)
GD
7.3
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 18)
FR
-4
0.1
dB
DAC Digital Filter (LPF): Short delay Slow roll-off mode(DEM=OFF; SLDA bit=“1” ; SDDA bit=“1”)
Passband
(Note 16) ±0.07dB
PB
0
24.2
kHz
44.6
kHz
3.0dB
Stopband
SB
83.0
kHz
Passband Ripple
PR
dB
-0.05
+0.05
Stopband Attenuation
SA
82
dB
Group Delay
(Note 17)
GD
5.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 40.0kHz (Note 18)
FR
-5
0.1
dB
Note 15. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.454 x fs (@ fs=96kHz).
Note 16. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.204 x fs (@ fs=96kHz).
Note 17. The calculated delay time is resulting from digital filtering. For the DAC, this is the time from the
input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at
audio interface is within +1[1/fs].
Note 18. The reference frequency is 1kHz.
015004500-E-01
2015/04
- 17 -
[AK4558]
14. DAC Filter Characteristics (fs=192kHz)
(Ta= -40  +105C; AVDD =2.4 3.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
Typ.
Max.
DAC Digital Filter (LPF): Sharp roll-off mode(DEM=OFF; SLDA bit=“0” ; SDDA bit=“0”)
±0.05dB
PB
0
87.0
Passband
(Note 15)
96.0
6.0dB
Stopband
SB
105
Passband Ripple
PR
-0.0032
+0.0032
Stopband Attenuation
SA
80
Group Delay
(Note 17)
GD
27.8
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 18)
FR
-1.0
1.0
Unit
kHz
kHz
kHz
dB
dB
1/fs
dB
DAC Digital Filter (LPF): Short delay Sharp roll-off mode (DEM=OFF; SLDA bit=“0” ; SDDA bit=“1”)
Passband
(Note 15)
±0.05dB
6.0dB
PB
0
105
-0.0031
80
-
96.0
-
87.0
+0.0031
-
kHz
kHz
kHz
dB
dB
1/fs
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay
(Note 17)
GD
6.8
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 18)
FR
-1.0
1.0
dB
DAC Digital Filter (LPF): Slow roll-off mode (DEM=OFF; SLDA bit=“1” ; SDDA bit=“0”)
0
35.5
Passband
(Note 16) ±0.07dB
PB
kHz
kHz
3.0dB
79.1
Stopband
SB
kHz
171
Passband Ripple
PR
dB
-0.043
+0.043
Stopband Attenuation
SA
dB
73
Group Delay
(Note 17)
GD
7.3
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 18)
FR
-5.0
0.1
dB
DAC Digital Filter (LPF): Short delay Slow roll-off mode (DEM=OFF; SLDA bit=“1” ; SDDA bit=“1”)
Passband
(Note 16) ±0.07dB
PB
0
48.4
kHz
89.2
kHz
3.0dB
Stopband
SB
165.9
kHz
Passband Ripple
PR
dB
-0.05
+0.05
Stopband Attenuation
SA
82
dB
Group Delay
(Note 17)
GD
5.8
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response 0 ~ 80.0kHz (Note 18)
FR
-5.0
0.1
dB
Note 15. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.454 x fs (@ fs=192kHz).
Note 16. The passband and stopband frequencies scale with fs (sampling frequency).
For example, Passband (0.06dB) = 0.204 x fs (@ fs=192kHz).
Note 17. The calculated delay time is resulting from digital filtering. For the DAC, this is the time from the
input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at
audio interface is within +1[1/fs].
Note 18. The reference frequency is 1kHz.
015004500-E-01
2015/04
- 18 -
[AK4558]
15. DC Characteristics
(Ta= -40  +105C; AVDD=2.43.6V, TVDD=1.7 3.6V)
Parameter
Symbol
Min.
TVDD  3.0V
VIH
80%TVDD
High-Level Input Voltage
(CKS3, CKS2, CKS1, CKS0/TDMI, SDTI, LRCK,
BICK, MCKI, PMADL/SCL, PMADR/SDA,
PMDAL/CAD0, PMDAR/CAD1, PS, LDOE and
PDN pins)
VIL
Low-Level Input Voltage
(CKS3, CKS2, CKS1, CKS0/TDMI, SDTI, LRCK,
BICK, MCKI, PMADL/SCL, PMADR/SDA,
PMDAL/CAD0, PMDAR/CAD1, PS, LDOE and
PDN pins)
TVDD > 3.0V
High-Level Input Voltage
VIH
70%TVDD
(CKS3, CKS2, CKS1, CKS0/TDMI, SDTI, LRCK,
BICK, MCKI, PMADL/SCL, PMADR/SDA,
PMDAL/CAD0, PMDAR/CAD1, PS, LDOE and
PDN pins)
Low-Level Input Voltage
VIL
(CKS3, CKS2, CKS1, CKS0/TDMI, SDTI, LRCK,
BICK, MCKI, PMADL/SCL, PMADR/SDA,
PMDAL/CAD0, PMDAR/CAD1, PS, LDOE and
PDN pins)
High-Level Output Voltage
(SDTO,LRCK,BICK pins:
Iout=-100µA)
VOH
TVDD-0.5
Low-Level Output Voltage
(SDTO, LRCK, BICK pins: Iout= 100µA)
VOL
VOL
(SDA pin, 2.0V  TVDD  3.6V Iout= 3mA)
VOL
(SDA pin, 1.7V  TVDD < 2.0V Iout= 3mA)
Input Leakage Current
Iin
-
015004500-E-01
Typ.
Max.
Unit
-
-
V
-
20%TVDD
V
-
-
V
-
30%TVDD
V
-
-
V
-
0.5
0.4
20%TVDD
10
V
V
V
µA
2015/04
- 19 -
[AK4558]
16. Switching Characteristics
(Ta= -40  +105C; AVDD= 2.4 ~ 3.6V; TVDD=1.7 ~ 3.6V; CL=20pF)
Parameter
Symbol
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fsn, fsd, fsq
Stereo Mode: Duty Cycle
Duty
TDM128 Mode: (Note 19)
2
I S compatible: Pulse Width Low
Min.
Typ.
Max.
Unit
11.2896
0.4/fCLK
0.4/fCLK
-
27
-
MHz
s
s
-
Table 19
50
-
kHz
%
-
s
-
s
tLRCKL
-
MSB or LSB justified: Pulse Width High tLRCKH
-
TDM256 Mode: (Note 19)
2
I S compatible: Pulse Width Low
MSB or LSB justified: Pulse Width High
BICK Output Timing (Table 21)
Period
BCKO1-0 bits = “00”
BCKO1-0 bits = “01”
Duty Cycle
1/(8fsn)
1/(8fsd)
1/(8fsn)
1/(8fsd)
tLRCKL
tLRCKH
-
1/(4fsq)
1/(4fsq)
-
s
s
tBCK
tBCK
-
-
s
s
BCKO1-0 bits = “10”
tBCK
-
-
s
BCKO1-0 bits = “11”
tBCK
-
1/(32fs)
1/(64fs)
1/(128fsn)
1/(128fsd)
1/(256fsn)
-
s
TDM Mode (Note 19)
tBCK
-
1/(256fsn)
1/(256fsd)
1/(128fsq)
-
s
dBCK
-
50
-
%
Note 19. In TDM modes, TVDD=3.0V~3.6V. The AK4558 does not support variable pitch mode.
015004500-E-01
2015/04
- 20 -
[AK4558]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
Normal Speed Mode: 256fs, 512fs
fsn
384fs, 768fs
Double Speed Mode: 256fs
fsd
384fs
Quad Speed Mode: 128fs
fsq
192fs
Stereo mode duty cycle
Duty
TDM128Mode: (Note 19)
2
I S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High tLRCKH
TDM256 Mode: (Note 19)
2
I S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High
tLRCKH
Min.
Typ.
Max.
Unit
8
8
54
48
108
96
45
-
54
48
108
96
216
192
55
1/(128fsq)
1/(128fsq)
-
127/(128fsq)
127/(128fsq)
kHz
kHz
kHz
kHz
kHz
kHz
%
s
s
s
1/(256fsn)
1/(256fsd)
1/(256fsn)
1/(256fsd)
BICK Input Timing
Period
Stereo Mode
PLL3-0 bits = “0011”
PLL3-0 bits = “0010”
tBCK
tBCK
PLL3-0 bits = “0001”
tBCK
PLL3-0 bits = “0000”
TDM128 Mode
PLL3-0 bits = “0001”
TDM256 Mode
PLL3-0 bits = “0000”
Pulse Width Low
Pulse Width High
tBCK
-
tBCK
-
tBCK
tBCKL
tBCKH
015004500-E-01
-
0.4 x tBCK
0.4 x tBCK
-
255/(256fsn)
255/(256fsd)
255/(256fsn)
255/(256fsd)
s
s
1/(32fs)
1/(64fs)
1/(128fsn)
1/(128fsd)
1/(256fsn)
-
s
s
-
s
1/(128fsq)
1/(256fsn)
1/(256fsd)
-
-
s
-
s
s
s
s
2015/04
- 21 -
[AK4558]
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
Normal Speed Mode: 256fs, 512fs
fsn
384fs, 768fs
Double Speed Mode: 256fs
fsd
384fs
Quad Speed Mode: 128fs
fsq
192fs
Stereo Mode: Duty Cycle
Duty
TDM128Mode:
2
I S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High tLRCKH
TDM256 Mode:
2
I S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High tLRCKH
8
8
54
48
108
96
45
-
1/(128fsq)
1/(128fsq)
-
1/(256fsn)
1/(256fsd)
1/(256fsn)
1/(256fsd)
-
54
48
108
96
216
192
55
127/(128fsq)
127/(128fsq)
255/(256fsn)
255/(256fsd)
255/(256fsn)
255/(256fsd)
kHz
kHz
kHz
kHz
kHz
kHz
%
s
s
s
s
s
BICK Input Timing
Period
TDM128 Mode
(Note 19)
tBCK
1/(64fs)
1/(128fsd)
1/(256fsn)
-
TDM256 Mode
(Note 19)
tBCK
-
Stereo Mode
Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
015004500-E-01
0.4 x tBCK
0.4 x tBCK
-
1/(32fsn)
s
1/(128fsq)
1/(256fsn)
1/(256fsd)
-
-
s
-
s
-
s
s
2015/04
- 22 -
[AK4558]
Parameter
External Slave Mode
MCKI Input Timing
External Clock
256fsn:
Pulse Width Low
Pulse Width High
384fsn:
Pulse Width Low
Pulse Width High
512fsn, 256fsd, 128fsq:
Pulse Width Low
Pulse Width High
768fsn, 384fsd, 192fsq:
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
LRCK Input Timing
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode: 256fs, 512fs
384fs, 768fs
Double Speed Mode: 256fs
384fs
Quad Speed Mode: 128fs
192fs
Duty Cycle
TDM256 mode (Note 19) (Note 20)
(TDM1-0 bits = “01”)
LRCK frequency
“H” time
“L” time
TDM256 mode (Note 19) (Note 21)
(TDM1-0 bits = “01”)
LRCK frequency
“H” time
“L” time
TDM128 mode (Note 19) (Note 22)
(TDM1-0 bits = “10”)
LRCK frequency
“H” time
“L” time
Symbol
Min.
Typ.
Max.
Unit
2.048
29
29
3.072
22
22
4.096
15
15
6.144
11
11
0.4/fCLK
0.4/fCLK
-
13.824
18.432
27.648
36.864
-
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
s
s
Duty
8
8
54
48
108
96
45
-
54
48
108
96
216
192
55
kHz
kHz
kHz
kHz
kHz
kHz
%
fsn
tLRH
tLRL
8
1/256fsn
1/256fsn
-
48
-
kHz
ns
ns
fsd
tLRH
tLRL
48
1/256fsd
1/256fsd
-
96
-
kHz
ns
ns
fsq
tLRH
tLRL
96
1/128fsq
1/128fsq
-
192
-
kHz
ns
ns
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
tCLKL
tCLKH
fsn
fsd
fsq
Note 20. The AK4558 should be in Normal Speed mode.
Note 21. The AK4558 should be in Double Speed mode.
Note 22. The AK4558 should be in Quad Speed mode.
015004500-E-01
2015/04
- 23 -
[AK4558]
Parameter
External Master Mode
MCKI Input Timing
External Clock
256fsn:
384fsn:
512fsn, 256fsd, 128fsq:
768fsn, 384fsd, 192fsq:
Pulse Width Low
Pulse Width High
LRCK Output Timing
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode: 256fs, 512fs
384fs, 768fs
Double Speed Mode: 256fs
384fs
Quad Speed Mode: 128fs
192fs
Stereo Mode: Duty Cycle
TDM256 mode
(Note 23)
(TDM1-0 bits = “1X”)
LRCK frequency
I2S compatible: Pulse Width Low
MSB justified: Pulse Width High
TDM256 mode
(Note 24)
(TDM1-0 bits = “1X”)
LRCK frequency
I2S compatible: Pulse Width Low
MSB justified: Pulse Width High
TDM128 mode
(Note 25)
(TDM1-0 bits = “01”)
LRCK frequency
I2S compatible: Pulse Width Low
MSB justified: Pulse Width High
BICK Output Timing (Table 15)
Period
BCKO1-0 bits = “00”
BCKO1-0 bits = “01”
BCKO1-0 bits = “10”
BCKO1-0 bits = “11”
TDM Mode
Symbol
fCLK
fCLK
fCLK
fCLK
tCLKL
tCLKH
fsn
Min.
Typ.
Max.
Unit
2.048
3.072
4.096
6.144
0.4/fCLK
0.4/fCLK
-
13.824
18.432
27.648
36.864
-
MHz
MHz
MHz
MHz
s
s
8
8
54
48
108
96
-
50
54
48
108
96
216
192
-
fsn
8
-
48
kHz
tLRCKL
tLRCKH
-
1/(8fsn)
1/(8fsn)
-
s
s
48
-
96
kHz
-
1/(8fsd)
1/(8fsd)
-
s
s
96
-
192
kHz
tLRCKL
tLRCKH
-
1/(4fsq)
1/(4fsq)
-
s
s
tBCK
tBCK
tBCK
tBCK
-
-
s
s
s
s
tBCK
-
1/(32fs)
1/(64fs)
1/(128fs)
1/(256fsn)
1/(256fsn)
1/(256fsd)
1/(128fsq)
50
-
s
fsd
fsq
Duty
fsd
tLRCKL
tLRCKH
fsq
-
kHz
%
Duty Cycle (Note 26)
dBCK
%
Note 23. The AK4558 should be in Normal Speed mode.
Note 24. The AK4558 should be in Double Speed mode.
Note 25. The AK4558 should be in Quad Speed mode.
Note 26. When MCKI = 256fsn or 256fsd and BICK output frequency is 256fs, or when MCKI =
128fsq and BICK output frequency is 128fs, the Duty of BICK is MCKI pulse width.
015004500-E-01
2015/04
- 24 -
[AK4558]
Parameter
Audio Interface Timing (Slave mode)
Stereo mode (TDM1-0 bits = “00”)
Normal, Double, Quad Speed Mode
(TVDD= 1.7V~3.6V)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 27)
BICK “” to LRCK Edge
(Note 27)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “” to SDTO
SDTI Hold Time
SDTI Setup Time
Normal, Double, Quad Speed Mode
(TVDD= 2.7V~3.6V)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 27)
BICK “” to LRCK Edge
(Note 27)
LRCK to SDTO(MSB) (Except I2S mode)
BICK “” to SDTO
SDTI Hold Time
SDTI Setup Time
Symbol
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
015004500-E-01
Min.
Typ.
Max.
Unit
1/128fsn
1/64fsd
1/32fsq
58
58
58
58
10
10
-
48
48
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/256fsn
1/128fsd
1/64fsq
33
33
33
33
5
5
-
28
28
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/04
- 25 -
[AK4558]
Parameter
Symbol
Min.
Audio Interface Timing (Slave mode)
Stereo mode (TDM1-0 bits = “00”)
TDM256 mode (Normal Speed Mode
(TDM1-0 bits = “1X”)
(Note 23)
tBCK
1/256fsn
BICK Period
tBCKL
33
BICK Pulse Width Low
tBCKH
33
Pulse Width High
tLRB
23
LRCK Edge to BICK “”
(Note 27)
tBLR
23
BICK “” to LRCK Edge
(Note 27)
tBSS
5
SDTO Setup time BICK “”
tBSH
5
SDTO Hold time BICK “”
tSDH
5
SDTI/TDMI Hold Time
tSDS
5
SDTI/TDMI Setup Time
TDM256 mode (Double Speed Mode)
(TDM1-0 bits = “1X”)
(Note 24)
tBCK
1/256fsd
BICK Period
tBCKL
14
BICK Pulse Width Low
tBCKH
14
Pulse Width High
tLRB
14
LRCK Edge to BICK “”
(Note 27)
tBLR
14
BICK “” to LRCK Edge
(Note 27)
tBSS
5
SDTO Setup time BICK “”
tBSH
5
SDTO Hold time BICK “”
tSDH
5
SDTI/TDMI Hold Time
tSDS
5
SDTI/TDMI Setup Time
TDM128 mode (Quad Speed Mode)
(TDM1-0 bits = “01”)
(Note 25)
tBCK
1/128fsq
BICK Period
tBCKL
14
BICK Pulse Width Low
tBCKH
14
Pulse Width High
tLRB
14
LRCK Edge to BICK “”
(Note 27)
tBLR
14
BICK “” to LRCK Edge
(Note 27)
tBSS
5
SDTO Setup time BICK “”
tBSH
5
SDTO Hold time BICK “”
tSDH
5
SDTI/TDMI Hold Time
tSDS
5
SDTI/TDMI Setup Time
Note 27. BICK rising edge must not occur at the same time as LRCK edge.
015004500-E-01
Typ.
Max.
Unit
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/04
- 26 -
[AK4558]
Parameter
Symbol
Audio Interface Timing (Master mode)
Stereo mode (TDM1-0 bits = “00”)
Normal ,Double, Quad Speed Mode
(TVDD= 1.7V~3.6V)
(Note 28)
tMBLR
BICK “” to LRCK
tLRS
LRCK to SDTO(MSB) (Except I2S mode)
tBSD
BICK “” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
Normal, Double, Quad Speed Mode
(TVDD= 2.7V~3.6V)
(Note 29)
tMBLR
BICK “” to LRCK
tLRS
LRCK to SDTO(MSB) (Except I2S mode)
tBSD
BICK “” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
TDM256 mode, TDM128 mode
(TDM1-0 bits = “01”, “10”)
BICK “” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold time BICK “”
tSDH
SDTI/TDMI Hold Time
tSDS
SDTI/TDMI Setup Time
Note 28. When BICK output frequency ≦6.912MHz.
Note 29. When BICK output frequency >6.912MHz.
015004500-E-01
Min.
Typ.
Max.
Unit
14
38
52
20
20
-
14
38
52
-
ns
ns
ns
ns
ns
7
20
27
9
9
-
7
20
27
-
ns
ns
ns
ns
ns
6
5
5
5
5
-
6
-
ns
ns
ns
ns
ns
2015/04
- 27 -
[AK4558]
Parameter
Symbol
Min.
Typ.
Max. Unit
Control Interface Timing (I2C Bus):
kHz
fSCL
400
SCL Clock Frequency
s
tBUF
1.3
Bus Free Time Between Transmissions
s
tHD:STA
0.6
Start Condition Hold Time (prior to first clock pulse)
s
tLOW
1.3
Clock Low Time
s
tHIGH
0.6
Clock High Time
s
tSU:STA
0.6
Setup Time for Repeated Start Condition
s
tHD:DAT
0
SDA Hold Time from SCL Falling
(Note 30)
s
tSU:DAT
0.1
SDA Setup Time from SCL Rising
s
tR
1.0
Rise Time of Both SDA and SCL Lines
s
tF
0.3
Fall Time of Both SDA and SCL Lines
s
tSU:STO
0.6
Setup Time for Stop Condition
ns
tSP
0
50
Pulse Width of Spike Noise Suppressed by Input Filter
pF
Cb
400
Capacitive load on bus
Power-down & Reset Timing
tAPD
150
ns
PDN Accept Pulse Width
(Note 31)
tRPD
30
ns
PDN Reject Pulse Width
tPDV
5200
1/fs
PDN “” to SDTO valid
(Note 32)
Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 31. The AK4558 can be reset by setting the PDN pin to “L” upon power-up.
The PDN pin must held “L” for more than 150ns for a certain reset. The AK4558 is not reset by
the “L” pulse less than 30ns.
Note 32. This cycle is the numbers of LRCK rising from the PDN pin rising. (Internal power-down is
released in 5ms (max.) after the PDN pin = “H”)
015004500-E-01
2015/04
- 28 -
[AK4558]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tdLRKH
tdLRKL
Duty
= tdLRKH (or tdLRKL) x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing (TDM1-0 bits = “00” & Slave Mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (Except TDM1-0 bits = “00” & Slave Mode)
015004500-E-01
2015/04
- 29 -
[AK4558]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
LRCK
50%TVDD
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/tBCK
50%TVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x tBCK x 100
Figure 4. Clock Timing (TDM1-0 bits = “00” & Master Mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
LRCK
50%TVDD
tLRH
1/tBCK
50%TVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x tBCK x 100
Figure 5. Clock Timing (Except TDM1-0 bits = “00” & Master Mode)
015004500-E-01
2015/04
- 30 -
[AK4558]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (TDM1-0 bits = “00” & Slave Mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSS
tBSH
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
VIH
TDMI
VIL
Figure 7. Audio Interface Timing (Except TDM1-0 bits = “00” & Slave Mode)
015004500-E-01
2015/04
- 31 -
[AK4558]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tLRS
tBSD
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Figure 8. Audio Interface Timing (TDM1-0 bits = “00” & Master Mode)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
tSDS
tSDH
VIH
TDMI
VIL
Figure 9. Audio Interface Timing (Except TDM1-0 bits = “00” & Master Mode)
015004500-E-01
2015/04
- 32 -
[AK4558]
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 10. I2C Bus Mode Timing
PMADL bit, PMADR bit
tPDV
SDTO
50%TVDD
tAPD
tRPD
PDN
VIL
Figure 11. Power-down & Reset Timing
015004500-E-01
2015/04
- 33 -
[AK4558]
17. Functional Descriptions
■ Parallel / Serial Mode
The AK4558 is in parallel control mode (not using I2C bus) by setting the PS pin = “H”. Operation mode in
parallel control mode is selected by the CKS3-0 pins. I2C bus of the AK4458 is available when the PS pin
= “L”. When the AK4558 is in operation, setting of the PS pin cannot be changed.
■ Master Mode/Slave Mode
The CKS3and CKS2 pins select either master or slave mode. When the CKS3 pin = “H” and CKS2 pin =
H”, the AK4558 is in master mode. The AK4558 is in slave mode with all other settings.
CKS3 pin
CKS2 pin
Mode
L
L
Slave Mode
L
H
Slave Mode
H
L
Slave Mode
H
H
Master Mode
Table 1. Select Master/Slave Mode
PDN pin
L
H
CKS3 pin
L
L
H
H
L
L
H
H
CKS2 pin
LRCK pin
L
Input
H
Input
L
Input
H
“L” Output
L
Input
H
Input
L
Input
H
Output
Table 2. LRCK, BICK pin
015004500-E-01
BICK pin
Input
Input
Input
“L” Output
Input
Input
Input
Output
2015/04
- 34 -
[AK4558]
■ System Clock
There are four clock modes to interface with external devices (Table 3, Table 4).
Mode
PMPLL bit CKS3-2 pins PLL3-0 bits
PLL Master Mode
1
“HH”
Table 16
PLL Slave Mode
“LL”
1
Table 16
(PLL Reference Clock: LRCK or BICK pin)
“LH”
EXT Slave Mode
0
“HL”
x
EXT Master Mode
0
“HH”
x
Table 3. Clock Mode Setting (x: Don’t care)
PS pin
Mode
“H”
Parallel
Mode
EXT Slave Mode
Selected by CKS3-0 pins
EXT Master Mode
Selected by CKS3-0 pins
PLL Master Mode
Selected PLL3-0 bits
“L”
Serial
Mode
MCKI pin
PLL Slave Mode
(PLL Reference Clock:
LRCK or BICK pin)
EXT Slave Mode
EXT Master Mode
Connect to VSS2
ACKS bit = “1”
or
ACKS bit = “0” and
DFS1-0 bits
015004500-E-01
Figure 16
Figure 12
Figure 13
BICK pin
Input
( 32fs)
Output
(64fs)
Output
(Selected by
BCKO1-0 bits)
Input
(Selected by
PLL3-0 bits)
LRCK pin
Input
(1fs)
Output
(1fs)
Input
( 32fs)
Input
(1fs)
Output
(Selected by
BCKO1-0 bits)
Table 4. Clock Pin States in Clock Mode
Selected by MCKS1-0
bits and DFS1-0 bits
Figure
Figure 14
Output
(1fs)
Input
(1fs)
Output
(1fs)
2015/04
- 35 -
[AK4558]
■ Parallel Mode (PS pin= “H”)
The external clocks, which are required to operate the AK4558, are MCKI, BICK and LRCK. MCKI should
be synchronized with LRCK but the phase is not critical. MCKI frequencies that corresponds normal
audio rate are shown in Table 5. MCKI frequency, BICK frequency, HPF ON/OFF switching and
Master/Slave mode switching are controlled by the CKS3-0 pins The AK4558 does not support variable
pitch mode when the MCKI is 192fs, 384fs or 768fs (Table 6).
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
N/A
24.576MHz
MCKI
192fs
256fs
384fs
512fs
N/A
8.192MHz
12.288MHz
16.384MHz
N/A
11.2896MHz 16.9344MHz 22.5792MHz
N/A
12.288MHz
18.432MHz
24.576MHz
N/A
24.576MHz
36.864MHz
N/A
36.864MHz
N/A
N/A
N/A
Table 5. System Clock Example (N/A: Not Available)
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
N/A
Mode
Sampling Frequency
MCKI
256fs/512fs
8kHz  fs  54kHz
Normal Speed
384fs/768fs
8kHz  fs  48kkHz
256fs
54kHz < fs  108kHz
Double Speed
384fs
48kHz < fs  96kHz
128fs
108kHz < fs  216kHz
Quad Speed
192fs
96kHz < fs  192kHz
Table 6. Sampling Frequency Range
015004500-E-01
2015/04
- 36 -
[AK4558]
Mode
CKS3
pin
CKS2
pin
CKS1
pin
CKS0
pin
HPF
M/S
0
L
L
L
L
ON
Slave
1
L
L
L
H
ON
Slave
2
L
L
H
L
OFF
Slave
3
L
L
H
H
OFF
Slave
4
L
H
L
L
ON
Slave
5
L
H
L
H
ON
Slave
6
L
H
H
L
OFF
Slave
7
L
H
H
H
OFF
Slave
8
H
L
L
L
ON
Slave
9
H
L
L
H
ON
Slave
10
H
L
H
L
OFF
Slave
11
H
L
H
H
OFF
Slave
12
13
14
15
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
ON
ON
ON
ON
Master
Master
Master
Master
MCKI
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256/384/512/768fs
(Normal Speed)
256fs (Double Speed)
512fs (Normal Speed)
128fs (Quad Speed)
256fs (Normal Speed)
Audio
Interface
Format
32bit LJ/RJ
(Mode 5)
Table 23
2
32bit I S
(Mode 7)
Table 23
32bit LJ
(Mode 6)
Table 23
2
32bit I S
(Mode 15)
Table 23
Table 7. Mode Setting
Note 33. When the PS pin = “L”, only Master/Slave mode setting is valid by the CKS3 and CKS2 pins.
015004500-E-01
2015/04
- 37 -
[AK4558]
■ Serial Mode (PS pin= “L”)
EXT Mode (PMPLL bit = “0”)
The external clocks which are required to operate the AK44558 in slave mode are MCKI, LRCK and
BICK. MCKI should be synchronized with LRCK but the phase is not critical. There are two methods to
set MCKI frequency; Manual Setting Mode and Auto Setting Mode. In Manual Setting Mode (ACKS bit=
“0”: Default), the sampling speed is set by DFS0 and DFS1 bits (Table 8). The frequency of MCKI at each
sampling speed is set automatically. (Table 10, Table 11, Table 12). In Auto Setting Mode (ACKS bit=
“1”), as MCKI frequency is detected automatically (Table 13) and the internal master clock attains the
appropriate frequency (Table 14), so it is not necessary to set DFS.
In master mode, only MCKI is required. Master Clock Input Frequency should be set with the MCKS1-0
bits (Table 9), and the sampling speed should be set by the DFS1-0 bits (Table 8). The frequencies and
the duties of the clocks (LRCK, BICK) are not stable immediately after setting MCKS1-0 bits and DFS1-0
bits up. After exiting reset upon power-up in master mode, the AK4558 is in power-down mode until MCKI
is input.
After exiting reset upon power-up in slave mode, the AK4558 is in power-down mode until MCKI, LRCK
and BICK are input.
If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally.
DFS1
DFS0
0
0
1
1
Sampling Speed Mode (fs)
0
Normal Speed Mode
8kHz~54kHz
1
Double Speed Mode
48kHz~108kHz
0
Quad Speed Mode
96kHz~216kHz
1
Quad Speed Mode
96kHz~216kHz
Table 8. Sampling Speed (Manual Setting Mode)
MCKS1
(default)
MCKS0
Normal
Double
Quad Speed
Speed Mode
Speed Mode
Mode
0
0
256fs
256fs
128fs
0
1
384fs
256fs
128fs
1
0
512fs
256fs
128fs
1
1
768fs
256fs
128fs
Table 9. Master Clock Input Frequency Select (Master Mode)
(default)
LRCK
MCKI (MHz)
BICK (MHz)
fs
256fs
384fs
512fs
768fs
64fs
8.0kHz
2.0480
3.0720
4.0960
6.1440
0.5120
32.0kHz
8.1920
12.2880
16.3840
24.5760
2.0480
44.1kHz
11.2896
16.9344
22.5792
33.8688
2.8224
48.0kHz
12.2880
18.4320
24.5760
36.8640
3.0720
Table 10. System Clock Example (Normal Speed Mode @Manual Setting Mode)
015004500-E-01
2015/04
- 38 -
[AK4558]
LRCK
MCKI (MHz)
BICK (MHz)
fs
256fs
64fs
88.2kHz
22.5792
5.6448
96.0kHz
24.5760
6.1440
108.0kHz
27.6480
6.9120
Table 11. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
MCKI (MHz)
BICK (MHz)
fs
128fs
64fs
176.4kHz
22.5792
11.2896
192.0kHz
24.5760
12.2880
216.0kHz
27.6480
13.8240
Table 12. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCKI
Sampling Speed Mode
512fs
768fs
Normal Speed Mode
256fs
384fs
Double Speed Mode
128fs
192fs
Quad Speed Mode
Table 13. Sampling Speed (Auto Setting Mode)
LRCK
fs
8.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
216.0kHz
128fs
22.5792
24.5760
27.6480
192fs
33.8688
36.8640
-
MCKI (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
4.0960
16.3840
22.5792
24.5760
-
768fs
6.1440
24.5760
33.8688
36.8640
-
Sampling
Speed Mode
Normal
Speed Mode
Double
Speed Mode
Quad Speed
Mode
Table 14. System Clock Example (Auto Setting Mode)
Mode
BCKO1 bit
0
1
2
3
0
0
1
1
BICK Output Frequency BICK Output Frequency
(Stereo mode)
(TDM mode)
0
32fsn,32fsd,32fsq
N/A (Note 34)
1
64fsn,64fsd,64fsq
N/A (Note 34)
(default)
0
128fsn, 128fsd
N/A (Note 34)
1
256fsn
256fsn,256fsd,128fsq
Table 15. BICK Output Frequency at Master Mode
BCKO0 bit
Note 34. Mode0, Mode1 and Mode2 can not be used in TDM modes.
015004500-E-01
2015/04
- 39 -
[AK4558]
EXT Slave Mode (PMPLL bit = “0”, CKS3-2 pins = “LL” or “LH” or “HL”)
DSP or P
AK4558
128fs, 256fs, 384fs,
512fs or 768fs
MCKI
MCLK
 32fs or
128fs(TDM128) or
256fs(TDM256)
BICK
LRCK
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 12. EXT Slave Mode
EXT Master Mode (PMPLL bit = “0”, CKS3-2 pins = “HH”)
DSP or P
AK4558
128fs, 256fs, 384fs,
512fs or 768fs
MCKI
BICK
LRCK
MCLK
32fs, 64fs or
128fs(TDM128) or
256fs(TDM256)
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 13. EXT Master Mode
015004500-E-01
2015/04
- 40 -
[AK4558]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is
selected by the PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4558 is supplied stable clocks or
the sampling frequency is changed after PLL is powered-up (PMPLL bit = “0” → “1”), are shown in Table
16. In Mode 15 (LRCK reference), the VCOC pin must be connected to VSS via a 10nF capacitor. In
other modes, the VCOC pin must be connected to VSS directly.
1) PLL Mode Setting
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
0
1
2
3
4
5
6
7
8
10
11
12
13
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
1
0
1
BICK pin
BICK pin
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
256fs
128fs
64fs
32fs
11.2896MHz
12.288MHz
12MHz
24MHz
19.2MHz
13MHz
26MHz
13.5MHz
27MHz
15
1
1
1
1
LRCK pin
1fs
Mode
Connection
of
VCOC pin
C[F]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10n
 50%
PLL Lock
Time
(max)
2ms
2ms
2ms
2ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
(default)
(Note 35)
(Note 36)
40ms
Table 16. Setting of PLL Mode (fs: Sampling Frequency)
Note 35. The AK4558 should be in EXT Master Mode when fs = 22.05kHz or 44.1kHz.
Note 36. The AK4558 should be in EXT Master Mode when fs = 16kHz, 24kHz, 32kHz or 48kHz.
015004500-E-01
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- 41 -
[AK4558]
2) Sampling Frequency Setting in PLL Mode
When the PLL reference clock input is the MCKI pin, the sampling frequency is selected by FS3-0 bits as
defined in Table 17.
Mode FS3 bit FS2 bit FS1 bit
FS0 bit
Sampling Frequency (Note 37)
0
0
0
0
0
8kHz mode
1
0
0
0
1
11.025kHz mode
2
0
0
1
0
12kHz mode
3
0
0
1
1
16kHz mode
4
0
1
0
0
22.05kHz mode
5
0
1
0
1
24kHz mode
(default)
6
0
1
1
0
32kHz mode
7
0
1
1
1
44.1kHz mode
8
1
0
0
0
48kHz mode
9
1
0
0
1
64kHz mode
10
1
0
1
0
88.2 kHz mode
11
1
0
1
1
96 kHz mode
12
1
1
0
0
128 kHz mode
13
1
1
0
1
176.4 kHz mode
14
1
1
1
0
192 kHz mode
15
1
1
1
1
192 kHz mode
Table 17. Setting of Sampling Frequency at PMPLL bit = “1”
Note 37. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL
differs from the sampling frequency of mode name in some combinations of MCKI
frequency(PLL3-0 bits) and sampling frequency (FS3-0 bits). Refer to Table 19 for the details of
sampling frequency. In master mode, LRCK and BICK output frequency correspond to sampling
frequencies shown in Table 19.
When the PLL reference clock input is the LRCK pin or the BICK pin, the sampling frequency is selected
by FS3-1 bits as defined in Table 18. When the BICK pin is the PLL reference clock input, the sampling
frequency generated by PLL is the same sampling frequency of mode name.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
0
0
0
x
8kHz  fs  13.5kHz
0
0
x
1
1
12kHz < fs  27kHz
0
1
x
2
0
(default)
24kHz < fs  54kHz
0
1
x
3
1
48kHz < fs  108kHz
1
0
x
4
0
96kHz < fs  216kHz
Others Others
N/A
Table 18. Setting of Sampling Frequency at PLL3-2 bits = “00” or PLL3-0 bits = “1111”, and PMPLL bit =
“1” in PLL Slave Mode (PLL Mode 0-3: BICK Reference, Mode15: LRCK Reference)
(PLL Reference Clock: LRCK or BICK pin), (x: Do not care, N/A: Not Available)
015004500-E-01
2015/04
- 42 -
[AK4558]
Input Frequency
MCKI[MHz]
11.2896
12.288
12
Sampling Frequency
Mode
8kHz mode
12kHz mode
16kHz mode
24kHz mode
32kHz mode
48kHz mode
64kHz mode
96kHz mode
128kHz mode
192kHz mode
11.025kHz mode
22.05kHz mode
44.1kHz mode
88.2kHz mode
176.4kHz mode
8kHz mode
12kHz mode
16kHz mode
24kHz mode
32kHz mode
48kHz mode
64kHz mode
128kHz mode
96kHz mode
192kHz mode
11.025kHz mode
22.05kHz mode
44.1kHz mode
88.2kHz mode
176.4kHz mode
8kHz mode
12kHz mode
16kHz mode
24kHz mode
32kHz mode
48kHz mode
64kHz mode
96kHz mode
128kHz mode
192kHz mode
11.025kHz mode
22.05kHz mode
44.1kHz mode
88.2kHz mode
176.4kHz mode
015004500-E-01
Sampling Frequency
generated by PLL [kHz](Note 19)
8.000000
12.000000
16.000000
24.000000
32.000000
48.000000
64.000000
96.000000
128.000000
192.000000
11.025000
22.050000
44.100000
88.200000
176.400000
8.000000
12.000000
16.000000
24.000000
32.000000
48.000000
64.000000
128.000000
96.000000
192.000000
11.025000
22.050000
44.100000
88.200000
176.400000
8.000000
12.000000
16.000000
24.000000
32.000000
48.000000
64.000000
96.000000
128.000000
192.000000
11.024877
22.049753
44.099507
88.199013
176.398026
2015/04
- 43 -
[AK4558]
24
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
64kHz mode
64.000000
96kHz mode
96.000000
128kHz mode
128.000000
192kHz mode
192.000000
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
88.2kHz mode
88.199013
176.4kHz mode
176.398026
Sampling frequency that differs from sampling frequency of mode
name
Input Frequency
MCKI[MHz]
19.2
13
Sampling Frequency
Mode
8kHz mode
12kHz mode
16kHz mode
24kHz mode
32kHz mode
48kHz mode
64kHz mode
96kHz mode
128kHz mode
192kHz mode
11.025kHz mode
22.05kHz mode
44.1kHz mode
88.2kHz mode
176.4kHz mode
8kHz mode
12kHz mode
16kHz mode
24kHz mode
32kHz mode
48kHz mode
64kHz mode
96kHz mode
128kHz mode
192kHz mode
11.025kHz mode
22.05kHz mode
44.1kHz mode
88.2kHz mode
176.4kHz mode
015004500-E-01
Sampling Frequency
generated by PLL [kHz](Note 38)
8.000000
12.000000
16.000000
24.000000
32.000000
48.000000
64.000000
96.000000
128.000000
192.000000
11.025000
22.050000
44.100000
88.200000
176.400000
7.999786
11.999679
15.999572
23.999358
31.999144
47.998716
63.998288
95.997432
127.996575
191.994863
11.024877
22.049753
44.099507
88.199013
176.398026
2015/04
- 44 -
[AK4558]
26
8kHz mode
7.999786
12kHz mode
11.999679
16kHz mode
15.999572
24kHz mode
23.999358
32kHz mode
31.999144
48kHz mode
47.998716
64kHz mode
63.998288
96kHz mode
95.997432
128kHz mode
127.996575
192kHz mode
191.994863
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
88.2kHz mode
88.199013
176.4kHz mode
176.398026
13.5
8kHz mode
8.000300
12kHz mode
12.000451
16kHz mode
16.000601
24kHz mode
24.000901
32kHz mode
32.001202
48kHz mode
48.001803
64kHz mode
64.002404
96kHz mode
96.003606
128kHz mode
128.004808
192kHz mode
192.007212
11.025kHz mode
11.025218
22.05kHz mode
22.050436
44.1kHz mode
44.100871
88.2kHz mode
88.201742
176.4kHz mode
176.403485
27
8kHz mode
8.000300
12kHz mode
12.000451
16kHz mode
16.000601
24kHz mode
24.000901
32kHz mode
32.001202
48kHz mode
48.001803
64kHz mode
64.002404
96kHz mode
96.003606
128kHz mode
128.004808
192kHz mode
192.007212
11.025kHz mode
11.025218
22.05kHz mode
22.050436
44.1kHz mode
44.100871
88.2kHz mode
88.201742
176.4kHz mode
176.403485
Sampling frequency that differs from sampling frequency of mode name
Note 38. These are rounded off to six decimal places.
Table 19. Sampling Frequency at PLL mode (Reference clock is MCKI)
015004500-E-01
2015/04
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[AK4558]
■ PLL Unlock State
PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins = “HH”)
In this mode, LRCK and BICK pins output “L” until the PLL goes to lock state after PMPLL bit = “0” → “1”.
(Table 20).
After PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs.
To avoid invalid outputs of BICK and LRCK pins, set PMPLL bit = “0” once when changing sampling
frequency. It enables to output “L” signal without invalid clocks.
PLL State
BICK pin
LRCK pin
After PMPLL bit “0” → “1”
“L” Output
“L” Output
PLL Unlock (except the case above)
Invalid
Invalid
PLL Lock
Table 21
1fs Output
Table 20. Clock Operation at PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins =”HH”)
■ PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins = “HH”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 19MHz, 24MHz, 26MHz or
27MHz) is input to the MCKI pin, the internal PLL circuit generates BICK and LRCK clocks. The BICK
output frequency is selected from 32fs, 64fs, 128fs and 256fs by BCKO1-0 bits (Table 21).
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or P
AK4558
MCKI
BICK
LRCK
32fs, 64fs or
128fs(TDM128),
256fs(TDM256)
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Master Mode
Mode
0
1
2
3
BICK Output Frequency
(Stereo mode)
BICK Output Frequency
(TDM mode)
0
0
32fsn,32fsd,32fsq
N/A (Note 39)
0
1
64fsn,64fsd,64fsq
N/A (Note 39)
1
0
128fsn, 128fsd
N/A (Note 39)
1
1
256fsn
256fsn,256fsd,128fsq
Table 21. BICK Output Frequency at Master Mode (N/A: Not Available)
BCKO1 bit
BCKO0 bit
(default)
Note 39. Mode0, Mode1 and Mode2 cannot be used in TDM modes.
015004500-E-01
2015/04
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[AK4558]
■ PLL Slave Mode (PMPLL bit = “1”, CKS3-2 pins = “LL” or “LH” or “HL”)
A reference clock of PLL is selected among the input clocks to the BICK pin or the LRCK pin. The
required clock for the AK4558 is generated by an internal PLL circuit. Input frequency is selected by
PLL3-0 bits (Table 16).
a) PLL Reference Clock: BICK pin
The required clock for the AK4558 is generated by an internal PLL circuit with the BICK input clock. PLL
reference clock is selected by PLL3-0 bits. BICK and LRCK inputs must be synchronized. 8kHz ~ 216kHz
sampling frequency is supported and it can be set by FS3-0 bits (Table 17).
AK4558
DSP or P
MCKI
BICK
LRCK
32fs, 64fs or
128fs(TDM128) or
256fs(TDM256)
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15. PLL Slave Mode 1 (PLL Reference Clock: BICK pin)
b) PLL Reference Clock: LRCK pin
The required clock for the AK4558 is generated by an internal PLL circuit with the LRCK input clock. Set
PLL3-0 bits = “1111”. BICK and LRCK inputs must be synchronized. 8kHz ~ 216kHz sampling frequency
is supported and it can be set by FS3-0 bits (Table 17).
AK4558
DSP or P
MCKI
BICK
LRCK
32fs, 64fs or
128fs(TDM128) or
256fs(TDM256)
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
015004500-E-01
2015/04
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[AK4558]
■ De-emphasis Filter
DEM1-0 bits control a digital de-emphasis filter for DAC (SDTI) inputs. This filter (tc=50/15s) is
composed by IIR filter and corresponds to three frequencies (32kHz, 44.1kHz, 48kHz). It is always OFF
in double and quad speed modes.
Mode
0
1
2
3
4
5
Sampling Speed Mode
DEM1
DEM0
DEM
Normal Speed Mode
0
0
44.1kHz
Normal Speed Mode
0
1
OFF
Normal Speed Mode
1
0
48kHz
Normal Speed Mode
1
1
32kHz
Double Speed Mode
Don’t Care Don’t Care
OFF
Quad Speed Mode
Don’t Care Don’t Care
OFF
Table 22. De-emphasis Filter Control
(default)
■ Digital HPF
The ADC has a Digital High Pass Filter (HPF) for DC-offset cancellation. The cut-off frequency of the
HPF is 1Hz at fs=48kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling
frequency (fs). The HPF is controlled by CKS3-0 pins (Table 7). If the HPF setting (ON/OFF) is changed
in operation, click noise occurs by changing DC offset. It is recommended to change HPF setting during
power-down state (PDN pin = “L”).
When the PS pin = “L”, L and R channel HPFs can be ON/OFF independently by HPFEL and HPFER
bits, respectively.
015004500-E-01
2015/04
- 48 -
[AK4558]
■ Audio Interface Format
Eight types of data formats are available and selected by setting the DIF2-0 bits (Table 23). In all modes,
the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master
and slave modes. LRCK and BICK are output from the AK4558 in master mode, but must be input to the
AK4558 in slave mode. The SDTO is clocked out on the falling edge (“”) of BICK and the SDTI is latched
on the rising edge (“”) of BICK.
TDM1
bit
TDM0 DIF2 DIF1 DIF0
bit
bit
bit
bit
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0
Mode
3
CKS3-2
pins
00
01
10
SDTO
(ADC)
24bit MSB
justified
(Note 41)
24bit MSB
justified
(Note 41)
24bit MSB
justified
SDTI
(DAC)
BICK
Figure
16bit LSB
justified
≥32fs
Figure 17
20bit LSB
justified
≥40fs
Figure 18
24bit MSB
justified
≥48fs
Figure 19
2
32fs
Figure 20
2
≥48fs
Figure 21
≥48fs
Figure 22
≥64fs
Figure 23
≥64fs
Figure 24
≥64fs
Figure 25
≥32fs
Figure 17
≥40fs
Figure 18
≥48fs
Figure 19
2
32fs
Figure 20
2
≥48fs
Figure 21
≥64fs
Figure 22
≥64fs
Figure 23
≥64fs
Figure 24
≥64fs
Figure 25
16bit I S Compatible
0
0
0
1
1
24bit I S Compatible
4
0
0
1
0
0
5
0
0
1
0
1
6
0
0
1
1
0
7
0
0
1
1
1
8
11
0
0
0
0
0
9
11
0
0
0
0
1
10
11
0
0
0
1
0
24bit MSB
24bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
24bit MSB
16bit LSB
justified
justified
(Note 41)
24bit MSB
20bit LSB
justified
justified
24bit MSB
24bit MSB
justified
justified
16bit I S Compatible
11
11
0
0
0
1
1
24bit I S Compatible
12
11
0
0
1
0
1
13
11
0
0
1
0
1
14
11
0
0
1
1
0
15
11
0
0
1
1
1
24bit MSB
32bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
Table 23. Audio Interface Format (Stereo Mode) (N/A: Not available)
Note 40. Longer BICK than selected bit-length should be input each channel.
Note 41. When BICK is under 48fs, the output bit-length of the SDTO pin is limited by the number of BICK
in half cycle of LRCK.
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[AK4558]
LRCK
0
1
2
16
17
18
24
25
31
0
1
2
16
17
18
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
8
7
Don’t Care
6
0
15 14
8
23 22
7
1
8
7
Don’t Care
0
6
0
15 14
SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 17. Mode 0/8 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
0
19 18
8
Don’t Care
23 22
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 18. Mode 1/9 Timing
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 19. Mode 2/10 Timing
LRCK
0
1
2
3
12
13
14
15
0
1
2
3
12
13
14
15
0
1
29
30
31
BICK(32fs)
SDTO(o)
SDTI(i)
15 14
4
3
2
1
0
15 14
4
3
2
1
0
15 14
4
3
2
1
0
15 14
4
3
2
1
0
16:MSB, 0:LSB
Lch Data
Rch Data
Figure 20. Mode 3/11 Timing (32fs)
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 21. Mode 3/11 Timing (≥48fs)
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0
[AK4558]
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 22. Mode 4/12 Timing
LRCK
0
1
2
3
4
5
26
27
28
29
30
31
0
1
2
3
4
5
26
27
28
29
30
31
0
1
BCLK(64fs)
SDTO(o)
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
31
SDTI(i)
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
31
31:MSB, 0:LSB
Lch Data
Rch Data
Figure 23. Mode 5/13 Timing
LRCK
0
1
2
3
4
5
26
27
28
29
30
31
0
1
2
3
4
5
26
27
28
29
30
31
0
1
BCLK(64fs)
SDTO(o)
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
31
SDTI(i)
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
31
31:MSB, 0:LSB
Lch Data
Rch Data
Figure 24. Mode 6/14 Timing
LRCK
0
1
2
3
4
5
26
27
28
29
30
31
0
1
2
3
4
5
26
27
28
29
30
31
0
1
BCLK(64fs)
SDTO(o)
0
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
SDTI(i)
0
31 30 29 28 27
5
4
3
2
1
0
31 30 29 28 27
5
4
3
2
1
0
31:MSB, 0:LSB
Lch Data
Rch Data
Figure 25. Mode 7/15 Timing
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[AK4558]
■ TDM Cascade Mode
a) ADC
A cascade connection of four AK4558s (max.) is supported in TDM256 mode and two AK4558s (max.) is
supported in TDM128 mode.
(1) TDM256 Mode (Normal or Double speed Mode)
The SDTO pin of device #1, #2, and #3 are connected with the TDMI pin of device #2, #3 and #4,
respectively. It is possible to output 8 channel TDM data from the SDTO pin of device #4 as shown in
Figure 26 and Figure 27.
AK4558 #1
TDMI
MCKI
48kHz, 96kHz
LRCK
256fs
BICK
GND
SDTO
AK4558 #2
TDMI
MCKI
LRCK
BICK
SDTO
AK4558 #3
TDMI
MCKI
LRCK
BICK
SDTO
AK4558 #4
TDMI
MCKI
LRCK
BICK
8ch TDM
SDTO
Figure 26. Cascade TDM256 Connection Diagram
256 BICK
LRCK
BICK(256fs)
#1 SDTO (o)
#4 TDMI (i)
#4 SDTO (o)
31 30
1
0 31 30
1
L#1
R#1
32 BICK
32 BICK
31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1 0 31 30
1
0 31 30
1 0
L#3
R#3
L#2
R#2
L#1
R#1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1 0 31 30
1
0 31 30
31 30
1 0 31 30
1
0 31 30
1
L#4
R#4
L#3
R#3
L#2
R#2
L#1
R#1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
Figure 27. Cascade TDM Timing (Mode 20; TDM256 mode, MSB justified, Slave mode)
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[AK4558]
(2) TDM128 Mode
The SDTO pin of device #1 is connected with the TDMI pin of device #2. It is possible to output 4 channel
TDM data from the SDTO pin of device #2 as shown in Figure 28 and Figure 29.
AK4558 #1
TDMI
MCKI
192kHz
LRCK
128fs
BICK
GND
SDTO
AK4558 #2
TDMI
MCKI
LRCK
BICK
4ch TDM
SDTO
Figure 28. Cascade TDM128 Connection Diagram
128 BICK
LRCK
BICK(128fs)
#1 SDTO(o)
#2 SDTO(o)
31 30 29 28
4
3
2
1 0 31 30 29 28
4
3 2
L#1
R#1
32 BICK
32 BICK
31 30 29 28
4
3
2
1
0 31 30 29 28
4
3 2
1
0
31 30
1
0 31 30 29 28
4
3
2
1
0 31 30 29 28
4
3
L#2
R#2
L#1
R#1
32 BICK
32 BICK
32 BICK
32 BICK
2
1 0 31 30
Figure 29. Cascade TDM Timing (Mode 32; TDM128 mode, MSB justified, Slave mode)
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[AK4558]
b) DAC
(1) TDM256 Mode (Normal, Double Mode)
By setting TDM1-0 bits = “1X” and SDS1-0 bits, eight channel outputs can be supported at maximum.
The SDTI input data of the AK4558 #1, #2, #3 and #4 can be selected as DAC TDM data by SDS1-0 bits
(Table 24). LOUT/ROUT pins of each device output the data set by SDS1-0 bits as shown in Figure 31.
AK4558 #1
256fs
MCKI
48kHz, 96kHz
LRCK
256fs
BICK
8ch TDM
SDTI
CAD1-0
=00H
LOUT
ROUT
AK4558 #2
SDTI
MCKI
LRCK
BICK
CAD1-0
=01H
LOUT
ROUT
AK4558 #3
SDTI
MCKI
LRCK
BICK
CAD1-0
=10H
LOUT
ROUT
AK4558 #4
SDTI
MCKI
LRCK
BICK
CAD1-0
=11H
LOUT
ROUT
Figure 30. Cascade TDM256 Connection Diagram
256 BICK
LRCK
BICK(256fs)
SDTI 1,2,3,4
SDTI#1 (i)
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
0
31 30
L (Data1) R (Data2)
32 BICK
SDTI#2 (i)
32 BICK
31 30
1
0 31 30
1
0
31 30
L (Data3) R (Data4)
31 30
1
0 31 30
1 0
L#1
R#1
32 BICK
32 BICK
32 BICK
31 30
32 BICK
SDTI#3 (i)
31 30
1
0 31 30
1
0
31 30
L (Data5) R (Data6)
32 BICK
SDTI#4 (i)
32 BICK
31 30
1
0 31 30
1 0 31 30
L (Data7) R (Data8)
32 BICK
32 BICK
Figure 31. Cascade TDM Timing (Mode 22; TDM256 mode, MSB justified, Slave mode)
015004500-E-01
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[AK4558]
(2)TDM128 Mode (Quad Mode)
By setting TDM1-0 bits = “01” and SDS1-0 bits, four channel outputs can be supported at maximum. The
SDTI input data of the AK4558 #1 and #2 can be selected as DAC TDM data by SDS1-0 bits (Table 24).
AK4558 #1
256fs
4ch TDM
SDTI
MCKI
48kHz
LRCK CAD1-0
256fs
BICK
=00H
LOUT
ROUT
AK4558 #2
SDTI
MCKI
LRCK CAD1-0
BICK
=01H
LOUT
ROUT
Figure 32. Cascade TDM128 Connection Diagram
128 BICK
LRCK
BICK(128fs)
SDTI 1,2
SDTI#1 (i)
31 30 29 28
4
3 2
1 0 31 30 29 28
4
3 2
1
0 31 30 29 28
4
3 2
1 0 31 30 29 28
4
3 2
DATA1
DATA2
DATA3
DATA4
32 BICK
32 BICK
32 BICK
32 BICK
31 30 29 28
4
3 2
L (Data1)
32 BICK
1 0 31 30 29 28
4
3 2
1
1 0 31 30
31 30
0
R (Data2)
32 BICK
SDTI#2 (i)
31 30 29 28
4
3 2
1
0 31 30 29 28
4
3 2
L (Data3)
R (Data4)
32 BICK
32 BICK
1 0 31 30
Figure 33. Cascade TDM Timing (Mode 32; TDM128 mode, MSB justified, Slave mode)
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- 55 -
[AK4558]
Mode
0
1
2
3
Mode
M/S
SDS1
SDS0
TDM Data
0
0
L(Data1)/R(Data2)
0
1
L(Data3)/R(Data4)
TDM256
1
0
L(Data5)/R(Data6)
1
1
L(Data7)/R(Data8)
Table 24. DAC TDM Data Select (SDS 1-0 bits)
TDM128
-
TDM1
DIF2
DIF1
DIF0
0
0
0
0
0
0
0
1
16
0
0
1
0
17
0
0
1
1
18
0
1
0
0
19
0
1
0
1
20
0
1
1
0
21
0
1
1
1
0
0
1
0
0
1
0
1
22
1
0
1
0
23
1
0
1
1
24
1
1
0
0
25
1
1
0
1
26
1
1
1
0
27
1
1
1
1
1
TDM0
x
SDTO (ADC)
SDTI (DAC)
(default)
BICK
Figure
256fs
Figure 34
256fs
Figure 35
256fs
Figure 36
256fs
Figure 36
256fs
Figure 34
256fs
Figure 35
256fs
Figure 34
256fs
Figure 35
256fs
Figure 36
256fs
Figure 36
256fs
Figure 34
256fs
Figure 35
N/A
N/A
24bit MSB
24bit MSB
justified
justified
2
24bit I S Compatible
24bit MSB
24bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
N/A
N/A
24bit MSB
24bit MSB
justified
justified
2
24bit I S Compatible
24bit MSB
24bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
Table 25. Audio Interface Format (TDM256 Mode) (x: Don’t care, N/A: Not Available)
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- 56 -
[AK4558]
Mode
M/S
TDM1
TDM0
DIF2
DIF1 DIF0
0
0
0
0
0
0
0
1
28
0
0
1
0
29
0
0
1
1
30
0
1
0
0
31
0
1
0
1
32
0
1
1
0
33
0
0
0
1
0
0
1
0
0
1
0
1
34
0
0
1
0
35
0
0
1
1
36
0
1
0
0
37
0
1
0
1
38
0
1
1
0
39
0
1
1
1
0
1
SDTO (ADC)
SDTI (DAC)
BICK
Figure
128fs
Figure 37
128fs
Figure 38
128fs
Figure 39
128fs
Figure 39
128fs
Figure 37
128fs
Figure 38
128fs
Figure 37
128fs
Figure 38
128fs
Figure 39
128fs
Figure 39
128fs
Figure 37
128fs
Figure 38
N/A
N/A
24bit MSB
24bit MSB
justified
justified
2
24bit I S Compatible
24bit MSB
24bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
N/A
N/A
24bit MSB
24bit MSB
justified
justified
2
24bit I S Compatible
24bit MSB
24bit LSB
justified
justified
32bit MSB
32bit LSB
justified
justified
32bit MSB
32bit MSB
justified
justified
2
32bit I S Compatible
Table 26. Audio Interface Format (TDM128 Mode) (N/A: Not available)
256 BICK
LRCK
Mode22 26
LRCK
Mode16 20
BICK (256fs)
SDTI
Mode16 22
SDTI
Mode20 26
SDTO
Mode16 22
SDTO
Mode20 26
23 22
0
31 30
23 22
0
0 31 30
23 22
0
31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
23 22
0 31 30
0
0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0 31 30
Figure 34. Mode 16/20/22/26 Timing (TDM256 mode, MSB justified)
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[AK4558]
256 BICK
LRCK
Mode23 27
LRCK
Mode17 21
BICK (256fs)
SDTI
Mode17 23
23
SDTI
Mode21 27
0
23
0 31 30
SDTO
Mode17 23
23
SDTO
Mode21 27
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0 31
0
23
0 31 30
0 31
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 35. Mode 17/21/23/27 Timing (TDM256 mode, I2S Compatible)
256 BICK
LRCK
Mode24 25
LRCK
Mode18 19
BICK (256fs)
SDTI
Mode18 24
SDTI
Mode19 25
SDTO
Mode18 24
SDTO
Mode19 25
23 22
0
31 30
23 22
0
0 31 30
23 22
0
31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
23
0 31 30
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 36. Mode 18/19/24/25 Timing (TDM256 mode, LSB justified)
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[AK4558]
128 BICK
LRCK
Mode34 38
LRCK
Mode28 32
BICK (128fs)
SDTI
Mode28 34
23 22
SDTI
Mode32 38
0
23 22
31 30
SDTO
Mode28 34
23 22
0 31 30
23 22
SDTO
Mode32 38
0
0
23 22
0 31 30
23 22
31 30
0
0
23 22
0 31 30
23 22
0 31 30
0
0
0 31 30
23 22
0 31 30
0
23 22
0 31 30
0 31 30
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 37. Mode 28/32/34/38 Timing (TDM128 mode, 24bit MSB justified)
128 BICK
LRCK
Mode35 39
LRCK
Mode29 33
BICK (128fs)
SDTI
Mode29 35
23 22
SDTI
Mode33 39
0
0 31 30
SDTO
Mode29 35
0
0 31 30
23 22
SDTO
Mode33 39
23 22
0
0 31 30
23 22
0
23 22
0 31 30
0 31 30
23 22
0
0 31 30
0
23 22
0
0 31
23 22
0 31 30
0
0 31 30
L1
R1
L2
32 BICK
32 BICK
32 BICK
23
23
0 31
R2
32 BICK
2
Figure 38. Mode 29/33/35/39 Timing (TDM128 mode, 24bit I S Compatible)
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[AK4558]
128 BICK
LRCK
Mode36 37
LRCK
Mode30 31
BICK (128fs)
SDTI
Mode30 36
23 22
SDTI
Mode31 37
0
31 30
SDTO
Mode30 36
0
0 31 30
23 22
SDTO
Mode31 37
23 22
0
31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
0 31 30
23 22
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 39. Mode 30/31/36/37 Timing (TDM128 mode, MSB/LSB justified)
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[AK4558]
■ ADC/DAC Digital Filter
The ADC has four kinds of digital filter modes. SDAD and SLAD bits select ADC digital filter mode. The
default setting is SLAD bit = “0”, SDAD bit = “1” (Short delay Sharp Roll-Off Filter).
SLAD bit
0
0
1
1
SDAD bit
0
1
0
1
ADC Filter Mode Setting
Sharp Roll-off Filter
Short delay Sharp Roll-Off Filter
Slow Roll-off Filter
Short delay Slow Roll-off Filter
Table 27. ADC Digital Filter Setting
(default)
The DAC has five kinds of digital filter modes. SSLOW, SDDA and SLDA bits controls digital filter mode.
When SSLOW bit = “1”, the setting of SDDA and SLDA bits is invalid. The default setting is SSLOW bit =
SLDA bit = “0”, SDDA bit = “1” (Short delay Sharp Roll-Off Filter).
When SSLOW bit = “1”, DATT cannot be used. When the PS pin = “H”, DAC digital filter is set to Short
delay Sharp Roll-Off Filter as default.
SSLOW bit
0
0
0
0
1
SLDA bit
0
0
1
1
SDDA bit
0
1
0
1
DAC Filter Mode Setting
Sharp Roll-off Filter
Short delay Sharp Roll-Off Filter
Slow Roll-off Filter
Short delay Slow Roll-off Filter
Super Slow Roll-Off Filter
x
Table 28. DAC Digital Filter Setting (x: Don’t care)
(default)
■ Mono/Stereo Switching
When the PS pin = “L” (“H”), PMADL and PMADR bits(pins) set mono/stereo ADC operation. When
changing ADC operation, PMADL and PMADR bits must be set “0” at first.
PMADL bit
0
0
1
1
PMADR bit
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal Rch Input Signal
Table 29. Mono/Stereo Switching
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■ Digital Attenuator
The AK4558 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of
the DAC can be set by ATL/R 7-0 bits (Table 30). Transition time between set values of ATL/R bits can be
selected by ATS1-0 bits (Table 31). Transition between set values is the soft transition in Mode1/2/3
eliminating switching noise in the transition. Transition between set values is a soft transition of 4080
levels in Mode 0. It takes 4080/fs ([email protected]=48kHz) from 00H to FFH. If the PDN pin goes to “L”, ATL/R
7-0 bit are initialized to FFH. These bits are also set to FFH when RSTN bit = “0”, and fade to their current
value when RSTN bit returns to “1”.
ATL/R
Attenuation Level
7-0 bits
FFH
0dB
(default)
FEH
0.5dB
FDH
1.0dB
FCH
1.5dB
:
:
03H
126.5dB
01H
127.0dB
00H
MUTE ()
Table 30. Attenuation Level of Digital Attenuator
Mode
0
1
2
3
ATS1
0
0
1
1
ATS0
0
1
0
1
ATT speed
4080/fs
2040/fs
510/fs
255/fs
(default)
Table 31. Transition Time Setting of Digital Attenuator (ATS 1-0 bits)
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■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When SMUTEN bit is set “1”, the output signal is
attenuated to - in the cycle set by ATS bit (Table 31) from the current ATT level. When the SMUTEN bit
is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level in
the cycle set by ATS bit. If the soft mute is cancelled before attenuating to - after starting the operation,
attenuation is discontinued and it is returned to ATT level by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
(2)
(4)
Attenuation
-
GD
(3)
GD
LOUT/ROUT
Notes:
(1) The time for input data attenuation to - (Table 31). For example, this time is 4080LRCK cycles
(4080/fs) at ATT_DATA=FFH. ATT transition of the soft-mute is from FFH to 00H
(2) The time for input data recovery to ATT level (Table 31). For example, this time is 4080LRCK
cycles (4080/fs) at ATT-DATA=00H. ATT transition of soft-mute is from 00H to FFH.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to
ATT level by the same cycle.
Figure 40. Soft Mute
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■ Out of Band Noise Reduction Filter
The AK4558 has an out of band noise reduction filter that can change frequency response. This FIR
filter attenuates out of band noise and prevents a degradation of the analog characteristics caused
by a switching regulator, etc. FIRDA2-0 bits set the frequency for noise attenuation. (Table 32)
FIRDA2-0 bits
000
001
010
011
100
101
110
111
FIR filter
FIR filter
Mode
0
1/4*[1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0]
1
1/4*[1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1]
2
1/4*[1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1]
3
1/4*[1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1]
4
1/4*[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1]
5
1/4*[1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1]
6
1/4*[1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1]
7
1/4*[1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1]
Table 32. FIR Filter Setting
(default)
Figure 41. Mode0 FIR Filter
Figure 42. Mode1 FIR Filter
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Figure 43. Mode2 FIR Filter
Figure 44. Mode3 FIR Filter
Figure 45. Mode4 FIR Filter
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Figure 46. Mode5 FIR Filter
Figure 47. Mode6 FIR Filter
Figure 48. Mode7 FIR Filter
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[AK4558]
■ DAC Output (LOUT, ROUT pin)
1. When the PS pin = “L”( “H”), settings by registers(pins) shown below are valid.
LOUT and ROUT pins output VCOM voltage. The load impedance is 5k (min.). When PMDAL/R bits =
LOPS bit = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100k (typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMDAL/R bits when LOPS bit = “0”. In this case, output
signal line should be pulled-down by 20k after AC coupled as Figure 49. Rise/Fall time is 300ms (max.)
when C=1F and RL=10k. When PMDAL/R bits = “1” and LOPS bit = “0”, the DAC output is in normal
operation.
LOPS bit
0
1
LOPS bit
0
1
PMDAL
Mode
LOUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 33. Lch DAC Output Mode Setting
PMDAR
Mode
ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 34. Rch DAC Output Mode Setting
LOUT
ROUT
1F
(default)
(default)
220
20k
Figure 49. External Circuit of DAC Output (in case of using a Pop Noise Reduction Circuit)
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[DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
(2)
(5)
PMDAL/R bits
(1)
(3)
(4)
(6)
LOPS bit
300 ms
300 ms
99%VCOM
LOUT, ROUT pins
Normal Output
1%VCOM
300 ms
300 ms
Figure 50. DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. DAC output enters power-save mode.
(2) Set PMDAL/R bits = “1”. DAC output exits power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) when
C=1F.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMDAL/R bits = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max
300ms) at C=1F.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits power-save
mode.
2. When the PS pin = “H”, settings shown below are valid.
LOUT and ROUT pins output VCOM voltage. The load impedance is 5k (min.). When PMDAL/R pins =
LOPS pin = “L”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100k (typ). When the LOPS pin is “H”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMDAL/R pins. In this case, output signal line should be
pulled-down by 20k after AC coupled as Figure 51. Rise/Fall time is 300ms (max.) when C=1F and
RL=10k. When PMDAL/R pins = “H” and LOPS pin = “L”, the stereo lineout is in normal operation.
LOUT
ROUT
1F
220
20k
Figure 51. External Circuit of DAC Output (in case of using a Pop Noise Reduction Circuit)
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[DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
(2)
(5)
PMDAL/R pins
(1)
(3)
(4)
(6)
LOPS pin
300 ms
300 ms
99%VCOM
LOUT, ROUT pins
Normal Output
300 ms
1%VCOM
300 ms
Figure 52. DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPS pin = “H”. DAC output enters power-save mode.
(2) Set PMDAL/R pin = “H”. DAC output exits power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) when
C=1F.
(3) Set LOPS pin = “L” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS pin = “H”. Stereo line output enters power-save mode.
(5) Set PMDAL/R pin = “L”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max
300ms) at C=1F.
(6) Set LOPS pin = “L” after LOUT and ROUT pins fall down. Stereo line output exits power-save
mode.
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■ Control Sequence
1. Clock Set Up
When the AK4558 is in operation, the clocks must be supplied.
1-1. PLL Master Mode(PS pin=“L”, CKS3-2 pins = “H H”)
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L”  “H”
(1)
PDN pin
(2)
(3)Addr:01H, Data:08H
Addr:03H, Data:38H
Addr:05H, Data:3AH
1ms (min) (LDOE=”L”), 10ms (min) (LDOE=”H”)
Internal PDN
PMPLL bit
(3)
(4)Addr:01H, Data:09H
(Addr:01H, D0)
(4)
MCKI pin
Input
10ms (max)
BICK pin
LRCK pin
BICK and LRCK output
(6)
Output
(5)
Figure 53. Clock Set Up Sequence (1)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (min.) when LDOE pin = “H”, or 1ms (min.)
when LDOE pin = “L”, after the PDN pin “L” → “H”.
(3) DIF2-0, PLL3-0, FS3-0 and BCKO1-0 bits must be set during this period.
(4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source. PLL lock time is 10ms (max). In this period, the AK4558 outputs BICK and LRCK as it is
in EXT, Master mode if a clock is supplied to the MCKI pin during the period (3).
(5) The AK4558 starts outputting the LRCK and BICK clocks after the PLL became stable. Then
normal operation starts.
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1-2. PLL Slave Mode with External Clock (BICK pin, LRCK pin)
(PS pin=“L”, CKS3-2 pins = “L L” or “L H” or “H L”)
Power Supply
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L”  “H”
1ms (min) (LDOE=”L”), 10ms (min) (LDOE=”H”)
Internal PDN
(3)
(3)Addr:01H, Data:04H
Addr:03H, Data:38H
Addr:05H, Data:22H
PMPLL bit
(Addr:01H, D0)
(4)
BICK pin
LRCK pin
Input
BICK…2ms (max)
LRCK…40ms (max)
(4) Addr:01H, Data:05H
Internal Clock
(5)
Figure 54. Clock Set Up Sequence (2)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (min.) when LDOE pin = “H”, or 1ms (min.)
when LDOE pin = “L”, after the PDN pin “L” → “H”. The power-up time of VCOM will be 2ms
(max.) after the PDN pin “L” → “H” if the external capacitor is 1μF±50%.
(3) DIF2-0, PLL3-0, FS3-0 and BCKO1-0 bits must be set during this period.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK or LRCK
pin) is supplied. PLL lock time is 2ms (max) when BICK is a PLL reference clock. PLL lock time is
40ms (max) when LRCK is a PLL reference clock.
(5) Normal operation starts after that the PLL is locked.
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1-3. External Clock Mode (Slave Mode)
(CKS3-2 pins = “L L” or “L H” or “H L”)
Example:
:Audio I/F Format: 32bit I2S (ADC & DAC)
Power Supply
Input MCKI frequency: 256fsn
Sampling Frequency: 44.1kHz
(1)
PDN pin
Internal PDN
(1) Power Supply & PDN pin = “L”  “H”
(2)
1ms (min) (LDOE=”L”), 10ms (min) (LDOE=”H”)
(3)
(4)
MCKI pin
Input
(3)
(PS pin=”L”) Addr:03H, Data:38H
Addr:04H, Data:00H
(PS pin=”H”) CKS3-0 pins= “LHLH” or“LHHH”
(4)
BICK pin
LRCK pin
Input
MCKI, BICK and LRCK input
Figure 55. Clock Set Up Sequence (3)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (min.) when LDOE pin = “H”, or 1ms
(min.) when LDOE pin = “L”, after the PDN pin “L” → “H”. The power-up time of VCOM will be
2ms (max.) after the PDN pin “L” → “H” if the external capacitor is 1μF±50%.
(3) DIF2-0, DFS1-0 and ACKS bits must be set during this period.
(4) Normal operation starts after MCKI, LRCK and BICK are supplied.
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1-4. External Clock Mode (Master Mode)
(CKS3-2 pins = “HH”)
Example:
: Audio I/F Format: 32bit I2S (ADC and DAC)
Input MCKI frequency: 256fsn
Sampling Frequency: 44.1kHz
BCKO: 64fs
(1) Power Supply & PDN pin = “L”  “H”
Power Supply
(3) MCKI input
(1)
PDN pin
Internal PDN
(2)
1ms (max) (LDOE=”L”), 10ms (max) (LDOE=”H”)
(3)
MCKI pin
Input
(4)
(PS pin=”L”) Addr:03H, Data:38H
Addr:04H, Data:00H
Addr:05H, Data:02H
(PS pin=”H”) CKS3-0 pins= “ HHHH”
(4)
BICK pin
LRCK pin
BICK and LRCK output
Output
Figure 56. Clock Set Up Sequence (4)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (1ms)(min.) when LDOE pin= “H”(“L”) after
the PDN pin “L” → “H”. The power-up time of VCOM will be 2ms (max.) after the PDN pin “L”
→ “H” if the external capacitor is 1μF±50%.
(3) Input MCKI.
(4) When PS pin = “L”, set DIF2-0, DFS1-0 MCKS1-0 and BCKO1-0 bits. When PS pin = “H”, set
CKS pin. The AK4558 starts outputting LRCK and BICK.
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2. ADC Output
2-1. PS pin = “L”
Example:
FS3-0 bits
0111
(Addr:05H, D6-3)
PLL Master Mode
Audio I/F Format :32bit I2S
Sampling Frequency: 44.1kHz
Digital filter:
Short delay Sharp Roll-off
0111
(1)
TDM1-0,DIF2-0 bits
(Addr:03H D7-6&D5-3)
SLAD,SDAD bits
(Addr:07H D3&D2)
(1) Addr:05H, Data:3AH
38H
38H
(2) Addr:03H, Data:38H
(2)
0FH
(3) Addr:07H, Data:0FH
0FH
(3)
(4)
(5)
(4) Addr:00H, Data:19H
PMADL/R bits
(Addr:00H, D4-3)
Recording
5200/fs
SDTO pin
State
“L” Output
Initialize
Normal
State
“L” Output
(5) Addr:00H, Data:01H
Figure 57. ADC Output Sequence (PS pin = “L”)
<Sequence>
In the case of fs=44.1kHz
At first, clocks should be supplied according to “Serial Mode”.
(1) Set up the sampling frequency (FS3-0 bits). The ADC must be powered-up in consideration of PLL
lock time.
(2) Set up the audio format (Addr=03H).
(3) Set up the de-emphasis filter (Addr = 07H).
(4) Power up the ADC: PMADL = PMADR bits = “0” → “1”
Initialization cycle of the ADC is 5200/fs @Normal mode. The SDTO pin outputs “L” during
initialization.
(5) Power down ADC: PMADL = PMADR bits = “1” → “0”
2-2. PS pin = “H”
CKS3-0 pins
XXXX
(1)
(2)
PMADL/R pins
5200/fs
SDTO pin
State
“L” Output
Initialize
Normal
State
“L” Output
Figure 58.ADC Output Sequence (PS pin =“H”)
<Sequence>
At first, operation mode should be set by CKS3-0 bits according to “Parallel Mode”.
(1) Power up the ADC: PMADL pin = PMADR pin = “L” → “H”
Initialization cycle of the ADC is 5200/fs @Normal mode. The SDTO pin outputs “L” during
initialization.
(2) Power down ADC: PMADL pin = PMADR pin = “H” → “L”
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3. DAC Output
3-1. PS pin = “L”
Example:
PLL, Master Mode
Audio I/F Format :32bit I2S (DAC)
Digital filter: Short delay Sharp Roll-off
Sampling Frequency:44.1KHz
Digital Volume: 0dB
(1) Addr:05H, Data: 3AH
FS3-0 bits
(Addr 05H,D6-3)
0111
0111
(2) Addr:06H, Data: 09H
(1)
SSLOW
SLDA, SDDA bits
ATL/ATR7-0 bits
(Addr 08H&09H)
(3) Addr:08H/09H, Data: FFH
09H
(Addr 06H, D4-2)
09H
(2)
(4) Addr:05H, Data: 3BH
FFH
FFH
(5) Addr:00H, Data: 07H
(3)
(6) Addr:05H, Data: 3AH
LOPS bit
(Addr 05H,D0)
>300 ms
(4)
(5)
>300 ms
(6)
(7)
Playback
(9)
(8)
PMDAL/R bits
(7) Addr:05H, Data: 3BH
(Addr:00H D2&D1)
<300 ms
LOUT pin
ROUT pin
<300 ms
Normal Output
(8) Addr:00H, Data: 01H
(9) Addr:05H, Data:3AH
Figure 59. DAC Sequence (PS pin =”L”)
<Sequence>
Following is the example when fs=44.1k.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). The DAC must be powered-up in consideration of PLL
lock time.
(2) Set up the digital filter mode.
(3) Set up the digital output volume (Address = 08H, 09H).
(4) Set the DAC output to power-save mode: LOPS bit “0” → “1”
(5) Power up the DAC: PMDAL = PMDAR bits = “0” → “1”
Outputs of the LOUT and ROUT pins start rising. Rise time is 300ms (max.) when C = 1µF.
(6) Release power-save mode of the DAC output: LOPS bit = “1” → “0”
Set LOPS bit to “0” after the LOUT and ROUT pins output “H”. Sound data will be output from the
LOUT and ROUT pins after this setting.
(7) Set the DAC output power-save mode: LOPS bit = “0” → “1”
(8) Power down the DAC: PMDAL = PMDAR bits = “1” → “0”
Outputs of the LOUT and ROUT pins start falling. Fall time is 300ms (max.) when C = 1µF.
(9) Release power-save mode of the DAC output: LOPS bit = “1” → “0”
Set LOPS bit to “0” after outputs of the LOUT and ROUT pins fall to “L”.
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3-2. PS pin = “H”
CKS3-0 pins
XXXX
LOPS pin
>300 ms
(1)
>300 ms
(3)
(2)
(4)
(6)
(5)
PMDAL/R pins
<300 ms
LOUT pin
ROUT pin
<300 ms
Normal Output
Figure 60. DAC Sequence (PS pin = “H”)
<Sequence>
At first, set operation mode by the CKS3-0 pins according to “Parallel Control Mode”.
In parallel mode, digital filter setting is Short delay Sharp Roll-Off Filter mode. Digital filter does not
correspond to PLL and TDM mode.
(1) Set the DAC output to power-save mode: LOPS pin “L” → “H”
(2) Power up the DAC: PMDAL = PMDAR pins = “L” → “H”
Outputs of the LOUT and ROUT pins start rising. Rise time is 300ms (max.) when C = 1µF.
(3) Release power-save mode of the DAC output (LOPS pin = “H” → “L”) after the LOUT and the ROUT
pins are risen up. Then data output is started from the LOUT and the ROUT pins.
(4) Set the DAC output to power-save mode: LOPS pin “L” → “H”
(5) Power down the DAC: PMDAL = PMDAR pins = “H” → “L”
Outputs of the LOUT and the ROUT pins go to low. The maximum fall time is 300 ms when C = 1 uF.
(6) Release power-save mode of the DAC output: LOPS pin = “H” → “L”
Set LOPS pin to “L” after output of the LOUT and ROUT pins fall to “L”.
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4. Reset Function
When RSTN bit= “0” analog and digital blocks of the ADC are powered-down and digital block of DAC is
powered-down, but the internal register are not initialized. The analog outputs go to VCOM voltage, and
SDTO pin outputs “L”.
RSTN bit
1/fs (5)
1/fs (6)
Internal
RSTN bit
(1)
ADC Internal
State
Normal Operation
Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Init Cycle
Normal Operation
Normal Operation
GD (2)
GD
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
(3)
“0”data
“0”data
(2)
GD
DAC Out
(Analog)
Clock In
MCKI,LRCK,BICK
GD
(7)
(7)
(4)
Don’t care
Figure 61. Reset Sequence
Note:
(1) The analog section of the ADC is initialized after exiting reset state.
The initializing cycle is 5200fs in Normal Speed Mode (DFS1-0 bits = “00”), 10000fs in Double
Speed Mode (DFS1-0 bits = “01”) and 19200fs in Quad Speed Mode (DFS1-0 bits “10”). In this
period, the ADC input voltage should be operating common voltage.
(2) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital
inputs have group delay (GD).
(3) The ADC output is “0” data at power-down state.
(4) The DAC output is VCOM voltage at power-down state.
(5) There is a delay, 1/fs from writing RSTN bit = “0” to set the internal RSTN bit = “0”.
(6) There is a delay, 1/fs from writing RSTN bit = “1” to start an initialization cycle.
(7) Click noise occurs at the edges (“ ”) of the internal timing of RSTN. This noise is output even if “0”
data is input. Mute the analog output externally if the click noise (7) adversely affect system
performance.
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5. Stop of Clock
Necessary clocks must be supplied when the AK4558 is in operation.
1. PLL Master Mode
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(1) Addr:01H, Data:00H
(2)
External MCKI
Input
(2) Stop an external MCKI
Figure 62. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1”  “0”
(2) Stop an external master clock.
2. PLL Slave Mode (BICK, LRCK pin)
Example
(1)
:
Audio
I/F Format : 32bit I2S (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
External LRCK
Input
(1) Addr:01H, Data:00H
(2)
(2) Stop the external clocks
Figure 63. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1”  “0”
(2) Stop the external BICK and LRCK clocks
3. EXT Slave Mode
(1)
External MCKI
Input
External BICK
Input
Example
: Audio I/F Format : 32bit I2S (ADC & DAC)
Input MCKI frequency:256fs
(1)
(1) Stop the external clocks
(1)
External LRCK
Input
Figure 64. Clock Stopping Sequence (3)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
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4. EXT Master Mode
(1)
Example
: Audio I/F Format : 32bit I2S (ADC & DAC)
External MCKI
Input
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Input MCKI frequency:256fs
(1) Stop the external MCKI
Figure 65. Clock Stopping Sequence (4)
<Example>
(1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”.
6. System Reset
The AK4558 should be reset once by bringing the PDN pin to “L” upon power-up. Reference voltage such
as VCOM is powered up by the PDN pin, and the internal timing starts as the internal circuit is powered
up on MCKI and LRCK rising edge “”. The ADC and DAC blocks are in power down state until MCKI,
LRCK and BICK are input.
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7. Power down
AVDD/TVDD
(1)
PDN pin
LDOE pin
VDD18 pin
(2)
Internal PDN
Figure 66. Power Down Sequence (LDOE pin= “L”)
AVDD/TVDD
(1)
PDN pin
LDOE pin
(2)
Internal PDN
VDD18 pin
Figure 67. Power Down Sequence (LDOE pin= “H”)
Note:
(1) The PDN pin must be held to “L” for 150 ns after power up AVDD and TVDD.
(2) When the LDOE pin = “L”, the internal shutdown switch is ON after power up the AK4558.
Internal circuit will be powered up after the shutdown switch is ON (1 ms max.). When the LDOE
pin = “H”, the internal LDO is powered up after the AK4558 is powered up. The internal circuit will
be powered up (10 ms max.) after the shutdown switch is ON following internal oscillator
count-up.
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[AK4558]
■ Serial Control Interface
I2C-bus Control Mode (PS pin = “L”)
Functions of the AK4558 are controlled by registers or pins. The register writing is executed via I2C bus.
The chip address is determined by the state of the CAD0 and CAD1 inputs. Setting the PDN pin = “L”
initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing
circuit, but the register values will not be initialized.
* A control register writing is not available when the PDN pin = “L”.
The AK4558 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins
must be connected to the voltage that is equal to or less than (TVDD+03)V.
1. WRITE Operations
Figure 68 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 74). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bit). These bits identify
the specific device on the bus. The hard-wired input pins (CAD1 and CAD0) set these device address bits
(Figure 69). If the slave address matches that of the AK4558, the AK4558 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (Figure 75). A R/W bit value of “1”
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4558. The format is MSB first, and
those most significant 1bit is fixed to zero (Figure 70). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 71). The AK4558 generates an acknowledge after each byte
is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 74).
The AK4558 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4558 generates an acknowledge and awaits the next data. The master can transmit more than
one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each
data packet the internal address counter is incremented by one, and the next data is automatically taken
into the next address. If the address exceeds “09H” prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 76) except for
the START and STOP conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 68. Data Transfer Sequence in I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
Figure 69. The First Byte (CAD1 and CAD0 are set by pin settings)
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0
0
0
A4
A3
A2
A1
A0
D1
D0
Figure 70. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 71. Byte Structure after The Second Byte
1. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4558. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 09H prior to generating stop condition, the address counter will “roll over” to 00H and the data of
00H will be read out.
The AK4558 supports two basic read operations: Current Address Read and Random Address Read.
2-1. Current Address Read
The AK4558 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
Current Read operation would access data from the address “n+1”. After receipt of the slave address with
R/W bit “1”, the AK4558 generates an acknowledge, transmits 1-byte of data to the address set by the
internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4558 ceases the transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
MA
AC
SK
T
E
R
Data(n+2)
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 72. Current Address Read
2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4558 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK4558 ceases the transmission.
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[AK4558]
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
S
T
O
P
R/W="1"
Slave
S Address
A
C
K
Data(n)
Data(n+1)
MA
AC
S K
T
E
R
A
C
K
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 73. Random Address Read
SDA
SCL
S
P
start condition
stop condition
Figure 74. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 75. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 76. Bit Transfer (I2C Bus)
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[AK4558]
■ Register Map
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
PMADR PMADL PMDAR PMDAL
00H Power Management
0
0
0
RSTN
01H PLL Control
0
0
0
PLL3
PLL2
PLL1
PLL0
PMPLL
02H DAC TDM
0
0
0
0
0
0
SDS1
SDS0
SMUTE
03H Control 1
TDM1
TDM0
DIF2
DIF1
DIF0
ATS1
ATS0
MCKS1 MCKS0
04H Control 2
0
0
0
DFS1
DFS0
ACKS
05H Mode Control
0
FS3
FS2
FS1
FS0
BCKO1 BCKO0 LOPS
FIRDA2 FIRDA1 FIRDA0
06H Filter setting
SLDA
SDDA SSLOW DEM1
DEM0
07H HPF Enable, Filter setting
0
0
0
0
SLAD
SDAD HPFER HPFEL
08H LOUT Volume Control
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
09H ROUT Volume Control
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Note 42. Address 0AH and 1FH are a read only register. The bits defined as 0 must contain a “0” value.
When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN
bit goes to “0”, the internal timing is reset, but registers are not initialized to their default values.
■ Register Definitions
Addr
00H
Register Name
Power Management
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
PMADR
R/W
0
D3
PMADL
R/W
0
D2
PMDAR
R/W
0
D1
PMDAL
R/W
0
D0
RSTN
R/W
1
RSTN: Internal Timing Reset
0: Reset Register values are not reset.
1: Normal Operation (default)
PMDAL/R: DAC L/Rch Power Management
0: DAC L/Rch Power Down (default)
1: Normal Operation
PMADL/R: ADC L/Rch Power Management
0: ADC L/Rch Power Down (default)
1: Normal Operation
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
PLL Control
0
0
0
PLL3
PLL2
PLL1
PLL0
PMPLL
R/W
Default
RD
0
RD
0
RD
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
0
PMPLL: PLL Power Management
0: EXT Mode and Power down (default)
1: PLL Mode and Power up
PLL3-0: PLL Reference Clock Select (Table 16)
Default: “0010” (BICK pin=64fs)
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[AK4558]
Addr
02H
Register Name
D7
D6
D5
D4
D3
0
RD
0
RD
0
0
D4
DIF1
R/W
1
D3
DIF0
R/W
1
DAC TDM
0
0
0
R/W
Default
RD
0
RD
0
RD
0
D2
D1
D0
0
SDS1
R/W
SDS0
R/W
0
0
RD
0
SDS1-0: DAC TDM Data Select (Table 24)
Default: “00”
Addr
03H
Register Name
Control 1
R/W
Default
D7
TDM1
R/W
0
D6
TDM0
R/W
0
D5
DIF2
R/W
1
D2
ATS1
R/W
0
D1
ATS0
R/W
0
D0
SMUTE
R/W
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: All DAC outputs are soft muted.
ATS1-0: Transition Time Setting of Digital Attenuator (Table 31)
Default: “00”
DIF2-0: Audio Interface Format Mode Select (Table 23)
Default: “111” (32bit I2S)
TDM1-0: TDM Format Select (Table 23, Table 25, Table 26)
Default: “00” (Stereo Mode)
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[AK4558]
Addr
04H
Register Name
Control 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
D3
D2
D1
D0
MCKS1
MCKS0
DFS1
DFS0
ACKS
RD
0
R/W
1
R/W
0
R/W
0
R/W
0
ACKS: Automatic Clock Recognition Mode
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
When ACKS bit = “1”, master clock frequency is detected automatically. In this case, the setting of
DFS1-0 bits is ignored. When ACKS bit = “0”, DFS1-0 bits set the sampling speed mode. The MCKI
frequency of each mode is detected automatically.
DFS1-0: Sampling Speed Control (Table 8)
The setting of DFS1-0 bits is ignored when ACKS bit =“1”.
MCKS1-0: Master Clock Input Frequency Select (Table 9)
Addr
05H
Register Name
Filter setting
R/W
Default
D7
0
RD
0
D6
FS3
R/W
0
D5
FS2
R/W
1
D4
FS1
R/W
0
D3
FS0
R/W
1
D2
D1
BCKO1 BCKO0
R/W
R/W
0
1
D0
LOPS
R/W
0
LOPS: Power-save Mode of LOUT/ROUT
0: Normal Operation (default)
1: Power-save Mode
BCKO1-0: BICK Output Frequency Setting in Master Mode (Table 21)
Default: “01” (64fs)
FS3-0: Sampling Frequency (Table 17, Table 18)
Default: “0101”
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[AK4558]
Addr
06H
Register Name
Mode Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
FIRDA2
FIRDA1
FIRDA0
SLDA
SDDA
SSLOW
DEM1
DEM0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
DEM1-0: De-emphasis response control for DAC (Table 22)
Default: “01”, OFF
SSLOW: Digital Filter Bypass Mode Enable
0: Roll-off filter (default)
1: Super Slow Roll-off Mode
SLDA: DAC Slow Roll-off Filter Enable (Table 28)
0: Sharp Roll-off filter (default)
1: Slow Roll-off Filter
SDDA: DAC Short delay Filter Enable (Table 28)
0: Normal filter
1: Short delay Filter (default)
FIRDA2-0: Out band noise eliminating Filters Setting (Table 32)
default: “001” (48kHz)
Addr
07H
Register Name
HPFE Enable,
SCF_SW
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
SLAD
SDAD
HPFER
HPFEL
RD
Default
RD
0
RD
0
RD
0
R/W
0
R/W
1
R/W
1
R/W
1
HPFEL/R: ADC HPF L/Rch Setting
0: HPF L/Rch OFF
1: HPF L/Rch ON (default)
SLAD: ADC Slow Roll-off Filter Enable (Table 27)
0: Sharp Roll-off filter (default)
1: Slow Roll-off Filter
SDAD: ADC Short delay Filter Enable (Table 27)
0: Normal filter
1: Short delay Filter (default)
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[AK4558]
Addr
08H
Register Name
LOUT Volume
Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
D7
D6
D5
D4
D3
D2
D1
D0
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
ATL 7-0: Attenuation Level (Table 30)
Default:FF(0dB)
Addr
09H
Register Name
ROUT Volume
Control
R/W
Default
ATLR 7-0: Attenuation Level (Table 30)
Default:FF(0dB)
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[AK4558]
18. Recommended External Circuits
Figure 77 and Figure 78 show the system connection diagram. An evaluation board is available which
demonstrates application circuits, the optimum layout, power supply arrangements and measurement
results.
■ Parallel Mode
Mode
Controller
19
18
17
16
PMDAR/CAD1
PMDAL/CAD0
PMADR/SDA
PMADL/SCL
22
LIN
23
RIN
24
AVDD
25
VSS1
C1
Analog Supply
(2.4~3.6V)
10u 0.1u
+
15
20
LOPS
C1
PDN
21
LDOE
Reset
VDD18
VSS2
AK4558
14
13
TVDD
12
MCKI
11
1.0u
0.1u 10u
+
Top View
26
VCOM
SDTI
10
27
LOUT
BICK
9
28
ROUT
SDTO
8
VCOC
PS
CKS3
CKS2
CKS1
CKS0/TDMI
LRCK
1
2
3
4
5
6
7
1u
Power Supply
(2.4~3.6V)
Audio
Controller
Figure 77. System Connection Diagram (PS pin= “H”, LDOE pin= “H”)
Note:
- VSS1 and VSS2 of the AK4558 must be distributed separately from the ground of external
controllers.
- All digital input pins must not be allowed to float.
- An AC coupling capacitor value of at least 10uF is recommended for the LIN and RIN pins to
preserve low frequency response.
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[AK4558]
■ Serial Mode
μP
19
18
17
16
PMDAR/CAD1
PMDAL/CAD0
PMADR/SDA
PMADL/SCL
Analog Supply
(2.4~3.6V)
22
LIN
23
RIN
24
AVDD
25
AVSS
C1
10u 0.1u
+
AK4558
15
20
LOPS
C1
PDN
21
LDOE
Reset
VDD18
14
VSS2
13
TVDD
12
MCKI
11
Power Supply
(1.7~1.98V)
0.1u +
10u
0.1u 10u
+
10
Top View
26
VCOM
SDTI
10
27
LOUT
BICK
9
28
ROUT
SDTO
8
CKS1
5
LRCK
CKS2
4
Audio
Controller
7
CKS3
3
CKS0/TDMI
PS
2
6
VCOC
1
1u
Power Supply
(VDD18~3.6V)
Figure 78. System Connection Diagram (PS pin= “L”, LDOE pin= “L”)
Note:
- VSS1 and VSS2 of the AK4558 must be distributed separately from the ground of external
controllers.
- All digital input pins must not be allowed to float.
- An AC coupling capacitor value of at least 10uF is recommended for the LIN and RIN pins to
preserve low frequency response.
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[AK4558]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to each AVDD and
TVDD. AVDD is supplied from analog supply in system and TVDD is supplied from digital supply in
system. Power lines of AVDD and TVDD should be distributed separately from the point with low
impedance of regulator etc. The power up sequence between AVDD and TVDD is not critical. VSS1 and
VSS2 must be connected to the same analog ground plane. Decoupling capacitors for high frequency
should be placed as near as possible to the supply pin.
2. Voltage Reference
The voltage of AVDD sets the analog input/output range. Connect a 0.1µF ceramic capacitor between
the AVDD pin and the VSS1 pin in parallel with a 10µF electric capacitor. VCOM is a signal ground for
this device. A 1.0F ceramic capacitor attached between the VCOM pin and the VSS1 pin eliminates the
effects of high frequency noise. Do not connect the VCOM pin with an external circuit. No load current
may be drawn from this pin. All signals, especially clocks, should be kept away from the AVDD, TVDD
and VCOM pins in order to avoid unwanted noise coupling into the AK4558.
3. Analog Input
The ADC inputs is single-ended and biased to VCOM voltage (AVDD/2) internally by 8kΩ (typ @
fs=48kHz, 96kHz, 192kHz). The inputs signal range scales with AVDD nominally at 0.8 x AVDD Vpp
(typ). The output code format is 2's complement. Input DC offset (including DC offset of the ADC
itself) is canceled by an integrated high-pass filter.
The AK4558 samples the analog input at 128fs (@fs=48kHz), 64fs (@fs=96kHz) or 32fs
(@fs=192kHz). A digital filter removes the noise over the stopband attenuation level, except for a
band of integral multiplication of the sampling frequency. The AK4558 has an integrated anti-alias
RC filter in order to reduce the noise around the sampling frequency.
4. Analog Outputs
The DAC output is single-ended and output range is 0.76 x AVDD Vpp (typ) centered on VCOM. The
input data format is two’s compliment. The output voltage is positive full scale for 7FFFFFH (@24-bit
data) and negative full scale for 800000H (@24-bit data). The ideal output is VCOM for 000000H
(@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator
should be attenuated by an external filter if the noise becomes problem.
DC offsets on analog outputs are eliminated by AC coupling since analog outputs has DC offset of
VCOM.
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[AK4558]
19. Package
■ Materials & Lead Finish
Package molding compound: Epoxy Resin
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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[AK4558]
■ Marking
4558
XXXX
1
Marking Code: 4558
Pin #1 indication
XXXX: Date code (4 digit)
20. Revision History
Date (Y/M/D)
15/04/02
15/04/17
Revision
00
01
Reason
Page
First Edition
Error
1
Correction
Contents
1. General Description
AK4438 → AK4558
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
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