GS71108AU FP-BGA Commercial Temp Industrial Temp 7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS 128K x 8 1Mb Asynchronous SRAM Features Fine Pitch BGA 128K x 8-Bump Configuration • Fast access time: 7, 8, 10, 12 ns • CMOS low power operation: 140/120/95/80 mA at minimum cycle time • Single 3.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up U: 6 mm x 8 mm Fine Pitch Ball Grid Array package GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS71108A is a high speed CMOS Static RAM organized as 131,072 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS 71108 operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS71108A is available in the 6 mm x 8 mm Fine Pitch BGA package. 1 2 3 4 5 6 A NC OE A2 A6 A7 NC B DQ1 NC A1 A5 CE DQ8 C DQ2 NC A0 A4 NC DQ7 D VSS NC NC A3 NC VDD E VDD NC NC NC NC VSS F DQ3 NC A14 A11 DQ5 DQ6 G DQ4 NC A15 A12 WE A8 H NC A10 A16 A13 A9 NC Package U 6 mm x 8 mm, 0.75 mm Bump Pitch Top View Pin Descriptions Symbol Description A0–A16 Address input DQ1–DQ8 Data input/output CE Chip enable input WE Write enable input OE Output enable input VDD +3.3 V power supply VSS Ground NC No connect Rev: 1.10a 3/2011 1/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Block Diagram A0 Address Input Buffer Row Decoder Memory Array Column Decoder A16 CE WE OE I/O Buffer Control DQ1 DQ8 Truth Table CE OE WE DQ1 to DQ8 VDD Current H X X Not Selected ISB1, ISB2 L L H Read L X L Write L H H High Z IDD Note: X: “H” or “L” Rev: 1.10a 3/2011 2/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD –0.5 to +4.6 V Input Voltage VIN –0.5 to VDD +0.5 (≤ 4.6 V max.) V Output Voltage VOUT –0.5 to VDD +0.5 (≤ 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG –55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -7/-8/-10/-12 VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VDD +0.3 V Input Low Voltage VIL –0.3 — 0.8 V Ambient Temperature, Commercial Range TAc 0 — 70 oC Ambient Temperature, Industrial Range TAI –40 — 85 o C Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Rev: 1.10a 3/2011 3/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN VIN = 0 V 5 pF Output Capacitance COUT VOUT = 0 V 7 pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to VDD –1 uA 1 uA Output Leakage Current ILO Output High Z VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA 2.4 — Output Low Voltage VOL ILO = +4 mA — 0.4 V Power Supply Currents Parameter Symbol Test Conditions IDD CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA Standby Current ISB1 CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time Standby Current ISB2 CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V Operating Supply Current Rev: 1.10a 3/2011 0 to 70°C 7 ns 8 ns –40 to 85°C 10 ns 12 ns 7 ns 140 mA 120 mA 95 mA 80 mA 25 mA 20 mA 15 mA 20 mA 10 ns 12 ns 145 mA 125 mA 100 mA 85 mA 30 mA 25 mA 20 mA 2 mA 4/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 8 ns 25 mA 5 mA © 2001, GSI Technology GS71108AU AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V 50Ω Input rise time tr = 1 V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 30pF1 589Ω DQ Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ 5pF1 434Ω AC Characteristics Read Cycle Parameter Symbol Read cycle time -8 -7 -10 -12 Unit Min Max Min Max Min Max Min Max tRC 7 — 8 — 10 — 12 — ns Address access time tAA — 7 — 8 — 10 — 12 ns Chip enable access time (CE) tAC — 7 — 8 — 10 — 12 ns Output enable to output valid (OE) tOE — 3 — 3.5 — 4 — 5 ns Output hold from address change tOH 3 — 3 — 3 — 3 — ns Chip enable to output in low Z (CE) tLZ* 3 — 3 — 3 — 3 — ns Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — 0 — ns Chip disable to output in High Z (CE) tHZ* — 3.5 — 4 — 5 — 6 ns Output disable to output in High Z (OE) tOHZ* — 3 — 3.5 — 4 — 5 ns * These parameters are sampled and are not 100% tested Rev: 1.10a 3/2011 5/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA tOH Data Out Previous Data Data valid Read Cycle 2: WE = VIH tRC Address tAA CE tAC tHZ tLZ OE tOE Data Out Rev: 1.10a 3/2011 tOLZ High impedance tOHZ DATA VALID 6/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Write Cycle Parameter Symbol Write cycle time -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max tWC 7 — 8 — 10 — 12 — ns Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns Data set up time tDW 3 — 4 — 5 — 6 — ns Data hold time tDH 0 — 0 — 0 — 0 — ns Write pulse width tWP 5 — 5.5 — 7 — 8 — ns Address set up time tAS 0 — 0 — 0 — 0 — ns Write recovery time (WE) tWR 0 — 0 — 0 — 0 — ns Write recovery time (CE) tWR1 0 — 0 — 0 — 0 — ns Output Low Z from end of write tWLZ* 3 — 3 — 3 — 3 — ns Write to output in High Z tWHZ* — 3 — 3.5 — 4 — 5 ns * These parameters are sampled and are not 100% tested Write Cycle 1: WE control tWC Address tAW tWR OE tCW CE tAS tWP WE tDW Data In DATA VALID tWHZ Data Out Rev: 1.10a 3/2011 tDH tWLZ HIGH IMPEDANCE 7/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU Write Cycle 2: CE control tWC Address tAW tWR1 OE tAS tCW CE tWP WE tDW Data In DATA VALID Data Out Rev: 1.10a 3/2011 tDH HIGH IMPEDANCE 8/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU 6 mm x 8 mm Fine Pitch BGA 0.36(typ) D H G F E D C B A 0.22 ± 0.05 1 0.75(typ). 3.75 3 4 5.25 Rev: 1.10a 3/2011 9/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Ball Dia. 0.35 Pitch 0.75 6 5 Bottom View 2 pin A1 index 1.20(max) pin A1 index units: mm Top View 6.00 ± 0.10 8.00 ± 0.10 0.10 © 2001, GSI Technology GS71108AU Ordering Information Part Number* Package Access Time Temp. Range GS71108AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71108AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71108AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71108AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71108AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71108AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71108AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71108AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial GS71108AGU-7 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71108AGU-8 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71108AGU-10 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71108AGU-12 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71108AGU-7I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71108AGU-8I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71108AGU-10I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71108AGU-12I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial Note: Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS71108AU-8T. Rev: 1.10a 3/2011 10/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology GS71108AU 1Mb Asynchronous Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Content Page #/Revisions/Reason • Creation of new datasheet 71108A_r1 71108A_r1; 71108A_r1_01 Content • Added 6 ns speed bin to entire document 71108A_r1_01; 71108A _r1_02 Content • Updated all power numbers • Changed 6 mm x 10 mm package designator from U to X 71108A_r1_02; 71108A _r1_03 Content • Updated Recommended Operating Conditions table on page 3 • Updated Power Supply Currents table • Changed FPBGA package from 6 x 10 to 6 x 8 (package U) 71108A_r1_03; 71108A _r1_04 Content • Removed 6 ns speed bin from entire document • Added 7 ns speed bin to entire document 71108A_r1_04; 71108A _r1_05 Content • Added missing 300 mil SOJ mechanical drawing 71108A_r1_05; 71108A _r1_06 Content • Updated format • Added RoHS-compliant information for TSOP-II package 71108A_r1_06; 71108A _r1_07 Content • Added RoHS-compliant information for FP-BGA package 71108A_r1_07; 71108A _r1_08 Content • Added RoHS-compliant 400 mil, 32-pin SOJ 71108A_r1_08; 71108A _r1_09 Content • Updated to MP in ordering information table Content • Removed Status column from Ordering Information Table • Removed SOJ package reference from entire document • (Rev1.10a: Removed TSOP-II references due to EOL (EOL_091016111CY) 71108A_r1_09; 71108A _r1_10 Rev: 1.10a 3/2011 11/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, GSI Technology