HD74LS123 Dual Retriggerable Monostable Multivibrators (with Clear) REJ03D0429–0200 Rev.2.00 Feb.18.2005 This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs, or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS123P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74LS123FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. HD74LS123RPEL SOP-16 pin (JEDEC) A = "L" Clear = "H" EL (2,500 pcs/reel) Retrigger Pulse "H" B "L" tw + tPLH "H" Q tw "L" Output without retrigger A = "L" "H" B "L" "H" Clear "L" "H" Q "L" Output without clear Figure 1 Rev.2.00, Feb.18.2005, page 1 of 8 Typical Input / Output Pulse HD74LS123 Pin Arrangement 1A 1 16 VCC 1B 2 15 1Rext/Cext 1CLR 3 14 1Cext 13 1Q 12 2Q 11 2CLR 1Q 4 2Q 5 CLR Q Q Q CLR Q 2Cext 6 2Rext/Cext 7 10 2B GND 8 9 2A (Top view) Function Table Inputs Clear A1 L X X H X X H L H ↓ ↑ L Notes: H; high level, L; low level, X; irrelevant ↑; transition from low to high level ↓; transition from high to low level ; one high-level pulse ; one low-level pulse Outputs B2 X X L ↑ H H Q L L L Block Diagram (1/2) External parameter Cext Rext /Cext A B Clear Clear Rev.2.00, Feb.18.2005, page 2 of 8 VCC Q Q Q Q Q H H H HD74LS123 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Input pulse width A, B CLR Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C 40 — — ns 40 — — ns 40 — — ns 5 — 260 kΩ 50 pF “H” tw (in) “L” “L” External timing resistance Rext External capacitance Cext Non restriction Wiring capacitance at Rext/Cext terminal — — Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V II — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 µA mA mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, V IL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC VIK — — 12 — 20 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Output voltage VOL Input current Short-circuit output current Supply current** Input clamp voltage IIH IIL V Condition * VCC = 5 V, Ta = 25°C ** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. Note: To measure VOH at Q, VOL at Q, or IOS at Q, ground Rext / Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V. Rev.2.00, Feb.18.2005, page 3 of 8 HD74LS123 Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Symbol tPLH tPHL tPLH tPHL tPLH Inputs Outputs Q Q Q Q Q Q Q A B CLR tPHL t(out)min Output pulse width A, B t(out) min. — — — — — — — Q 4 typ. 23 32 23 34 20 28 116 4.5 max. 33 45 44 56 27 45 200 5 Unit Condition ns Cext = 0, Rext = 5 kΩ, CL = 15 pF, RL = 2 kΩ µs Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2 kΩ Typical Application Data for HD74LS123 For pulse widths when Cext ≤ 1000 pF, See Figure 3. The output pulse is primarily a function of the external capacitor and resistor. For Cext > 1000 pF, the output pulse width (tw) is defined as: tw(out) = K • Rext • Cext; See Figure 4. VCC Rext + – Cext Rext (kΩ) Cext (pF) tw(out) (ns) to Cext Figure 2 to Rext/Cext Timing Component Connections Output pulse width tw (ns) 100,000 Rext = 160kΩ 10,000 1,000 Rext = 80kΩ 40kΩ 20kΩ 10kΩ 5kΩ 100 10 1 10 100 1,000 External capacitance Cext (pF) Figure 3 Rev.2.00, Feb.18.2005, page 4 of 8 Typical Output Pulse Width (Cext ≤ 1000 pF) HD74LS123 A coefficient of output pulse width K 0.5 0.4 0.3 0.2 VCC = 5V Ta = 25°C 0.1 0 103 2 3 5 7104 2 3 5 7105 2 3 5 7106 2 3 Timing capacitance Cext (pF) Figure 4 Rev.2.00, Feb.18.2005, page 5 of 8 Cext vs. K (Cext > 1000 pF) 5 7107 HD74LS123 Testing Method Test Circuit VCC Cext A1 Input P.G. Zout = 50Ω Cext Output Q Rext /Cext VCC Rext /Cext RL Load circuit 1 Q CL B1 Input P.G. Zout = 50Ω Output Q Q CLR Input Same as Load Circuit 1. CLR P.G. Zout = 50Ω Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveform tw (in) A 3V ≥ 40ns 1.3V 1.3V tw (in) 1.3V 0V ≥ 40ns tw (in) B 1.3V 3V ≥ 40ns 1.3V 1.3V tw (in) 0V ≥ 40ns tw (CLR) 3V ≥ 40ns Clear 1.3V 1.3V 0V tPLH tPLH VOH 1.3V Q 1.3V 1.3V 1.3V VOL tPHL tw (out) tPLH Q 1.3V tw (out) 1.3V 1.3V VOH 1.3V VOL tPHL Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns. Rev.2.00, Feb.18.2005, page 6 of 8 tPHL HD74LS123 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.2.00, Feb.18.2005, page 7 of 8 8° 0.50 1 0.70 1.15 0.90 HD74LS123 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 8 1 Z e *3 bp x A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 1.75 A M L1 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 1.27 e x 0.25 y 0.15 0.635 Z 0.40 L L Rev.2.00, Feb.18.2005, page 8 of 8 8° 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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