UL ® LSI/CSI A3800 LS7082N LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 QUADRATURE CLOCK CONVERTER FEATURES: • x1, x2 and x4 mode selection • Up to 16MHz output clock frequency • INDEX input and output • UP/DOWN indicator output • Programmable output clock pulse width • On-chip filtering of inputs for optical or magnetic encoder applications. • TTL and CMOS compatible I/Os • +4.5V to +10V operation (VDD - VSS) • LS7082N (DIP); LS7082N-S (SOIC ) - See Figure 1 PIN ASSIGNMENT - TOP VIEW VSS (Pin 4) Supply Voltage negative terminal. A (Pin 5) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (Pin 8) A low level applied to this input selects x2 mode of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. B (Pin 9) Quadrature Clock Input B. This input has a filter circuit identical to input A. 7082N-012703-1 INDX 2 RBIAS 3 A NC NC 4 5 LS7082N RBIAS (Pin 3) Input for external component connection. A resistor connected between this input and V SS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A, B pulse separation (TOW ≤ TPS). 1 LSI INDX (Pin 2) Encoder Index pulses are applied to this input. V DD (+V) V SS (-V) DESCRIPTION: The LS7082N is a CMOS quadrature clock converter. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B Inputs of the LS7082, are converted to strings of Up Clocks and Down Clocks. Pulses derived from the Index Track of an encoder, when applied to the INDX input, produce absolute position reference pulses which are synchronized to the Up Clocks and Down Clocks. These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION: VDD (Pin 1) Supply Voltage positive terminal. January 2003 14 INDX 13 UPCK 12 DNCK 11 UP/DN 10 6 7 x4/x1 9 B 8 x2 FIGURE 1 TABLE 1. MODE SELECTION TRUTH TABLE x2 Input 0 1 1 x4/x1 Input Don’t Care 0 1 MODE x2 x1 x4 x4/x1 (Pin 10) This input selects between x1 and x4 modes of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. UP/DN (Pin 11) The count direction at any instant is indicated at this output. An UP count direction is indicated by a high, and a DOWN count direction is indicated by a low (See Figure 2). DNCK (Pin 12) This DOWN Clock output consists of low-going pulses generated when A input lags the B input (See Figure 2). UPCK (Pin 13) This UP Clock output consists of low-going pulses generated when A input leads the B input (See Figure 2). INDX (Pin 14) This output consists of low-going pulses generated by clock transitions at the A input when INDX input is high and B input is low (See Figure 2). NOTE: All unused input pins must be tied to VDD or VSS. ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL DC Supply Voltage VDD - VSS Voltage at any input VIN Operating temperature TA Storage temperature TSTG VALUE 11.0 VSS - 0.3 to VDD + 0.3 0 to + 70 -55 to + 150 UNITS V V °C °C DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to VSS, TA = 0°C to 70°C.) PARAMETER Supply voltage Supply current SYMBOL VDD IDD MIN 4.5 - x4/x1, x2, INDX Logic Low A, B Logic Low VIL VIL - x4/x1, x2, INDX Logic High A, B Logic High VIH VIH 0.7VDD 3.1 5.0 5.6 ALL OUTPUTS: Sink Current VOL = 0.4V IOL IOH Source Current VOH = VDD - 0.5V TRANSIENT CHARACTERISTICS: (TA = 0°C to 70°C) PARAMETER A, B inputs: Validation Delay MAX 10.0 6.0 UNITS V µA 0.3VDD 0.6 1.0 1.1 CONDITION VDD = 10.0V, All input frequencies = 0Hz RBIAS = 2MΩ V V V V VDD = 4.5V VDD = 9V VDD = 10V - V V V V VDD = 4.5V VDD = 9V VDD = 10V 1.75 5.0 5.7 - mA mA mA VDD = 4.5V VDD = 9V VDD = 10V 1.0 2.5 3.0 - mA mA mA VDD = 4.5V VDD = 9V VDD = 10V SYMBOL MIN TvD - A, B inputs: Pulse Width TPW A to B or B to A Phase Delay UNITS CONDITION 85 100 160 ns ns ns VDD = 10V VDD = 9V VDD = 4.5V TVD + TOW Infinite ns - TPS TOW Infinite ns - A, B frequency fA, B - 1 2TPW Hz - Input to Output Delay TDS - 120 150 235 ns ns ns VDD = 10V VDD = 9V VDD = 4.5V Includes input validation delay Output Clock Pulse Width TOW 50 - ns See Fig. 4 & 5 7082N-012703-2 MAX TPW A B TPS INDX TDS UPCK (x1) Tow DNCK (x1) UPCK (x2) DNCK (x2) UPCK (x4) DNCK (x4) INDX TDS UP/DN FIGURE 2. LS7082N INPUT/OUTPUT TIMING DIAGRAM RBIAS 3 A 5 B 9 CURRENT MIRROR FILTER FILTER DUAL ONE-SHOT DUAL ONE-SHOT CLOCK AND DIRECTION DECODE 14 INDX 11 UP/DN 13 x2 CLOCK MUX 12 INDX 2 x4/x1 10 x2 8 V DD 1 V SS 4 +V -V FIGURE 3. 7082N-012703-3 LS7082N BLOCK DIAGRAM NOTE : Vertical axis is output clock pulse width, Tow, ns NOTE : Vertical axis is output clock pulse width, Tow, µs 1500 30 VDD=5V VDD=5V 25 1250 VDD=9V 1000 20 VDD=10.0V 750 15 500 10 250 5 100 200 300 400 VDD=9V VDD=10.0V 500 2 Figure 4. Tow vs RBIAS , k 6 4 8 10 Figure 5. Tow vs RBIAS , M +V 10 8 x2 A CLOCK B CLOCK 5 A UPCK 9 LS7082N B ENCODER INDEX x4/x1 1 +V V DD 13 5 12 4 14 14 2 INDX INDX UPCK DNCK DNCK 16 V DD 40193 RESET V SS RBIAS 3 8 V SS 4 RB FIGURE 6. A TYPICAL APPLICATION IN x4 MODE The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7082N-012703-4 12