LSI/CSI UL ® LS7083/7084 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 October 2000 QUADRATURE CLOCK CONVERTER PIN ASSIGNMENT - TOP VIEW RBIAS 1 LSI V DD(+V) 2 LS7083 FEATURES: • x1 and x4 mode selection • Up to 16 MHz output clock frequency • Programmable output clock pulse width • On-chip filtering of inputs for optical or magnetic encoder applications. • TTL and CMOS compatible I/Os • +4.5V to +10.0V operation (VDD-VSS) • LS7083, LS7084 (DIP) LS7083-S, LS7084-S (SOIC) - See Figure 1 VSS(-V) 3 A 4 VDD (Pin 2) Supply Voltage positive terminal. VSS (Pin 3) Supply Voltage negative terminal. A (Pin 4) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. B (Pin 5) Quadrature Clock Input B. This input has a filter circuit identical to input A. x4/x1 (Pin 6) This input selects between x1 and x4 modes of operation. A high-level selects x4 mode and a low-level selects the x1 mode. In x4 mode, an output pulse is generated for every transition at either A or B input. In x1 mode, an output pulse is generated in one combined A/B input cycle. (See Figure 2.) 7083/84-100600-1 1 V DD(+V) 2 VSS(-V) 3 A LS7084 INPUT/OUTPUT DESCRIPTION: RBIAS (Pin 1) Input for external component connection. A resistor connected between this input and V SS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A,B pulse separation (TOW≤TPS). RBIAS LSI DESCRIPTION: The LS7083 and LS7084 are monolithic CMOS silicon gate quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083/LS7084, are converted to strings of Up Clocks and Down Clocks (LS7083) or to a Clock and an Up/Down direction control (LS7084). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. 4 8 UPCK 7 DNCK 6 x4/x1 5 B 8 CLK 7 UP/DN 6 x4/x1 5 B FIGURE 1 LS7083 - DNCK (Pin 7) In LS7083, this is the DOWN Clock Output. This output consists of low-going pulses generated when A input lags the B input. LS7084 - UP/DN (Pin 7) In LS7084, this is the count direction indication output. When A input leads the B input, the UP/DN output goes high indicating that the count direction is UP. When A input lags the B input, UP/DN output goes low, indicating that the count direction is DOWN. LS7083 - UPCK (Pin 8) In LS7083, this is the UP Clock output. This output consists of low-going pulses generated when A input leads the B input. LS7084 - CLK (Pin 8) In LS7084, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is indicated by the UP/DN output (Pin 7). NOTE: For the LS7084, the timing of CLK and UP/DN requires that the counter interfacing with LS7084 counts on the rising edge of the CLK pulses. ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL DC Supply Voltage VDD - VSS Voltage at any input VIN Operating temperature TA Storage temperature TSTG VALUE 11.0 VSS -.3 to VDD +.3 0 to +70 -55 to +150 UNITS V V °C °C DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to VSS, TA = 0°C to 70°C.) PARAMETER Supply voltage Supply current SYMBOL VDD IDD MIN 4.5 - MAX 10.0 6.0 UNITS V µA CONDITION VDD = 10.0V, All input frequencies = 0 Hz RBIAS = 2MΩ x4/x1 Logic Low A,B Logic Low VIL VIL 0.3VDD - 0.6 1.0 1.1 V V V V VDD = 4.5V VDD = 9V VDD = 10.0V x4/x1Logic High A,B Logic High VIH VIH 0.7VDD 3.1 5.0 5.6 - V V V V VDD = 4.5V VDD = 9V VDD = 10.0V ALL OUTPUTS: Sink Current VOL = 0.4V IOL 1.75 5.0 5.7 - mA mA mA VDD = 4.5V VDD = 9V VDD = 10.0V IOH 1.0 2.5 3.0 - mA mA mA VDD = 4.5V VDD = 9V VDD = 10.0V Source Current VOH = VDD - 0.5V TRANSIENT CHARACTERISTICS: (TA = 0°C to 70°C) PARAMETER A,B inputs: Validation Delay SYMBOL MIN TvD - A,B inputs: Pulse Width TPW A to B or B to A Phase Delay UNITS CONDITION 85 100 160 ns ns ns VDD = 10.0V VDD = 9V VDD = 4.5V TVD+TOW Infinite ns - TPS TOW Infinite ns - A,B frequency fA,B - 1 2TPW Hz - Input to Output Delay TDS - 120 150 235 ns ns ns VDD = 10.0V VDD = 9V VDD = 4.5V Includes input validation delay Output Clock Pulse Width TOW 50 - ns See Fig. 4 & 5 7083/84-100100-2 MAX TPW A B TPS TDS UPCK (x1/7083) TOW DNCK (x1/7083) UPCK (x4/7083) DNCK (x4/7083) CLK (x1/7084) CLK (x4/7084) TDS UP/DN (7084) FIGURE 2. LS7083/LS7084 INPUT/OUTPUT TIMING DIAGRAM RBIAS 1 CURRENT MIRROR A 4 FILTER B 5 FILTER DUAL ONE-SHOT DUAL ONE-SHOT x4 CLOCK CLOCK AND DIRECTION DECODE 8 x1 CLOCK UP/DN x4/x1 6 V DD 2 +V V SS 3 -V UPCK or CLK MUX 7 DNCK or UP/DN FIGURE 3. LS7083/LS7084 BLOCK DIAGRAM The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7083/84-100100-3 30 V DD=5V V DD=5V 1250 OUTPUT CLOCK PULSE WIDTH, Tow, µs OUTPUT CLOCK PULSE WIDTH, Tow, ns 1500 VDD=9V 1000 V DD=10.0V 750 500 250 100 200 300 400 25 20 V DD=9V 15 V DD=10.0V 10 5 500 Figure 4. Tow vs RBIAS, K 6 A CLOCK 4 +V ENCODER B CLOCK 5 1 16 2 V DD V DD 8 UPCK A LS7083 B 5 7 4 DNCK RBIAS CK-UP 40193 CK-DN V SS V SS 8 3 RB 8 FIGURE 6A. TYPICAL APPLICATION FOR LS7083 IN x4 MODE MODE SELECT R 6 ENCODER B CLOCK 5 1 A +V 2 16 CLK LS7084 B UP/DN RBIAS V DD 8 15 7 10 CK 4516 UP/DN V SS V SS RB +V V DD x4/x1 A CLOCK 4 3 8 FIGURE 6B. TYPICAL APPLICATION FOR LS7084 WITH x4/x1 MODE SELECTION 7083/84-100100-4 10 Figure 5. Tow vs RBIAS, M +V x4/x1 6 4 2 12