HD74LV2G123A Retriggerable Monostable Multivibrator REJ03D0098–0300Z (Previous ADE-205-352B (Z)) Rev.3.00 Sep.30.2003 Description The HD74LV2G123A features output pulse duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The basic pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level active (A) or high-level active (B) input. Pulse duration can be reduced by taking CLR low. The output pulse equation is simply : tWQ = Cext • Rext. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Electrical characteristics equivalent to the HD74LV123A Supply voltage range : 1.65 to 5.5 V Operating temperature range : –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type HD74LV2G123AUSE SSOP-8 pin Rev.3.00, Sep.30.2003, page 1 of 18 Package Code Package Abbreviation Taping Abbreviation (Quantity) TTP-8DBV US E (3,000 pcs/reel) HD74LV2G123A Outline and Article Indication • HD74LV2G123A Index band Lot No. Y M W L 2 3 Y : Year code (the last digit of year) M : Month code W : Week code SSOP–8 Marking Function Table Inputs Output Q CLR A B L X X L H H X L H X L L H L ↑ H ↓ H ↑ L H H : High level L : Low level X : Immaterial ↑ : Low to high transition ↓ : High to low transition : High level pulse Rev.3.00, Sep.30.2003, page 2 of 18 HD74LV2G123A Pin Arrangement A 1 8 VCC B 2 7 Rext / Cext CLR 3 6 Cext GND 4 5 Q (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range VCC –0.5 to 7.0 V Input voltage range *1 VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V Output voltage range *1, 2 –0.5 to 7.0 Test Conditions Output : H or L VCC : OFF Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00, Sep.30.2003, page 3 of 18 HD74LV2G123A Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage range VCC 1.65 — 5.5 V Input voltage range VI 0 — 5.5 V Output voltage range VO 0 — VCC V Output current IOH — — –1 mA — — –2 VCC = 2.3 to 2.7 V — — –6 VCC = 3.0 to 3.6 V — — –12 VCC = 4.5 to 5.5 V — — 1 VCC = 1.65 to 1.95 V — — 2 VCC = 2.3 to 2.7 V — — 6 VCC = 3.0 to 3.6 V — — 12 VCC = 4.5 to 5.5 V 0 — 300 0 — 200 VCC = 2.3 to 2.7 V IOL Input transition rise or fall rate ∆t / ∆v External timing resistance Rext ns / V VCC = 1.65 to 1.95 V 0 — 100 VCC = 3.0 to 3.6 V — 20 VCC = 4.5 to 5.5 V 5 — — 1 — — kΩ — Unlimited — F Supply transition rise rate ∆t / ∆VCC 1 — — ms / V –40 — 85 °C Note: Unused or floating inputs must be held high or low. VCC = 1.65 to 1.95 V VCC ≥ 2.3 V Cext Rev.3.00, Sep.30.2003, page 4 of 18 VCC = 1.65 to 1.95 V 0 External capacitance Operating free-air temperature Ta Conditions HD74LV2G123A Logic Diagram Cext Rext/ Cext A B Q CLR CLR Rev.3.00, Sep.30.2003, page 5 of 18 Q HD74LV2G123A Electrical Characteristic • Ta = –40 to 85°C Item Symbol VCC (V) * Input voltage VIH VIL Hysteresis voltage Output voltage VH VOH VOL Min Typ 1.65 to 1.95 VCC×0.75 — Max Unit — V Test condition 2.3 to 2.7 VCC×0.7 — — 3.0 to 3.6 VCC×0.7 — — 4.5 to 5.5 VCC×0.7 — — 1.65 to 1.95 — — VCC×0.25 2.3 to 2.7 — — VCC×0.3 3.0 to 3.6 — — VCC×0.3 4.5 to 5.5 — — VCC×0.3 1.8 — 0.25 — 2.5 — 0.30 — 3.3 — 0.35 — 5.0 — 0.45 — Min to Max VCC–0.1 — — 1.65 1.4 — — IOH = –1 mA 2.3 2.0 — — IOH = –2 mA 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 1.65 — — 0.3 IOL = 1 mA 2.3 — — 0.4 IOL = 2 mA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA V VT+ – VT– V IOH = –50 µA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Input current Rext / Cext IIN 5.5 — — ±2.5 µA VIN = VCC or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 Active state supply current ∆ICC 2.3 — — 220 µA 3.0 — — 280 4.5 — — 650 VIN = VCC or GND Rext / Cext = 0.5VCC 5.5 — — 975 Output leakage current IOFF 0 — — 5 µA VIN or VO = 0 to 5.5 V Input capacitance 3.3 — 2.5 — pF VIN = VCC or GND CIN Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00, Sep.30.2003, page 6 of 18 HD74LV2G123A Switching Characteristics • VCC = 1.8 ± 0.15 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Unit Test FROM Conditions (Input) A or B Q CLR Q Propagation delay time tPLH tPHL — 22.5 67.0 1.0 72.0 — 28.0 78.0 1.0 82.0 Enable time tZH tZL — 16.0 48.5 1.0 54.0 — 20.0 60.0 1.0 66.0 tHZ tLZ — 21.5 64.0 1.0 69.5 — 29.0 80.0 1.0 84.5 Output pulse width twQ — 315 650 — 800 ns CL = 50 pF, Cext = 28 pF, Rext = 5 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ Disable time ns CL = 15 pF TO (Output) CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) Pulse width tw 7.0 — — 8.0 — ns A, B or CLR Retrigger time trr — 150 — — — ns A or B (Rext = 5 kΩ, Cext = 100 pF) — 2.5 — — — µs A or B (Rext = 5 kΩ, Cext = 0.01 µF) Rev.3.00, Sep.30.2003, page 7 of 18 HD74LV2G123A Switching Characteristics (cont) • VCC = 2.5 ± 0.2 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Unit Test FROM Conditions (Input) A or B Q CLR Q Propagation delay time tPLH tPHL — 13.5 31.4 1.0 37.0 — 16.0 36.0 1.0 42.0 Enable time tZH tZL — 11.0 25.0 1.0 29.5 — 13.0 32.8 1.0 34.5 tHZ tLZ — 14.0 33.4 1.0 39.0 — 16.0 38.0 1.0 44.0 Output pulse width twQ — 170 260 — 320 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ Disable time ns CL = 15 pF TO (Output) CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) Pulse width tw 6.0 — — 6.5 — ns A, B or CLR Retrigger time trr — 40 — — — ns A or B (Rext = 1 kΩ, Cext = 100 pF) — 1.5 — — — µs A or B (Rext = 1 kΩ, Cext = 0.01 µF) Rev.3.00, Sep.30.2003, page 8 of 18 HD74LV2G123A Switching Characteristics (cont) • VCC = 3.3 ± 0.3 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max 20.6 1.0 24.0 Unit Test FROM Conditions (Input) A or B Q CLR Q Propagation delay time tPLH tPHL — 9.7 — 11.5 24.1 1.0 27.5 Enable time tZH tZL — 8.0 15.8 1.0 18.5 — 9.5 19.3 1.0 22.0 tHZ tLZ — 9.9 22.4 1.0 26.0 — 11.5 25.9 1.0 29.5 Output pulse width twQ — 150 240 — 300 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ Disable time ns CL = 15 pF TO (Output) CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) Pulse width tw 5.0 — — 5.0 — ns A, B or CLR Retrigger time trr — 30 — — — ns A or B (Rext = 1 kΩ, Cext = 100 pF) — 1.2 — — — µs A or B (Rext = 1 kΩ, Cext = 0.01 µF) Rev.3.00, Sep.30.2003, page 9 of 18 HD74LV2G123A Switching Characteristics (cont) • VCC = 5.0 ± 0.5 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max 1.0 14.0 Unit Test FROM Conditions (Input) A or B Q CLR Q Propagation delay time tPLH tPHL — 7.3 12.0 — 8.5 14.0 1.0 16.0 Enable time tZH tZL — 5.9 9.4 1.0 11.0 — 7.5 11.4 1.0 13.0 tHZ tLZ — 7.3 12.9 1.0 15.0 — 8.7 14.9 1.0 17.0 Output pulse width twQ — 140 200 — 240 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ Disable time ns CL = 15 pF TO (Output) CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) Pulse width tw 5.0 — — 5.0 — ns A, B or CLR Retrigger time trr — 20 — — — ns A or B (Rext = 1 kΩ, Cext = 100 pF) — 0.95 — — — µs A or B (Rext = 1 kΩ, Cext = 0.01 µF) Operating Characteristics • CL = 50 pF Item Power dissipation capacitance Symbol CPD VCC (V) Ta = 25°C Min Typ Max 3.3 — 28.0 — 5.0 — 31.0 — Rev.3.00, Sep.30.2003, page 10 of 18 Unit Test Conditions pF f = 10 MHz HD74LV2G123A Test Circuit VCC Cext – Input See Function Table VCC Rext Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF Rext = 1 kΩ or 2 kΩ or 5 kΩ or 10 kΩ + Cext Rext/ Cext A VCC Q B Output C L = 15 pF or 50 pF CLR GND Note : C L includes the probe and jig capacitance. Rev.3.00, Sep.30.2003, page 11 of 18 HD74LV2G123A Timing Diagram t rr A B CLR Rext/ Cext Q tw tw t w +t rr Caution in use In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible. Large values of Cext may cause problems when powering down the HD74LV2G123A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from Vcc through the protection diodes at pin 7 pin. Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example, if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/ 20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of Vcc to zero volts occurs, the HD74LV2G123A may sustain damage. To avoid this possibility, use an external calmping diode. The input pins for unused circuit should be used under conditions to fix the outputs to avoid malfunction caused by noises. Also, it's recommended that Rext / Cext terminals are open and external parts are not connected to. Rev.3.00, Sep.30.2003, page 12 of 18 HD74LV2G123A • Waveform – 1 Input A tf VCC 90% 50% 10% GND tr VCC 90% 50% Input B 10% GND tf tr 90% 50% Input CLR 10% tr 90% 50% 10% 90% 50% 10% VCC GND t w (L) t PLH (trigger) t PHL VOH Output Q 50% 50% VOL Rev.3.00, Sep.30.2003, page 13 of 18 HD74LV2G123A • Waveform – 2 Input A tf tr 90% 50% 10% tr 90% 50% 10% 90% 50% 10% t w (H) tf Input B VCC GND t w (L) tf tr 90% 50% 90% 50% 10% 10% t w (L) VCC 90% 50% 10% t w (H) GND VOH Output Q 50% 50% VOL t w (out) • Waveform – 3 Input A tf tf tr 90% 50% 90% 10% VCC 90% 50% 10% 10% t rr tf tr Input B 90% 50% tr 90% 10% GND 90% 50% 10% 10% VCC GND VOH Output Q 50% 50% VOL t w (out) + t rr Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. Rev.3.00, Sep.30.2003, page 14 of 18 HD74LV2G123A Application Data Vcc = 1.8 V tWQ (µs) 10000.0 1000.0 Output pulse width 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance 10 5 10 6 10 7 Cext (pF) Vcc = 2.5 V tWQ (µs) 10000.0 1000.0 Output pulse width 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance Rev.3.00, Sep.30.2003, page 15 of 18 10 5 Cext (pF) 10 6 10 7 HD74LV2G123A Vcc = 3.3 V Output pulse width tWQ (µs) 10000.0 1000.0 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance 10 5 10 6 10 7 Cext (pF) Vcc = 5.0 V Output pulse width tWQ (µs) 10000.0 1000.0 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance Rev.3.00, Sep.30.2003, page 16 of 18 10 5 Cext (pF) 10 6 10 7 HD74LV2G123A Rext = 2 kΩ 1.4 K Cext 1000 pF 10000 pF 100000 pF 1000000 pF Coefficient of output pulse width 1.3 1.2 1.1 1.0 0.9 0.8 1.5 2.0 2.5 3.0 3.5 4.0 Supply voltage 4.5 5.0 5.5 6.0 VCC (V) Rext = 10kΩ 1.4 K Cext 1000pF 10000pF 100000pF 1000000pF Coefficient of output pulse width 1.3 1.2 1.1 1.0 0.9 0.8 1.5 2.0 2.5 3.0 3.5 Supply voltage Rev.3.00, Sep.30.2003, page 17 of 18 4.0 4.5 VCC (V) 5.0 5.5 6.0 HD74LV2G123A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.3.00, Sep.30.2003, page 18 of 18 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. 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