HT16D595 Constant Current LED Driver Features General Description ●● Logic supply voltage: 4.5V~5.5V The HT16D595 is a high accuracy constant current driver which is specifically designed for LED display applications. The device provides 8-channel stable and constant current outputs for driving LEDs which may have different forward voltage characteristics, VF, due to process variations. Communication with the outside world is catered for by including a fully integrated serial interface function, which provides designers with a means of easy communication with external peripheral hardware. In this way, many devices can be cascaded together to drive larger LED ●● 8-channel constant current output ●● Channel output current is fixed at 28~34mA ●● Build-in current setting resistor ●● High output current accuracy: Variation between chips is less than ±8% ●● Up to 25MHz serial interface clock frequency ●● Maximum output terminal voltage 17V ●● Schmitt trigger input structure ●● 16-pin NSOP package displays. Applications ●● LED Display ●● Digital clock, thermometer, counter, voltmeter ●● Other consumer application Block Diagram OUT0 OUT1 OUT7 OE Q ST Q D ST Q D ST D LE SDI D CK Q D Q CK D Q SDO CK CLK Rev. 1.10 1 November 26, 2012 HT16D595 Pin Assignment OUT1 1 16 VDD OUT2 2 15 OUT0 OUT3 3 14 SDI OUT4 4 13 OE OUT5 5 12 LE OUT6 6 11 CLK OUT7 7 10 NC GND 8 9 SDO HT16D595 16 NSOP-A Pin Description Pin Name I/O Description VDD — Power supply GND — Ground SDI I Serial data input CLK I Clock input. Each data bit is shifted in to the shift register on the rising edge of the input clock signal. LE I Data Latch control. Data will be latched into the internal register on high level on the LE pin. OE O Output enable control: 1: all outputs disabled 0: all outputs enabled SDO O Serial data output OUT0~OUT7 O Parallel data output Rev. 1.10 2 November 26, 2012 HT16D595 Generic Input / Output Structure SDI,CLK, LE SDO OE VDD VDD VDD GND GND GND OUT0~OUT7 Constant Current GND Rev. 1.10 3 November 26, 2012 HT16D595 Absolute Maximum Ratings Logic Supply Voltage (VDD) ...............…................................................…………..VGND-0.3V to VGND+6.0V Logic Input Voltage .................……………….................................................………. VGND-0.3V to VDD+0.3V Output Voltage ...............…………………..................................................................................... ……………20V Output Current ...............………………................................................................................. .………………60mA GND Terminal Current....………………............................................................................. .……………….450mA Storage Temperature ................................................................................................. ………………-55°C to 150°C Operating Temperature................................................................................................ ………………-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25ºC Test condition VDD Condition VDD Logic Supply Voltage — — Min. Typ. Max. Unit 4.5 5.0 5.5 V VOUT Output Voltage 5V OUT0~OUT7 — — 17 V VIH High Input Voltage 5V SDI, CLK 0.7VDD — VDD V VIL Low Input Voltage 5V SDI, CLK 0 — 0.3VDD V VOH High-Level Output Voltage 5V SDO, IOUT=-4mA 4.6 — — V VOL Low-Level Output Voltage 5V SDO, IOUT=+4mA — — 0.4 V IOZ Output Leakage Current 5V VDS=17V — — 0.5 µA IOUT Output Current 5V VDS=1V — 28~34 — mA dIOUT2 Current Skew (chip) 5V VDS=1V — ±3 ±8 % %/dVDS Output Current VS Output Voltage Regulation 5V VDS within 1.0V and 3.0V — ±0.5 ±1.0 %/V %/dVDD Output Current VS Supply Voltage Regulation — VDD within 4.5V and 5.5V — ±1 ±2 %/V RPU Pull High Resistance 5V OE 250 500 800 kΩ IDD1 Supply Current 5V OUT0~OUT7=off — 3.0 4.5 mA IDD2 Supply Current 5V OUT0~OUT7=on — 3.5 5.3 mA Rev. 1.10 4 November 26, 2012 HT16D595 A.C. Characteristics Symbol Parameter Ta=25ºC Test condition VDD Condition Min. Typ. Max. Unit tpLH1 Propagation Delay Time (“L” to “H”, CLK→SDO) 5V — 17 25 ns tpLH2 Propagation Delay Time (“L” to “H”, LE→OUTn) 5V — 200 250 ns tpLH3 Propagation Delay Time (“L” to “H”, OE→OUTn) 5V — 200 250 ns tpHL1 Propagation Delay Time (“H” to “L”, CLK→SDO) 5V — 17 25 ns tpHL2 Propagation Delay Time (“H” to “L”, LE→OUTn) 5V — 150 200 ns tpHL3 Propagation Delay Time (“H” to “L”, OE→OUTn) 5V — 150 200 ns tW(CLK) Pulse Width 5V 10 — — ns tW(LE) Pulse Width 5V 10 — — ns tW(OE) Pulse Width 5V 300 — — ns th(LE) Hold Time For LE 5V 7 — — ns tsu(LE) Setup Time For LE 5V 10 — — ns th(SDI) Hold Time For SDI 5V 5 — — ns tsu(SDI) Setup Time For SDI 5V fCLK Clock Frequency 5V tr Maximum CLK Rise Time 5V tf Maximum CLK Fall Time 5V tor Output Rise Time of VOUT 5V tof Output Fall Time of VOUT 5V VDS=0.9V VIH=VDD VIL=GND VL=4V RL=62Ω CL=10pF CSDO = 50pF Cascade operation (Note1) 3 — — ns — — 25 MHz — — 500 ns — — 500 ns — 70 200 ns — 40 120 ns Note 1: If the devices are connected in cascade and if tr or tf is large, then these timings may be critical to achieve the correct timings for data transfer between two cascaded devices. Rev. 1.10 5 November 26, 2012 HT16D595 Test Circuit for AC Characteristics VL VDD VDD RL CL OUTn SDO CSDO Timing Waveform tW(CLK) CLK 50% tsu(SDI) SDI 50% 50% th(SDI) 50% 50% tpLH1,tpHL1 SDO 50% th(LE) LE OE tW(LE) 50% tsu(LE) 50% ‘L’ tpLH2,tpHL2 OUTn 50% tW(OE) OE tpHL3 tpLH3 90% OUTn tof Rev. 1.10 6 90% 50% 50% 10% 10% tor November 26, 2012 HT16D595 Serial-to-Serial Operation Serial-to-Parallel Output Operation The serial-to-serial function is implemented using the SDI and SDO pins. The SDI pin is used to receive serial input data for transfer into the LSB of the internal shift register while the SDO pin is used to transmit the MSB of the internal shift register to cascaded devices. Each bit of the data is shifted in from the SDI pin into the register on the rising edge of the CLK input signal where it will become the LSB of the internal shift register. At the same time, the SDO pin will shift out the MSB in the shift register to any connected cascaded devices. If the LE pin is high, then data will be latched from the shift register into an internal latch for transfer to the OUT pins. Data from the internal latch is transferred to the OUT pins using the OE pin. If the OE pin is low, then the data in the shift register will be transmitted to the output pins. The OUT pins can be disabled by setting the OE pin to a high level. The SDO pin will not be affected by the LE or OE pin status. The following timing diagram illustrates the serial-to-serial and serial-to-parallel operational waveform. 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 CLK SDI SD0 LE OE D0 OUT0 OFF ON OFF OUT1 D1 ON OFF OUT2 OUT3 D2 ON D3 OFF ON OFF OUT4 D4 ON OUT5 D5 OFF OUT6 D6 ON ON OFF OUT7 Rev. 1.10 OFF D7 7 ON November 26, 2012 HT16D595 Truth Table CLK LE OE SDI OUT0...OUT3...OUT7 SDO H L Dn Dn….Dn-3.…Dn-7 Dn-7 L L Dn+1 No Change Dn-6 H L Dn+2 Dn+2….Dn-1.…Dn-5 Dn-5 X L Dn+3 Dn+2….Dn-1.…Dn-5 Dn-5 X H Dn+3 Off Dn-5 Constant Current Output The maximum current variation between channels is less than ±3%, and that between ICs is less than ±3%. The IV curve (IOUT=26mA) of the following chart is just for reference. Iout=26mA 40 35 IOUT(mA) 30 25 20 15 10 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VDS(V) Rev. 1.10 8 November 26, 2012 HT16D595 Load Supply Voltage (VLED) HT16D595 can be operated very well when VDS is set from 0.7V to 2V. It is recommended to use the lowest supply voltage (VLED) to reduce the VDS value in order to lower both the power consumption of HT16D595 and IC temperature. VLED Control Signal VF VDS≥0.7V HT16D595 Application Circuit Rev. 1.10 9 November 26, 2012 HT16D595 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 16-pin NSOP (150mil) Outline Dimensions MS-012 Symbol Nom. Max. A 0.228 ― 0.244 B 0.150 ― 0.157 C 0.012 ― 0.020 C' 0.386 ― 0.402 D ― ― 0.069 E ― 0.050 ― F 0.004 ― 0.010 G 0.016 ― 0.050 H 0.007 ― 0.010 α 0° ― 8° Symbol Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 5.79 ― 6.20 B 3.81 ― 3.99 C 0.30 ― 0.51 C' 9.80 ― 10.21 D ― ― 1.75 E ― 1.27 ― F 0.10 ― 0.25 G 0.41 ― 1.27 H 0.18 ― 0.25 α 0° ― 8° 10 November 26, 2012 HT16D595 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 11 November 26, 2012