Recommended Test Procedures for Analog Switches ® Application Note Introduction The following text describes the basic test procedures that can be used for most Intersil CMOS switches. Various test conditions are used with the various switches. Table 1 has been included to help define the specific test setups to be used with each variety of switch. One additional note, all schematics assume an open switch for high logic inputs (i.e., NC). October 2002 AN557.1 RON is calculated from the voltage drop across a switch with a known current flow as in Figure 2. . IDS VDS V RON = DS IDS +15V DC Switch Parameters The analog signal range is the maximum input signal level which can be switched to the output with minimal distortion. For supply voltages lower than nominal, the analog signal range should be restricted to the voltage span between the supplies. Note that other parameters, such as “ON” resistance and leakage currents, are guaranteed over a smaller input range and tend to degrade toward the analog limits (+VS and -VS). Intersil switches can tolerate the positive analog signal limit (+VS) applied to one side of a switch cell while the negative analog signal limit (-VS) is applied to the other side (the switch must be open to avoid excessive currents). The analog signal range is measured (Figure 1) by increasing an input waveform until the output shows evidence of distortion or the maximum analog level is reached (as stated in the maximum ratings section of the data sheet). . +15V VIN S D VOUT ±VIN -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 2. “ON” RESISTANCE TEST CIRCUIT IS(OFF), ID(OFF), ID(ON): LEAKAGE CURRENTS Intersil prefers to guarantee only worst case high temperature leakage currents because the room temperature picoampere levels are virtually impossible to measure repeatedly on currently available automated test equipment. Even under laboratory conditions, fixture and test equipment leakage currents may frequently exceed the device leakage currents. Since the leakage currents tend to double for every 10°C increase in temperature, it is reasonable to assume that the +25°C value is about 1/1000 the +125°C value; however, in some cases there may be ohmic leakage paths, such as across the package, which would tend to make the +25°C reading slightly higher than expected. IS(OFF), measured directly with the circuit in Figure 3, consists largely of the diode leakage current from the source-body junction. ID(OFF), also measured directly with the circuit in Figure 3, is largely due to the diode leakage current in the drain-body junction. DVM 1kΩ +DCV -+ 0 S +Vs, -Vs: ANALOG SIGNAL RANGE +15V -15V FIGURE 1. SUGGESTED CIRCUIT TO DETERMINE ANALOG SIGNAL RANGE ISOFF S D IDOFF + VIN RON: ON RESISTANCE “ON” resistance is the effective series on-switch resistance measured from input to output under spedified conditions. Note that RON typically changes with temperature (highest at high temperature), and to a lesser degree with signal voltage and current. 1 ±VIN -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 3. OFF LEAKAGE CURRENT TEST CIRCUIT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved Application Note 557 “ON” leakage current (ID(ON)) is the current flowing through both the source-body and drain-body junctions of a closed switch. ID(ON) tends to have the most noticeable effect since it creates an offset voltage across the switch equal to ID(ON) *RON. ID(ON) is measured directly with the circuit in Figure 4. . +15V D S IDON CHARGE INJECTION Cycling a switch “ON” or “OFF” results in a small amount of charge being injected into the analog signal path. This charge injection is generated through the capactive coupling between the digital control lines and the analog outputs. The ensuing voltage spikes create an acquisition interval during which the output level is invalid even when little or no steady state level change is involved. The total net energy (charge injection) coupled onto the analog lines is especially critical when switching voltage to a capacitor since the injection charge will change the capacitor voltage at the instant of switching. Charge injection, measured in pico-coulombs, is measued with the aid of the circuit in Figure 6. ±VIN +15V -15V Q(pC) = CL(pf) * VOUT (VOLTS) S VOUT CL VA 0V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS D A FIGURE 4. “ON” LEAKAGE CURRENT TEST CIRCUIT Dynamic Switch Parameters -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS tON, tOFF: ACCESS TIME Switch “Turn On” time tON is the time required to activate an “OFF” switch to an “ON” state. tON is measured from the 50% point of the logic transition to the 90% point of the output transition (Figure 5). Switch “Turn Off” time tOFF is the time required to deactivate an “ON” switch to an “OFF” state. tOFF is measured from the 50% point of the logic transition to either the 90% point or 10% point (Figure 5). +15V VIN S VA 0V D OFF ISOLATION Off isolation is the degree of attenuation seen at the output of an “Open” switch when a high frequency signal is applied to the input. This feed through occurs through the sourcebody and drain-body capacitances and has a greater effect at higher frequencies. Off isolation is usually specified in decibels where Off Isolation = 20Log (VOUT/VIN), see Figure 7. The islolation generally decreases by 10dB/decade with increasing frequency. V OUT OFF ISOLATION = 20 LOG ---------------- ( dB ) V IN VOUT +15V A RL CL -15V DIGITAL INPUT FIGURE 6. CHARGE INJECTION TEST CIRCUIT VIN S D VOUT VAH 50% 1kΩ VAL tON SWITCH OUTPUT CL 50% tOFF1 90% 90% 10% -15V tOFF2 SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 5. “TURN ON” AND “TURN OFF” DELAY TEST CIRCUIT AND WAVEFORMS 2 FIGURE 7. OFF ISOLATION TEST CIRCUIT Application Note 557 CROSSTALK SETTING TIME Crosstalk is the amount of signal cross coupling from an “OFF” analog input to the output of another “ON” channel output. Crosstalk is usually measured in decibles where: Crosstalk = 20Log(VOUT2/VOUT1), see Figure 8. Setting time is the time required for the switch output to settle within a given percentage of the final value following a change in the digital input level. Usually the worst-case settling time occurs when the switch is required to slew across its full dynamic range (generally a 0V to +10V transition). This is known as full-scale settling time. V OUT2 CROSSTALK = 20 LOG ------------------- ( dB ) V IN1 +15V VIN1 D1 S1 VOUT1 +15V CL RL D2 RIN The settling time circuit, Figure 10, employs two resistors to generate an error voltage equal to the output error. A FET is used to buffer the summing junction from the oscilloscope probe capacitance. TO SCOPE -VIN VOUT2 5kΩ +15V 5kΩ CL RL VIN 0V -15V VA S D A RL VOUT CL SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 8. GENERAL CROSSTALK TEST CIRCUIT -15V T(BBM): BREAK-BEFORE-MAKE-DELAY The break-before-make-delay T(BBM) is the elapsed time between the “Turn Off” of one switch and the corresponding “Turn On” of another for a common change in logic states (Figure 9). The delay measurement is taken at the 50% levels of the output transitions. The T(BBM) delay prevents the switches from being simultaneously closed during switching transitions. +TS -TS SETTLING TIME (TS) IS MEASURED USING A HIGH SPEED RECOVERY OSCILLOSCOPE TO DISPLAY THE ERROR VOLTAGE VE. +15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS VIN S 1 VIN D1 S2 VOUT1 D2 CL 0V VA A RL RL VOUT2 CL -15V ON SWITCH OUTPUTS 0V 50% OFF ON 50% 0V OFF tBBM OFF 50% OUT1 ON OUT2 50% tBBM SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 9. BREAK-BEFORE-MAKE-DELAY TEST CIRCUIT AND WAVEFORMS 3 FIGURE 10. SETTLING TIME TEST CIRCUIT AND WAVEFORM Switch Logic Parameters VAL, VAH: INPUT THRESHOLDS The input thresholds are the digital input upper and lower limits at which proper switching action is guaranteed to take place. The input low threshold VAL is the maximum allowable voltage that can be applied to the digital input and still be recognized as a logic low (“0”) input. The input high threshold VAH is the minimum allowable voltage that can be applied to the digital input and still be recognized as a logic high (“1”) input. All other parameters will be valid if the logic inputs are either below VAL or above VAH. IAL, IAH: INPUT LEAKAGE CURRENT Input leakage current is the bias current flowing either into or out of the digital input terminal. Input leakage current high (IAH) is the current flowing while the digital input is in the high state (> VAH), while input leakage current low (IAL) is Application Note 557 the current flowing when the digital input is in the low state (<VAL). Input leakage currents are measured directly using the circuits in Figure 11. +15V I+ +15V S ±10V VAL S D1 A IAL 1kΩ PD = (+VCC *I+) + (-VCC *I-) D VA A 1kΩ 1kΩ I- -15V -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 12. SUPPLY CURRENT TEST CIRCUIT CS(OFF), CD(OFF), CD(ON), CDS(OFF),CA: SWITCH CAPACITANCE +15V ±10V VAH IAH The various switch capacitances are stated as typical values. These values are given by design and are not subject to production testing (Figure 13). D S A 1kΩ -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 11. INPUT LEAKAGE CURRENT TEST CIRCUITS Static and Package Related Switch Parameters I+, I-, PD: POWER DISSIPATION Quiescent power dissipation PD = (+VCC*I+) + (-VCC*I-) (Figure 12). PD may be specified with the switch in either a cycling or a steady state condition. Note that, as with all CMOS devices, power dissipation increases with switching frequency. Capacitance Source-Off CS(OFF) is the capacitance with respect to ground seen at the analog input with the switch open. This capacitance is the sum of the source capacitance of the N-channel and P-channel switching devices. CS(OFF) = CSGP1 + CSBP1 + CSGN + CSBN Capacitance Drain-Off CD(OFF) is the capacitance with respect to ground seen at the output terminal with the switch open. This capacitance is the sum of the drain capacitance of the N-channel and P-channel switching devices. CD(OFF) = CDGP1 + CDBP1 + CDGN + CDBN Capacitance Drain-On CD(ON) is the capacitance with respect to ground at the drain with the switch closed. Generally CD(ON) is the total of the source-off and drain-off capacitances. CD(ON) = CD(OFF) + CS(OFF) Input to output capacitance CDS(OFF) is the capacitance between the analog input and output with the switch open. Digital input capacitance CA is the capacitance with respect to ground at the digital input. CA chiefly affects propagation delays when the switch is driven by CMOS logic. 4 Application Note 557 Switch Test Fixture Design Rules The high performance characteristics of Intersil switches require high quality test fixtures for accurate characterization. The following design rules should eliminate most sources of error and provide highly accurate results. • All unused analog pins should be connected to ground through a 1kΩ resistor. • Teflon sockets should be used to minimize socket capacitance. • Decoupling capacitors should be placed as close to the supply pins as possible. +15V • A ground plane should be used to minimize distributed capacitance. CDSOFF • All grounds should terminate at a single point ground. • All sensitive analog lines should be routed between ground traces and kept away from digital lines. S • Analog and digital lines should cross at right angles. • All unused logic pins should be connected to either VAL or VAH. D CDOFF CSOFF A CA -15V SEE TABLE 1 FOR SPECIFIC TEST CONDITIONS FIGURE 13. EQUIVALENT SWITCH CIRCUIT INCLUDING CAPACITANCES All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5 6 VAL = 0.8V VAH = 2.4V VAL = 0.8V VAH = 2.4V VIN = +10V RL = 1kΩ VAL = 0.8V VAH = 3.0V HI-5042 Thru HI-5051 VIN = +10V VIN = +3V RL = 300Ω CL = 33pF VA = 5V, 0V VIN = +10V VIN = +14V IDS = 10mA VAL = 0.8V VAH = 4.0V HI-390 VIN = +10V IDS = 1mA VIN = +3V RL = 300Ω CL = 33pF VA = 5V, 0V VIN = +10V VIN = +14V IDS = 10mA VAL = 3.5V HI-307 VIN = +3V RL = 300Ω CL = 33pF VA = 4V, 0V VIN = +10V VIN = +14V IDS = 10mA VIN = +10V RL = 1kΩ CL = 35pF VA = 3V, 0V VIN = +14V VIN = +10V IDS = 1mA VIN = +10V VA = 0V, 4V RL = 1kΩ CL = 35pF VIN = +10V RL = 1kΩ CL = 35pF VA = 0V, 4V tON, tOFF VIN = +14V VIN = +14V IS, ID VIN = +10V IDS = 1mA VIN = +10V IDS = 1mA RON VAL = 0.8V VAH = 4.0V VL = 5V VR = 0V VREF OPEN VREF OPEN LOGIC REFERENCE HI-303 HI-201HS VAL = 0.8V VAH = 3.0V HI-201 HI-200 LOGIC LEVELS C = 10000pF C = 10000pF VA = 5.0V VIN = 2VP-P f = 100kHz RL = 100Ω CL = 15pF RIN = 0Ω VIN = 2VP-P f = 100kHz RL = 100Ω CL = 15pF VIN = 1VRMS f = 500kHz RL = 1kΩ CL = 15pF VIN = 1VRMS f = 500kHz RL = 1kΩ CL = 15pF C = 10000pF VA = 5.0V VIN = 3VRMS f = 100kHz RL = 1kΩ CL = 10pF VA = 3V, 0V VIN = 3VRMS f = 100kHz RL = 1kΩ CL = 10pF VA = 5V, 0V VIN = 3VRMS f = 100kHz RL = 1kΩ CL = 10pF VA = 5V, 0V VIN = 1VRMS f = 500kHz RL = 1kΩ CL = 15pF VIN = 3VRMS f = 100kHz RL = 1kΩ VA = 3V, 0V RIN = 1kΩ CROSSTALK OFF ISOLATION C = 10000pF VA = 5.0V C = 1000pF CHARGE INJECTION TABLE 1. TEST CONDITIONS FOR “HI” TYPE SWITCHES CL = 35pF VA = 3V, 0V VIN = +10V RL = 1kΩ SETTLING TIME VAL = 0V VAH = 5V RL = 300Ω CL = 33pF VIN = +3V VAL = 0V VAH = 5V RL = 300Ω CL = 33pF VIN = +3V VAL = 0V VAH = 5V RL = 300Ω CL = 33pF VIN = +3V VAL = 0V VAH = 4V VAL = 0V VAH = 4V BREAKBEFOREMAKE VA = 0V or VA = 3.0V VA = 0.8V or VA = 4.0V VAL min = 0V VAH max = 5V VAL min = 0V VAH max = 5V VA = 0V or VA = 15V VA = 0.8V or VA = 4.0V VA = 0V or VA = 3V VA = 0V or VA = 3V VA = 0V or VA = 3V POWER DISSIPATION VAL min = 0V VAH max = 15V VAL min = 0V VAH max = 5V VAL min = 0V VAH max = 5V VAL min = 0V VAH max = 5V VAL min = 0V VAH max = 5V IAL, IAH Application Note 557