Application Note 1619 Author: Richard Garcia Designing with ISL6752DBEVAL1Z and ISL6754DBEVAL1Z Control Cards These cards also provide control signals to drive Synchronous Rectifiers (SRs). An optional control circuit is provided for diode emulation. This design guide references the power topology of the ISL6752_54EVAL1Z power supply which comes complete with both of these daughter cards. The daughter cards are also available as stand alone evaluation boards to be used with customer provided power stages. Reviewing the ISL6752_54EVAL1Z ZVS DC-DC Power Supply with Synchronous Rectifiers-User Guide, AN1603, is highly recommended. Scope This application note will cover the methods for compensating the voltage error amplifier using current mode control. Biasing the peak current limit of the ISL6752 and ISL6754 is also reviewed. It is assumed that the reader has fundamental understanding of the peak current mode control. Familiarity with application note, AN1262, “Designing with the ISL6752, ISL6753 ZVS Full-bridge Controllers” is also recommended. Also covered is the compensation of the average current limit error amplifier of the ISL6754. Another subject covered by this application note is implementation requirements for proper operation of the ISL6754 when transitioning from voltage regulation to current regulation. Basic Design Considerations The ISL6754DBEVAL1Z uses two error amplifiers. One error amplifier is used to regulate the output voltage when the output load current is below the current limit value. The other error amplifier is used to regulate the output current when the output current is equal to the average current limit value. In this design example, the current amplifier is internal to the ISL6754. An external op-amp is used as the voltage amplifier. The output of the two error amplifiers are connected together with an OR-ing diode, as shown in the simplified schematic of Figure 1. When the voltage amplifier is in control of the output, the output of the amplifier is within the control range of the May 19, 2011 AN1619.1 1 +5V Vref VOLTAGE AMPLIFIER 8 2 7 Iref 8 FB Iout - 80mV + RAMP Verr PWM COMPARATOR - ISL6754 + These two controllers are basically the same except for the method used for current limiting. The ISL6752DBEVAL1Z uses pulse by pulse current limiting while the ISL6754DBEVAL1Z uses Intersil’s patented average current limiting technique. Both control cards have secondary referenced voltage error amplifiers with a linear opto-isolator used to transition the primary to secondary boundary. + The ISL6752DBEVAL1Z and ISL6754DBEVAL1Z are DC-DC power supply controllers on plug-in daughter cards. Both cards utilize Intersil’s ZVS resonant switching full bridge topology specifically intended for off-line, 500W or greater applications. PWM comparator (~ 0V to 5V). The output of the current amplifier is at the positive rail because it is demanding for more current on the output. Because the output of the current amplifier is more positive than the voltage amplifier, the OR-ing diodes block the current amplifier from controlling the output and is effectively operating open loop. + Introduction AVERAGE CURRENT AMPLIFIER FIGURE 1. TWO AMPLIFIERS CONNECTED TO ONE PWM COMPARATOR When the output load current exceeds the average current limit value, the output of the current amplifier slews rapidly down to the control range of the PWM comparator to regulate the output current. Because the output load current is being limited, the output voltage sags resulting with the output of the voltage error amplifier increasing towards the positive rail voltage. The voltage error amplifier is now operating open loop. Because only one or the other amplifier is in control of the output, it is sufficient to compensate each amplifier independently of the other. The designer does have to decide how rapidly he or she wants the transition from voltage control to current control to occur. Usually the load transient performance specification determines the compensation for the voltage error amplifier. There are other considerations for the compensation of the current amplifier. If it is desirable to allow momentary high amplitude load transients that exceed the current limit value, then the current amplifier should be compensated to respond slowly to the load transient. Because it is still necessary to limit the peak load transient current to some safe level, the pulse by pulse current limit of the ISL6754 should be biased to allow the highest acceptable load transient amplitude. In applications where it is desirable to rapidly limit the output current to the current limit value, the current amplifier can be compensated to provide nearly instantaneous limiting to the current limit value. The transition can be made so fast that the pulse by pulse current may never activate. With both fast and slow transitions between voltage and current regulation, it is necessary to insure that the minimum input voltage of -0.3V is not exceeded on the FB pin of the CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2011. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1619 ISL6754. When the output of the voltage amplifier is slewing down towards the control range of the PWM comparator, the negative dv/dt on the VERR pin will cause current to flow through the compensation capacitor of the current error amplifier resulting with a negative transient on the FB pin. A similar effect can occur on the external amplifier. For those readers who are not familiar with MathCad, the following symbols are defined as follows: := Assignment operator. The variable on the left side is assigned the value on the right side = This is the usual equals operator. The value of a symbol on the left is displayed on the right = This operator is used to assign any expression to a symbol. It is used most frequently when variables of multiple independent equations are evaluated using the find() function +5V (bold type) Vref + Iref _ 8 FB + 7 VOLTAGE AMPLIFIER Iout AVERAGE CURRENT AMPLIFIER + FIGURE 2. VOLTAGE CLAMPS TO PREVENT EXCESSIVE NEGATIVE TRANSIENTS ON FB A simple solution to the problem is to implement a negative voltage clamp on this pin, as shown in Figure 2. It may also be necessary to have a similar clamp on the negative input pin of the external amplifier depending on how it responds to excessively negative transients. About this Analysis The following design procedure is available in a native MathCad file created with MathCad ver. 14. This file may work with older versions of MathCad but it has not been evaluated with any version other than 14. New MathCad versions, when available, will probably maintain backwards compatibility. The topology used for this analysis is the ISL6752_54EVAL1Z, which uses a current doubler secondary. This analysis does not consider the center tap rectification topology. Calculations for the CT topology must be derived by the user. 2 In most cases, this analysis uses ordinary math rules for precedence and can be understood by readers who are not familiar with MathCad. For detailed help with features and functions of MathCad that are incorporated in this analysis, please refer to the MathCad 14 Users Guide. Included at the end of this application note are the schematics and the PCB layouts of the ISL6752DBEVAL1A and the ISL6754DBEVAL1Z control cards. Related Intersil Literature 1. AN1262, “Designing with the ISL6752, ISL6753 ZVS Full Bridge Controllers”, Application Note 2. AN1603, “ISL6752_54EVAL1Z ZVS DC-DC Power Supply with Synchronous Rectifiers-User Guide”, Application Note 3. FN6754,“ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control”, Data Sheet 4. FN9181,“ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control”, Data Sheet 5. “ISL6752_54DBEVAL1Z Board Design.mcdx”, Native MathCad Design File References [1] MathCad 14 Users Guide [2] Unitrode Application Note U-97” Modelling, Analysis and Compensation of the Current-mode Converter” AN1619.1 May 19, 2011 Application Note 1619 Author: [email protected] Biasing the ISL6752_54EVAL1Z Using Current Mode Control © Intersil Americas Inc. 2011. All Rights Reserved. You may use this copyrighted Mathcad data sheet solely in conjunction with Intersil products. You may modify and distribute this data sheet. However, the preceding grants of rights are subject to your agreements with the following terms: Your exploitation of the foregoing rights indicates your agreement to such terms. The copyright notice and the text following it may not be modified or removed from the Mathcad data sheet. This material is provided "as is". Intersil specifically disclaims all warranties, including without limitation the warranties of fitness for a particular purpose and merchantability. To the extent permitted by law, you indemnify Intersil Corporation and its direct and indirect subsidiaries with respect to any claims arising from your use of this Mathcad data sheet. There are seven major design steps in this analysis: 1. 2. 3. 4. 5. 6. 7. Set the oscillator frequency. Calculate the value of the current sensing resistor, Rs, for peak current limit. Set the slope compensation ratio for peak current mode control for the voltage error amplifier. Establish the DC biasing of the average current limit amplifier (ISL6754 only). Determine the small signal gain of the peak current mode power stage for bode analysis. Compensate the voltage error amplifier. Compensate the current error amplifier (ISL6754 only) Unless otherwise specified, the following analysis applies to both the ISL6752 and the ISL6754 evaluation daughter cards (ISL6752DBEVAL1Z and ISLl6754DBEVAL1Z). Because these two boards use different reference designators, this analysis uses designators as defined by the equivalent schematics shown in this document. When applicable, a cross reference table is included to identify the specific parts on each board vs. the reference designator used in this analysis. The following parameters are for the ISL6752_54EVAL1Z power supply. With appropriate changes to power components, these parameters can be modified to satisfy a custom application. Input and output parameters: Component parameters: Vbus_max 450V maximum input operating voltage Lind 3.3 μH output inductance Vbus_nom 400V nominal input operating voltage Nt 13 Vo_nom 12V max output voltage Nct 50 turns ratio of the power transformer turns ratio of the current sensing transformer Vo_min 0V min output voltage (short circuit) VCL 1V Iout_PK 65A max for pulse by pulse current limit Iout_min 0A no load Peak Current Limit voltage primary magnetizing inductance of the Lpri 3200 μH power transformer Oscillator timing capacitor CT 180pF Iout_avg 60A Average current limit RTD 6.65KΩ Timing capacitor discharge resistor (used to set dead time) Step 1) Setting the Oscillator Frequency TC 11.5 KΩ CT 2.07 μs TD 0.06 RTD CT 50ns P TC TD Freq Dmax 2 P 122 ns 2.192 μs 1 P TD Vbus_min Charge time for CT as defined in the data sheet. Note that TC is increased by the presence of the CT slope transistor Q1. To minimize the loading on the CT pin, the beta of Q1 should be greater than 200. P 2 Dmax Discharge time for CT (as defined in the data sheet). This is also the dead time between the two FETs on one side of the full bridge. Calculated PWM period for one half cycle 228.121 KHz This is the frequency of the full bridge and of each output current doubler inductor. Note that the actual switching frequency of the ISL6752_54EVAL1Z is 200KHz because of the loading effects of Q1 on the CT pin. 0.944 This is the maximum duty cycle Nt Vo_nom 330.361 V 3 This is the input voltage at which the output begins regulation. AN1619.1 May 19, 2011 Application Note 1619 Step 2) Rs for pulse by pulse current limit The nominal Duty cycle for each current doubler inductor: Vo_nom Dnom_ind Vbus_nom Nt Period for each current doubler inductor is 2P 0.390 Inductor currents 12 V and Vbus_nom The nominal on period for Vo_nom Ton 2 P Dnom_ind Summed current of both inductors 400 V : 1.71 μs Iupramp Iupramp is the i of the current in one output Ton Iout 2 inductor of the current doubler topology. The average current of each inductor is ½ of the total output D=Ton /2xP 2xP · § Vbus_nom Vo_nom ¸ ¨ Nt ¸ Ton 9.724 A Iupramp ¨ Lind © ¹ Transformer voltage waveform P = TC+TD Ipri_mag is the i of the primary side magnetizing current. Ipri_mag Vbus_nom Lpri Ton Xfmr magnetizing current Ipri_mag 0.214 A Isense.p is the peak output current referenced to the output of the current sensing transformer. Ipri_mag 59.617 mA Rb 2.2V VCTE 0.2V 9 VCT.s 2V TC 0.966 T1 V μs Rs CS - 80 mV + VCS D1 8 RAMP 1.71 μs 1 - 0.6V + 7 Tct VCS = Ra Rb Rs VCTE.p Isense.p 1 Rs 4 Ra Rb 1 = 1V 50:1 - Average current limit amplifier CT Rb Cycle by cycle I limit comparator - 1V CS 8 D1 Rs Rs 7 Q1 2.2V VCTE 0.2V VCS is the voltage that is seen on the CS input FB ISL6752 current sensing 2.8V VCT 0.8V (calculated using superposition). Peak current limit occurs when VCS = 1 PWM comparator + @ Ton Cycle by cycle I limit comparator 2 2 VCTE.p is the peak voltage as seen on the emitter of Q1 at the end of the on period: 1.852 V - Verr Ra 50:1 VCTE.p VCT.s Ton .2V - 1V Rc VCT.s is the rising slope of the CT signal CT Ra VCS PWM comparator - 80 mV + Verr 2 + 2 Nct 6 Q1 + 2 2 Nt Nct Nt Nct ISL6754 current sensing 2.8V VCT 0.8V + Isense.p Iupramp + Iout_PK 3 1 AN1619.1 May 19, 2011 Application Note 1619 Step 3) 3) Slope compensation Step Slope compensation slope compensation ratio definition: slope compensation ratio definition: Vramp.s M = M = Vramp.s = 1= 1 or or Vramp.s = =VV down.s Vramp.s down.s Vdown.s V down.s Output Inductor current down slope Output Inductor current down slopecurrent currentscaled scaled to to the output of the current sensing transformer the output of the current sensing transformer: : Vo_nom Vo_nom Idown.s Idown.s LindL N Nct indt N t Nct M = 1 is the optimal slope compensation ratio. V is M = 1 is the optimal slope compensation ratio. Vramp.sramp.s is the ramp added to the current sense scaled to the ramp the ramp added to the current sense scaled to the ramp Vdown.s pinofofthe theISL6752. ISL6752. is the effective down Vdown.s pin is the effective down slopeslope rampthat thatisisproportional proportional to the down slope current ramp to the down slope current of theof the outputinductor inductoralso also scaled to the ramp pinthe of ISL6752. the ISL6752. output scaled to the ramp pin of (referenceUnitrode Unitrode app note U-97) (reference app note U-97) AA Idown.s Idown.s 0.006 0.006 μs μs RbRb º º Idown.s RR R Idown.s R I ª ª Idown.s » »== down.s bb s Vdown.s = «= « Vdown.s 1 1 R R R R R 1 1 R R R R R « Rs« Rs R a RaRbRb a a b»b» aa bb s ¬ ¬ ¼¼ Idown.s Notethat thatIdown.s does actually appear on output the output Note does notnot actually appear on the of of thecurrent currentsensing sensing transformer. value is only the transformer. ThisThis value is only usedused toscale scaleVV to ramp.s ramp.s Primary magnetizing slopecurrent, current,VVmag.s scaled Primary sideside magnetizing upup slope mag.s,, scaled to output the output of the current sensingtransformer: transformer: to the of the current sensing Vbus_nom Vbus_nom AA 0.003 Imag.sImag.s 0.003 L N Lpri Nprict ct μsμs Imag.s both contribute theslope slopecompensation. compensation. CT.s and VCT.sVand Imag.s both contribute totothe Ra RaRs Rs RbR bR R ss Vramp.s VCT.s Imag.s Vramp.s = = R R RVCT.s R R R Imag.s Ra aRs sRb b Ra a Rb b Rs s substituting (c) and (b): substituting (c) and (d)(d) intointo (b): M= Note of two components. Notethat thatMMisiscomposed composed of two components. Imag.s Imag.s is the slope compensation that is contributed by Idown.s is the slope compensation that is contributed by Idown.s the magnetizing current of the power transformer the magnetizing current of the power transformer Ra Rs Rb Rs Ra R s VCT.s Rb Rs Imag.s Ra Rs RVbCT.s Ra Rb RsImag.s R R R R R R s b a b s M =a Simplifying: Simplifying: Idown.s Rb Rs Idown.s Rb Rs Ra Rb Rs Ra Rb Rs VCT.s Ra Rs the injected compensation. and VCT.s Ra Rsis and Idown.s Rb Rs is the injected compensation. Idown.s Rb Rs VCT.s Ra Rs Imag.s VCT.s Ra Rs MImag.s = I Idown.s Rb Rs M= down.s Idown.s Idown.s Rb Rs Solving for Rb: Solving for Rb: VCT.s Ra Rs (eq 2) Rb = VCT.s Ra Rs Rs Imag.s Idown.s M (eq 2) Rb = Rs Imag.s Idown.s M Given Ra 499Ω Rb 10000Ω Rs 20Ω M 2 Given Ra 499Ω Rb 10000Ω Rs 20Ω M 2 1V Ra Rb Rs = 1V RbR I VCTE.p 1V RIasense.p a sense.p Rb Rs = R Isense.p Rb VCTE.p V1V IRsense.p CT.s a Rs a Rb = V Ra IR s M RCT.s s Imag.s down.s Rb = I I R § Rs ·s mag.s down.s M § 16.713 · Find Rs Rb ¨ ¸Ω § Rs ·¨© Rb ¸¹ ·¹ § ©16.713 3431.248 ¨ ¸ Find Rs Rb ¨ ¸Ω KΩ © 3431.248 ¹ Rs 16.71 Ω © Rb ¹Ra 499 Ω Rb 3.43 This is the second of two equations required to solve for ThisResistor is the second twoand equations required to solve for two variablesof(Rs Rb) two Resistor variables (Rs and Rb) Initial estimated values (note that M can be made larger than the optimal value of 1(note to overcome noise on Initial estimated values that M can beproblems made larger the ramp than the input). optimal value of 1 to overcome noise problems on the ramp input). Ra following 499 Ω values Rb 3.43 KΩthe actual Rs reference 16.71 Ω designators on the ISL6752 and ISL6754 daughter cards. The arefor The following values are for the actual reference designators on the ISL6752 and ISL6754 daughter note that R4 cards. and R6 R13 Ra 499 Ω R17 Rb 3431 Ω R4 Rs 2 33.4 Ω R6 R4 33.4 Ω are in parallel note that R4 and R6 R13 Ra 499 Ω R17 Rb 3431 Ω R4 Rs 2 33.4 Ω R6 R4 33.4 Ω are in parallel Note that the portion of slope compensation ratio contributed Confirming the slope compensation ratio, M: Imag.s VCT.scompensation Ra Rs Confirming the slope ratio,Imag.s M: 2 Idown.sVCT.sIdown.s Imag.s Ra RRbsR s 2 Idown.s Idown.s Rb Rs 5 Idown.s Imag.s Idown.s I 0.447 0.447 I mag.s Notemag.s thatcan thebe portion of slope compensation ratio contributed by significant. If Lpri is small enough, Idown.s I down.sImag.s Imag.s byitself cancan be significant. If Lpri is small enough, by Idown.s be be greater than 1. Idown.s by itself can be be greater than 1. AN1619.1 May 19, 2011 Application Note 1619 Step 4) Average Current limit (ISL6754 only) In the above calculations, the value of Rs is calculated for pulse by pulse current limiting for Iout_PK 65 A . The average current limit is set to a lower value ( Iout_avg 60 A ) to prevent the peak current limiting from interfering with the average current limit control loop. VIout Iout_avg 2 Nt Nct Rs 4 This is the output voltage on the Iout pin of the ISL6754 when Iout_avg 60 A . 3.085 V To limit the output current to Iout_avg, the resistor divider of R25 and R26 are chosen so that the voltage on FB (pin 7) is .6V when VIout 100 uA. 3.085 V . For accurate performance, the maximum load on the Iout pin should also be limited to approximately ISL6754 current sensing 6 Q1 CT Given R25 10KΩ 9 R25 R26 T1 D1 = 100 μA RAMP - PWM comparator 2 2 1 50:1 § 24.9 · ¨ ¸ KΩ © 6.0 ¹ - 0.6V + 7 These are the actual values used on the ISL6754DBEVAL1Z control board: R25 22100Ω 8 Verr Ra Rs § R25 · Find( R25 R26) ¨ ¸ © R26 ¹ - 80 mV + VCS + VIout Rc CS Cycle by cycle I limit comparator + R26 VIout = .6V R25 R26 - 1V + R26 6KΩ Rb FB - R24 10 Average current limit amplifier IOUT R25 R26 6650Ω R26 Step 5) Small Signal Gain of the Current Mode Power stage (Iout/Verr) The input to the positive side of the PWM comparator (using superposition): Isense Rb Rs Vpwm_pos = Ra Rb Rs Ra Rs Rs Ra Rb VCT.s D 2P .6V 80mV verr where Isense and D are variables PWM current mode power stage zout iout vout with gain gt The input to the negative side of the PWM comparator: Vpwn_neg = Verr 2 Vdiode Cout RL Resr where Verr is a variable 3 The duty cycle terminates when Vpmw_pos = Vpwm_neg : (eq A) Isense Rb Rs Ra Rb Rs Ra Rs Rs Ra Rb VCT.s D 2P .6V 80mV = Peak Current sense: (eq B) Isense = Iout 2 Nt Nct Vbus Nt 1 Vo Lind Nt Nct D P Vbus Lpri Nct D P Verr 2 .6V 3 The first term of eq. B is the average current of one current doubler output inductor. The 2nd term is the up slope current of one output inductor. The 3rd term is the up slope current of the primary referenced magnetizing inductance (Lpri) of the power transformer. Duty cycle: (eq C) D= Vo Vbus Nt 6 AN1619.1 May 19, 2011 Application Note 1619 Substituting definitions of duty cycle D , eq C, and Isense , eq b, into eq A and simplifying: 1 §¨ Iout ·¸ Vbus Nt Vo Vbus Ra Rs Verr 2 .6V § 2 Nt P Vo VCT.s · D P D P .6V¸ 80mV = ¸ Rs Ra Rb ¨© Lpri Nct Ra Rb Rs ¨ 2 Nt Nct Lind Nt Nct Vbus 3 ¹ © ¹ Rb Rs solving for Iout and isolating Verr (eq E) 2 Nt Nct Ra Rb Rs Iout = 3 Rb Rs Verr Nt Nct V 0.24 Ra 0.96 Rb 0.24 Rs Rb Rs 2 2 Nt P Vo VCT.s 2 Nt Nct Ra Rs P Vo Vbus Nt Vo 2 Nt P Vo 2 Nt Nct Vbus Rb Rs Lind Nt Nct Vbus Lpri (eq E) is formatted as y=mx+b format where m is the slope and b is the offset of a line equation. where: x = Verr m= 2 Nt Nct Ra Rb Rs 3 Rb Rs and b= 2 Nt Nct V 0.24 Ra 0.96 Rb 0.24 Rs 2 Nt P Vo VCT.s 2 Nt Nct Ra Rs P Vo Vbus Nt Vo 2 Nt P Vo 2 Nt Nct Rb Rs Vbus Rb Rs Lind Nt Nct Vbus Lpri For AC analysis, Vo and Vbus are constants. The slope, m, is the small signal gain, gt , used for the bode analysis of the peak current mode power stage 2 Nt Nct Ra Rb Rs gt 3 499 Ω Ra gt Rb Rs 3.431 KΩ Rb 29.825 Rs A V 16.713 Ω These values are repeated here for reference. To validate the above calculations, Iout is redefined as a function of Vo , Vbus and Verr Iout Vo Vbus Verr Nt Nct V 0.24 Ra 0.96 Rb 0.24 Rs ª 2 Nt Nct Ra Rb Rs Verr « Rb Rs Rb Rs « 3 2 « 2 Nt P Vo VCT.s 2 Nt Nct Ra Rs P Vo Vbus Nt Vo 2 Nt P Vo 2 Nt Nct « Vbus Rb Rs Lind Nt Nct Vbus Lpri ¬ Verror 0.5V 1V 5V Vo_nom 12V Vo_min 6V Vbus_max 450 V Vbus_nom 400 V º » » » » ¼ Vbus_min 330.361 V 100.0 Iout Vo_nom Vbus_max Verror 90.0 80.0 Iout Vo_nom Vbus_nom Verror 70.0 Iout Vo_nom Vbus_min Verror Iout Vo_min Vbus_max Verror Iout Vo_min Vbus_nom Verror Iout Vo_min Vbus_min Verror 60.0 50.0 40.0 30.0 20.0 10.0 0.0 1.0 1.3 1.5 1.8 2.0 2.3 2.5 2.8 3.0 3.3 3.5 3.8 4.0 4.3 4.5 4.8 5.0 Verror 7 AN1619.1 May 19, 2011 Application Note 1619 The slope of these lines is the small signal gain iout verr = gt 12 V (solid lines) or These plots illustrate how Iout varies as Verror , Vbus , and Vo are changed. For constant Vo_nom 6 V (dotted lines), Vbus exhibits minimal influence on Iout as expected. For Vbus_min constant Vo_min 330.4 V to 450 V (the operating input voltage range), Iout changes very little for a constant Verror . Vbus_max As Vo is varied, between Vo_nom and Vo_min , gt remains constant. This is also expected because the slope compensation does not changed as Vo deviates from the nominal output voltage of 12V. When Vo decreases, as it will during current limit, the down slope current of the output inductors also decreases effectively increasing the slope compensation because the injected slope compensation from Vct does not change. Xpwm = gt = stage. vout is the small signal output voltage and verr is the small signal control voltage from the error amplifier. verr iout or verr iout = Xpwm is the gain of the PWM current mode power vout vout verr = zout vout Xpwm = verr = vout iout iout gt gt is the transconductance of the PWM current mode stage. gt = zout is the load impedance on the output of the current mode power stage. RL is the output load, Cout is the output capacitance and Resr is the ESR of the output capacitance. vout gt zout = gt zout gt zout note: the impedance of two parallel components is 1 ª« 1 · »º 1 § zout = RL ¨Resr ¸ «¬ Cout s ¹ »¼ © RL = 1 1 z = 1 z1 1 z2 or 1 z = z1 1 z2 1 Vout Iout s gt = gt §¨ 1¸· Freq 2 π ¨ ¸ © 2 1 The small signal gain has a pole at 1/2 the switching frequency (refer to Unitrode application note U-97) ¹ This gain function is used in the bode analysis for the ISL6752 and ISL6754. 1 1 ª s 1 · »º « 1 § Xpwm ( s) = gt ª« 1º» RL ¨Resr ¸ Cout s ¹ »¼ ¬ ( π Freq) ¼ «¬ © 8 1 verr PWM current mode power stage zout iout vout with gain gt Cout RL Resr AN1619.1 May 19, 2011 Application Note 1619 Step 6) Compensation of the Voltage Error Amplifier Functions for Bode Analysis db ( G f ) 20 log G 2π f j Gain in decibels of a Laplace gain function G for frequency f § © ϕ ( G f ) mod ¨arg G 2π f j 180 π · ¹ 360¸ fUnityGain ( G) Phase in degrees of a Laplace gain function G 8 root db ( G f ) f 100 10 Unity gain frequency of function G ϕmargin ( G) ϕ G fUnityGain ( G) 0 Unity gain phase margin of function G § db 20 1· © v ¹ Vdb2V dbv 10 F f0 fN N i db to voltage function for i 0 N Equidistant frequency data points for plotting: i § fN · f i m f0 ¨ ¸ © f0 ¹ This function generates N equidistant frequency data points on the log X scale with starting frequency f 0 and ending N frequency f N f N 200 i 0 N 8 f F .01 1 u 10 N i 9 f 0 0.01 fN 6 100 u 10 AN1619.1 May 19, 2011 Application Note 1619 Open loop gain of the LMV431 From LMV431data sheet The open loop transfer function of the LMV431 is created here by inserting poles as necessary to recreate the Gain/Phase plot found in the data sheet. Note that the phase shift is relative to the input. Vdb2V 57 GLMV431 ( s) db GLMV431 f i s s ·§ § 1· ¨ 1000 2 π 1¸ ¨ © ¹ 1 u 106 2 π ¸ © ¹ 80 180 70 150 60 120 50 90 40 60 30 30 20 0 10 30 0 60 10 90 0 20 100 1u 10 3 1u 10 fUnityGain GLMV431f i 10 4 1u 10 120 6 1u 10 5 605.566 u 10 ϕ GLMV431 f i 3 AN1619.1 May 19, 2011 Application Note 1619 Gain of the Voltage Amplifier Vi R3 For an Inverting Opamp the gain function, X(s), can be simplified to: Cx Rx XVerror.Amp ( s) = H1 ( s) GLMV431 ( s) Vo = Vi 1 H2 ( s) GLMV431 ( s) U1 LMV431 R5 1 ª§ 1 1 º» · «¨ Rx¸ R5¼ ¬© Cx s ¹ H1U1 ( s R3 R4 R5 Rx Cx) 1 ª§ 1 1 »º · «¨ Rx¸ R5¼ ¬© Cx s ¹ 1 1 1 1º ª « ( R3 R4) R5» ¬ ¼ 1 gain block diagram for an inverting amplifier ( R3 R4) H2(s) 1 1º ª « ( R3 R4) R5» ¬ ¼ H2U1 ( s R3 R4 R5 Rx Cx) Vo R4 1 Vi 1 ª 1 · º «§¨ Rx¸ » ¬© Cx s ¹ ¼ 1 Vo H1(s) GLM431(s) These values are used here only to illustrate and confirm the gain/phase functions R3 18 10 9 3 Cx .1 10 Rx 0 1 H2U1 ( s R3 R4 R5 Rx Cx) GLMV431 ( s) db XVerror.Amp f i 0 3 R5 2.15 10 H1U1 ( s R3 R4 R5 Rx Cx) GLMV431 ( s) XVerror.Amp ( s) db GLMV431 f i R4 649 60 180 50 150 40 120 30 90 20 60 10 30 0 0 10 30 20 60 30 90 40 120 50 150 60 1u 10 100 3 1u 10 f 11 4 1u 10 5 ϕ XVerror.Amp f i ϕ GLMV431 f i 180 6 1u 10 i AN1619.1 May 19, 2011 Application Note 1619 Open loop gain of EL5111 (note: some earlier releases of the ISL6752DBEVAL1Z and ISL6754DVEVAL1A use the EL5120 instead of the EL5111. The EL5120 has been obsoleted and is not recommended for new designs. In this application, the EL5120 and EL5111 are interchangeable.) From EL5111 data sheet Note that the phase of this graph is the output referenced to the negative input of the opamp. The open loop transfer function of the EL5111 is created here by inserting poles as necessary to recreate the gain/phase plot found in the data sheet. Vdb2V 68 G5111 ( s) s s § 1¸· § 1· ¨ ¨ © 19000 2 π ¹ 100 u 106 2 π ¸ © ¹ db G5111 f i 0 80 250 70 220 60 190 50 160 40 130 30 100 ϕ G5111 f i 20 70 10 40 0 10 20 20 1u 10 The phase of this graph is the output referenced to the negative input of the opamp. 10 3 1u 10 4 1u 10 5 1u 10 f fUnityGain G5111 12 2 i 6 1u 10 7 50 8 1u 10 6 40.889 u 10 AN1619.1 May 19, 2011 Application Note 1619 Gain of the EL5111 Compensation amplifier Vout VDD R24 R24 R13 R23 C9 D2 Vin PS2701 CTR ˜ 1 - - U2 EL5111 +5V + + Actual Compensation Amplifier R23 C9 R13 -Vin Vout - - U2 EL5111 + Vout + Equivalent AC Model The compensation amplifier provides two functional advantages. First, the optocoupler, D2, is biased with a constant voltage across the collector and emitter. The closed DC feedback loop around U2 keeps the negative input virtually at the same voltage as the positive input resulting with a constant DC voltage (VDD - 5V) across the optocoupler. The advantage of this cascode configuration is that there is no regenerative AC feed back through Ccb of the opto transistor. Consequently, the pole introduced by the optocoupler is greatly increased in frequency. The improved bandwidth of the opto removes its detrimental influence on the voltage feedback loop. Note that R13 is the same value in the ac model as it is in the actual circuit. This is the consequence of the optocoupler having a nominal ctr = 1. Also, note the negative value of Vin in the equivalent AC Model. This is necessary because in the actual circuit, Vin and Vout at low frequencies are in phase. In the equivalent AC Model, because the opamp is an inverting configuration, Vin must be negated to preserve the correct phase of the actual circuit. The second advantage of this opamp is that the loop compensation network is on the secondary side. Traditionally, the compensation network is applied around the LMV431. The problem is that when the average current regulator takes control of the loop to regulate the output current (by controlling the PWM input), the voltage regulator loop is opened causing the LMV431 output to saturate to the positive rail (Vout). If the voltage loop compensation is around the LMV431, the feedback network will greatly slow the slew rate (~ msecs) of the output of the LMV431. If the load is quickly reduced below the current regulation value (the current limit), the output voltage will overshoot until the output of the LMV431 slews down to the voltage necessary to regulate the output voltage (taking control away from the current regulator). This effect is especially bad for a short circuit load dump. If the loop compensation is not located around the LMV431, the output of the LMV431 will still saturate when the current regulator is in control of the PWM input, but the output is not now impeded by the local feedback and will recover very quickly minimizing the output voltage overshoot. Note that the compensation network around U2 is decoupled from the output of U2 by the series diode on the output. This diode prevents the feedback network capacitor from charging up to the rail voltage. This same technique is used on the output of the current regulator opamp (internal to the ISL6754). In a manner similar to the voltage control loop, the output of the current regulator is saturated when the voltage loop has control. Without the diode on its output, the current regulator would also be slow to respond to an over current for the same reason as stated for the voltage regulator loop. 13 AN1619.1 May 19, 2011 Application Note 1619 The voltage gain function for an Inverting Opamp: gain block diagram for an inverting amplifier H2(s) X ( s) = H1 ( s) G5111 ( s) Vo = Vi 1 H2 ( s) G5111 ( s) 1 º ª 1 1 · «§¨ R23¸ Cx s» R24 ¬© C9 s ¹ ¼ H1U2 ( s R13 R24 R23 C9 Cx) 1 º ª§ 1 1 · «¨ R23¸ Cx s» R24 ¬© C9 s ¹ ¼ G5120(s) H1(s) -Vi Vo 1 1 R13 R13 H2U2 ( s R13 R24 R23 C9 Cx) 1 º ª§ 1 1 · R23¸ Cx s» R13 «¨ R24 ¬© C9 s ¹ ¼ 1 These values are used here only to illustrate and confirm the compensation around the EL5111 amplifier: 126 R24 10 10 R23 4000 XComp.Amp ( s) R13 2200 123 Cx 100 10 C9 .01 10 6 H1U2 ( s R13 R24 R23 C9 Cx) G5111 ( s) 1 H2U2 ( s R13 R24 R23 C9 Cx) G5111 ( s) db G5111 f i db XComp.Amp f i 100 180 80 135 60 90 40 45 20 0 0 45 20 90 40 135 60 1 10 100 1u 10 3 1u 10 f 14 ϕ G5111 f i ϕ XComp.Amp f i 4 1u 10 5 1u 10 6 180 7 1u 10 i AN1619.1 May 19, 2011 Application Note 1619 Current mode PWM power stage gain with output loads The derivation of this small signal gain for the PWM power stage is found in step 5). gt = 2 Nt Nct ( R11 R14 R1_2) ( R14 R1_2) 3 PWM current mode power stage verr zout iout vout with gain gt 1 1 ª s 1 · »º « 1 § Xpwm ( s) = gt §¨ 1·¸ RL ¨Resr ¸ Cout s ¹ »¼ © Freq π ¹ «¬ © Cout 1 RL Resr Converting Xpwm to a function: R11 499 3 R14 9.09 10 Nt 13 Cout 8800 10 Nct 50 Resr 0.02 R1_2 13.2 gt 6 Vout 12 Iout 60 Freq 208300 2 Nt Nct ( R11 R14 R1_2) ( R14 R1_2) 3 s Xpwm ( s) gt §¨ 1·¸ Freq π © ¹ db Xpwm f i Vout RL Iout 34.678 1 ª« 1 · »º 1 § RL ¨Resr ¸ «¬ Cout s ¹ »¼ © 1 1 40 30 30 0 20 30 10 60 0 90 ϕ Xpwm f i 0 10 120 20 150 30 180 40 1 10 100 1u 10 3 1u 10 f 15 4 1u 10 5 1u 10 6 210 7 1u 10 i AN1619.1 May 19, 2011 Application Note 1619 Bode plot for the total Voltage loop gain The Resr contributes significantly to the stability of the loop by introducing a zero to the bode of PWM current mode power stage. With Resr = 0, the phase margin of the complete loop is at a minimum (but still stable). With increasing values of ESR, the phase margin improves and the unity grain frequency increases. The nominal value of Resr of the ISL6754EVAL board is 0.02 ohms. But as operating temperatures decrease, the Resr value increases resulting in the unity gain frequency approaching the PWM switching frequency. To avoid PWM switching frequency instability, it is wise to add a pole on the U2 amplifier to reduce the unity gain frequency. In this design example, if the gain of the compensation amplifier is set for no poles and zeros (except for the inherent pole of the amplifier) by setting R23 to infinity and/or by setting C9 to a very small value (although not zero), the loop is stable without any further compensation. This is the consequence of the single pole of the LMV431 error amplifier and the zero of the PWM current mode stage canceling each other. As with any analysis, some assumptions are made. In this bode analysis, the following assumptions were made: 1) The esl of the output capacitors are assumed not to significantly contribute the the bode of the PWM to output gain stage. 2) the turn off delays of the PWM control and bridge FETs is assumed to be insignificant. In reality, the turn off delay may result in non-linear transconductance gains of the PWM current mode stage. It is important that the turn off delays be as minimal as possible (~1% of the total PWM switching period). 3) the bandwidth of the opto transistor is assumed to be high enough to not contribute poles that affect the closed loop phase. Because other parasitic effects may also result with unexpected loop response, it is absolutely necessary to actually measure the bode response to insure that the loop compensation is adequate. Vi Error amplifier 3 R3 18 10 R4 649 R3 Cx Rx 3 R5 2.15 10 Rx 0 12 Cx 100 10 Xerror.Amp ( s) Vo R4 U1 LMV431 R5 H1U1 ( s R3 R4 R5 Rx Cx) GLMV431 ( s) 1 H2U1 ( s R3 R4 R5 Rx Cx) GLMV431 ( s) Compensation amplifier Cx R23 5000 R13 5000 R24 5000 R24 R23 C9 6 C9 1 u 10 126 Cx 1 10 XComp.Amp ( s) R13 -Vin H1U2 ( s R13 R24 R23 C9 Cx) G5111 ( s) 1 H2U2 ( s R13 R24 R23 C9 Cx) G5111 ( s) - - U2 EL5111 + Vout + Equivalent AC Model of the Compensation Amp 16 AN1619.1 May 19, 2011 Application Note 1619 PWM Current Mode Stage 6 R14 10000 Cout 8800 10 Resr .020 Vout 12 Iout.min .011 Iout.max 66 R11 499 30.9 2 Nct 50 R1_2 PWM current mode power stage zout iout vout with gain gt Cout 1 RL_max 2 Nt Nct ( R11 R14 R1_2) 3 verr RL RL_min Vout Iout.min Nt 13 gt Output parameters Xpwm.RLmin ( s) Xpwm.RLmax ( s) ( R14 R1_2) Resr 1 Vout Iout.max 29.49 gt Xpwm.RLmin Gain function for min load 1 ª 1 · »º 1 § § s 1· «R ¨ Freq π ¸ « L_min ¨Resr C s ¸ » © ¹¬ out ¹ ¼ © gt 1 ª 1 · º» 1 § § s 1· u «R ¨ Freq π ¸ « L_max ¨Resr C s ¸ » © ¹ ¬ out ¹ ¼ © Xpwm.RLmaxGain function for max load Xtotal.gain.RLmin ( s) Xerror.Amp ( s) u XComp.Amp ( s) Xpwm.RLmin ( s) Xtotal.gain.RLmax ( s) Xerror.Amp ( s) XComp.Amp ( s) Xpwm.RLmax ( s) Gain and Phase for Minimum Load 60 180 50 150 40 120 30 20 db XComp.Amp f i 10 db Xerror.Amp f i 0 db Xpwm.RLmin f i 10 90 0 20 60 30 90 40 120 50 150 db Xtotal.gain.RLmin f i 60 30 0 ϕ Xtotal.gain.RLmin f i 30 60 1 10 100 1u 10 3 1u 10 f fUnityGain Xtotal.gain.RLmin 17 11557 4 1u 10 5 1u 10 6 180 7 1u 10 i ϕmargin Xtotal.gain.RLmin 81 AN1619.1 May 19, 2011 Application Note 1619 Gain and Phase for Maximum Load 60 180 50 150 40 120 30 20 db XComp.Amp f i 10 db Xerror.Amp f i 0 db Xpwm.RLmax f i 10 90 0 20 60 30 90 40 120 50 150 db Xtotal.gain.RLmax f i 60 30 0 ϕ Xtotal.gain.RLmax f i 30 60 1 10 100 1u 10 3 1u 10 f fUnityGain Xtotal.gain.RLmax 4 1u 10 5 1u 10 180 7 1u 10 6 i ϕmargin Xtotal.gain.RLmax 10428 82 Load Regulation As can be seen in the above bode plots, the low frequency closed loop gains at minimum load and maximum load varies significantly primarily because of the change in gain of the PWM output stage. The consequence is that the output voltage will droop as the load increases from minimum to maximum. This droop is relatively large in this design example because the gain of the LMV431 error amplifier is relatively low (especially when compared to the EL5111). Vref 1.24V Vout 12V The reference voltage of the LMV431 The output voltage of the ISL6754EVAL board R5 2.15KΩ R3_4 18.649KΩ R3_4 is the sum of R3 and R4 1) Vref Vneg AVOLoop = Vout also 2) Vneg Where AvOLoop is the open loop gain including all of the gain elements (LMV431, EL5111, and PWM output). R5 Vout R5 R3_4 R3_4 substituting 2) into 1): R5 Vneg R5 Vout · § ¨Vref ¸ AVOLoop = Vout R5 R3_4 ¹ © - - AvOLoop Vref = 1.24V + Vout = 12V + solving for Vout and converting to a function: Vout AVOLoop Vref Equivalent DC Model of the Closed Loop R5 1 R5 R3_4 AVOLoop Because the Xtotal.gain includes the degenerative gain of the voltage scaling resistors R3_4 and R5, we must exclude this gain stage from this load regulation analysis. 11.9957 V This is the DC output voltage when Iout.min 0.011 db XComp.Amp f 0 db Xpwm.RLmax f 0 11.9652 V This is the DC output voltage when Iout.max 66 0 Vout Vdb2V db GLMV431 f db XComp.Amp f 0 db Xpwm.RLmin f 0 0 Vout Vdb2V db GLMV431 f 18 AN1619.1 May 19, 2011 Application Note 1619 Load regulation: db XComp.Amp f 0 db Xpwm.RLmax f 0 0 Vout Vdb2V db GLMV431 f db XComp.Amp f 0 db Xpwm.RLmin f 0 0 Vout Vdb2V db GLMV431 f LoadRegLMV431 99.746 % If an EL5111 is substituted for the LMV431 as the error amplifier, additional gain is added to the open loop gain which improves the load regulation: 57 0 db G5111 f 68 0 db GLMV431 f Vout Vdb2V db G5111 f Low Frequency gain of the EL5111 db XComp.Amp f 0 db Xpwm.RLmin f 0 This is the DC output voltage when Iout.min 0.011 11.9957 V 0 This is the improved DC output voltage when Iout.max 66 db XComp.Amp f 0 db Xpwm.RLmax f 0 11.9871 V Vout Vdb2V db G5111 f db XComp.Amp f 0 db Xpwm.RLmax f 0 0 Vout Vdb2V db G5111 f db XComp.Amp f 0 db Xpwm.RLmin f 0 0 Vout Vdb2V db G5111 f LoadRegEL5111 Low Frequency gain of the LMV431 0 99.928 % Step 7) Compensation of the Current Error Amplifier Open Loop Gain of the ISL6754 Internal Amplifier G6754 ( s) Vdb2V 100 The GBWP of the internal amplifier is specified as 5MHz. Although, the maximum gain a low frequencies is not specified, for the purpose of this analysis, the max gain is assumed to be 100db. § s 1· ¨ 50 2 π ¸ © ¹ db G6754 f i 0 100 180 80 135 60 90 40 45 20 0 0 45 20 90 40 135 60 10 1u 10 100 3 1u 10 4 1u 10 f 5 1u 10 6 1u 10 7 ϕ G5111 f i 180 8 1u 10 i fUnityGain G6754 6 5 u 10 Gain of the Current Error Amplifier The scaling factor for current sensing (From step 4) R25 22100 R26 6650 VS Iout_avg §¨ 4R1_2 · ¸ © 2 Nt Nct ¹ 19 AN1619.1 May 19, 2011 Application Note 1619 For an Inverting Opamp the gain function, X(s), can be simplified to: Vo Iout_avg = H1 ( s) G6754 ( s) § 4Rs · ¸ ¨ 1 H2 ( s) G6754 ( s) © 2 Nt Nct ¹ 1 ª§ 1 1 º · «¨ » R38¸ R26¼ ¬© C11 s ¹ H1U1 ( s R25 R26 R38 C11) 1 ª§ 1 1 º · «¨ » R38¸ R26¼ ¬© C11 s ¹ 1 º ª 1 « ( R25) R26» ¬ ¼ 1 1 6 XIerror.Amp ( s) - 7 R26 Vo Iref 11 ( R25) Amplifier internal to the ISL6754 1 1 ª§ 1 · º «¨ R38¸ » ¬© C11 s ¹ ¼ H2(s) 1 Iout_avg These values are used to compensate the current regulation closed loop. C11 .01 10 4•Rs Vs 2Nt•Nct 2 R25 1 ª 1 1 º « » ¬ ( R25) R26¼ H2U1 ( s R25 R26 R38 C11) Iout_avg C11 + XIerror.Amp ( s) = R38 4•Rs Vs 2Nt•Nct H1(s) G6754(s) Verr gain block diagram for the Current error amplifier R38 0 H1U1 ( s R25 R26 R38 C11) G6754 ( s) § 4 u 100 · ¸ ¨ 1 H2U1 ( s R25 R26 R38 C11) G6754 ( s) © 2 Nt Nct ¹ Gain of the PWM Current Mode Power Stage From step 5) gt s 1·¸ Freq 2 π ¨ ¸ gt ( s) gt §¨ © 2 PWM current mode power stage verr Low frequency gain (Iout_avg/Verr) 29.49 1 Iout_avg with gain gt with switching frequency pole ¹ Total Current Regulation Loop GainC11 10 u 10 9 R38 0 XIloop.total.gain ( s) XIerror.Amp ( s) gt ( s) db XIerror.Amp f i db gt f i db XIloop.total.gain f i 0 100 180 90 150 80 120 70 90 60 60 50 30 40 0 30 30 20 60 10 90 0 120 10 150 20 1 10 100 1u 10 f fUnityGain XIloop.total.gain 20 ϕ XIerror.Amp f i ϕ gt f i ϕ XIloop.total.gain f i 6518 i 3 1u 10 4 1u 10 5 180 6 1u 10 ϕmargin XIloop.total.gain 86 AN1619.1 May 19, 2011 ISL6754DBEVAL1Z Schematic VDD R29 R8 0 R30 1 3 EMITTER 1K R33 499 5 4 EL5111 EL5120IWT V+ 2 C11 4.75K 0.01UF 3 4 9 10 DISABLE J1 3 J1 16 5 OUTUL OUTUR OUTLLN 15 7 J1 J1 J1 CS OUTLRN IOUT GND ISL6754AAZA 12 C5 C10 14 9 13 11 13 11 OUTLL OUTLR OUTUL OUTUR J1 OURLLN J1 OUTLRN C15 0.1UF 1 THIS PAD BETWEEN 100PF 3 Q2 100PF R39 10K C17 1K 1 2 10K BSS138 10K C18 100PF R35 C16 R34 2 6.65K 100PF 82PF 100PF C4 18 VREF D5 100PF C8 100PF C6 10K 10 6.65K R10 CS- J1 33.2 R7 12 R4 PGND J1 33.2 R6 R25 100 14 8 499 17 19 R37 DNP 1K OUTLL OUTLR CT FB RAMP 7 22.1K 8 6 R18 499 R12 6 3.48K R20 R17 R13 20 RTD RESDEL 5 R24 SS VADJ VDD VREF VERR CTBUF 2 R36 1K R31 R38 100 2 Q1 1 61.9K U4 MMBT2222LT1 R21 1 15.4K R9 C2 3 VREF TP_PRI PGND R26 PGND 4 5 U2 3 V+ OUT 1 DRAWN BY: D3 1 ANODE 2 CATHODE COLLECTOR 4 1 EMITTER 3 2 V- TSW-102-08-T-D-RA J2 SR_ENABLE J2 SEC_GND 2 0.1UF EL5111 EL5120IWT C9 DNP 4 R15 R27 10K 10K R14 R23 DNP DNP R19 VDD VREF PS2701 SEC_GND AN1619.1 May 19, 2011 PGND FIGURE 3. ISL6754 CONTROL CARD SCHEMATIC RELEASED UPDATED RICHARD_GA BY: BY: Application Note 1619 0.1UF VDD PGND PGND J1 2 PGND SEC_GND TSW-107-08-T-D-RA VDD J1 1 VREF J1 2 CS+ J1 CS J1 D4 1 V- C14 C13 R28 1K 1 OUT 3 C7 0.1UF U3 0.1UF R22 PS2701 DNP BZX84C6V8LT1 C D1 1 A 2 NC 4 CATHODE R32 C12 3 2 3 R3 SEC_GND J2 2.15K 21 SGND DNP 4 COLLECTOR 0.1UF U1 1 LMV431AIMF D2 ANODE 2 TBD DNP R2 TP_SEC 649 R5 C3 1K R16 1K R11 R1 C1 0.1UF 18K 499 0.01UF 3 +12VOUT J2 ISL6752DBEVAL1Z Schematic VDD R29 R8 C2 2 CATHODE 4 EMITTER 3 R31 1K C12 R33 499 5 4 EL5111 EL5120IWT D4 U3 OUT 1 2 V- C14 0.01UF R24 1K C13 3 C7 0.1UF V+ 0.1UF DNP R22 BZX84C6V8LT1 C D2 PS2701 1 2 A 3 R3 2.15K 22 LMV431AIMF 4 SGND J2 DNP COLLECTOR 0.1UF U1 1 SGND 1K R16 ANODE 3 1 2 R5 D5 OPEN DNP R2 649 TP_SEC C1 0.1UF R11 18K R1 499 NC +12VOUT J2 0 R30 1K 3 PGND TSW-107-08-T-D-RA VDD J1 1 VREF C11 3 DNP 5 13 7 12 9 OUTLLN 11 11 J1 J1 J1 OUTLRN CS GND ISL6752AAZA 10 13 J1 6 RESDEL CT OUTUL OUTUR 9 5 3 1 PGND DISABLE J1 4 FIGURE 4. ISL6752 CONTROL CARD SCHEMATIC ANODE 2 CATHODE COLLECTOR 4 1 EMITTER 3 2 2 PGND PGND D3 1 V- C9 20K R15 47UF 2 C16 1K OUT 4 EL5120IWT EL5111 0.1UF 3 10K Q2 R27 U2 V+ 1 10K 10K R34 R35 100PF 10K C17 R37 C10 47PF 6.65K C5 82PF R7 C4 100PF 47PF C8 10K R18 BSS138 100PF 10K 10 37.4 R10 CS- J1 R6 12 R4 PGND J1 C6 VDD 1M R19 R32 37.4 TP_PRI 14 OUTLL OUTLR OUTUL OUTUR OURLLN OUTLRN VREF VREF 100 PGND J1 J1 J1 R23 61.9K R36 3 14 VERR CTBUF 0.1UF 10K R14 R21 3.48K R17 R12 8 OUTLL OUTLR 15 RTD 8 499 16 5 7 R13 VDD VADJ VREF 2K 665 100 4 6 CS J1 1 2 D1 2 Q1 PGND CS+ J1 R28 1 20K R9 C3 0.1UF U4 MMBT2222LT1 R20 3 PS2701 TSW-102-08-T-D-RA J2 SR_ENABLE J2 SGND Application Note 1619 2 VREF J1 AN1619.1 May 19, 2011 Application Note 1619 ISL6754DBEVAL1Z REV.B C2 R22 R6 R4 R12 C16 R11 C17 Q2 R28 C13 R35 R34 R36 C15 D4 U3 D2 R39 R33 C12 R16 C5 C4 U4 R30 R32 R20 R25 R26 R24 C11 R18 R19 C7 J2 R7 C10 R23 D3 R10 C6 R9 D5 C14 D1 U1 R1 R8 C18 R27 R2 R5 C3 U2 C1 R13 R29 R3 R15 R14 C9 R31 R38 Q1 R21 R17 C8 R37 J1 FIGURE 5. ISL6754 CONTROL CARD TOP ASSEMBLY 23 AN1619.1 May 19, 2011 Application Note 1619 ISL6754DBEVAL1Z REV.B C8 R21 R17 R26 R31 R38 R13 C11 R18 D5 R7 C9 C2 Q1 C18 C1 D3 R23 R1 U4 D4 R33 D1 C14 R11 D2 J2 U3 R22 R6 R4 R12 R28 C13 J1 C15 C5 C4 R39 C17 Q2 C16 R37 C12 R29 R16 C3 C10 R19 R30 R32 R27 R8 U1 C7 C6 R9 R35 R34 R36 U2 R3 R2 R5 R10 R20 R25 R24 R15 R14 Pb FIGURE 6. ISL6754 CONTROL CARD TOP LAYER 24 AN1619.1 May 19, 2011 Application Note 1619 ISL6754DBEVAL1Z REV.B FIGURE 7. ISL6754 CONTROL CARD BOTTOM LAYER 25 AN1619.1 May 19, 2011 Application Note 1619 ISL6752DBEVAL1Z REV.B R21 Q1 R20 R17 C8 U2 C16 R24 D4 D5 Q2 U3 R16 R11 R33 C12 R29 D2 C4 R31 C7 C5 U4 R30 R32 D3 R9 C13 R34 R23 C2 U1 R8 C6 R19 C14 R5 R36 R35 R1 R7 R10 C11 R2 C17 D1 C1 R27 R3 C10 C3 R13 R18 R37 R28 R15 R14 C9 R22 R4 J2 R6 R12 J1 FIGURE 8. ISL6752 CONTROL CARD TOP ASSEMBLY 26 AN1619.1 May 19, 2011 Application Note 1619 Pb U3 C14 R11 R22 R4 J2 R6 R12 R10 R20 U4 R28 R33 R34 R32 D2 C5 C4 C11 D5 R27 R29C12 R30 R31 D4 C2 R16 C3 R19 R8 U1 C7 C6 R9 Q2 C16 R3 R2 R5 Q1 D1 SGND C9 TP_SEC U2 C1 D3 R23 R1 R15 R14 TP_PRI R17 R37 C17 R36 R21 C8 R13 C10 R18 R7 PGND ISL6752DBEVAL1Z REV.B R24 C13 R35 J1 ISL6752DBEVAL1Z REV.A FIGURE 9. ISL6752 CONTROL CARD TOP LAYER 27 AN1619.1 May 19, 2011 Application Note 1619 ISL6752DBEVAL1Z REV.B FIGURE 10. ISL6752 CONTROL CARD BOTTOM LAYER Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 28 AN1619.1 May 19, 2011