W232 Ten Output Zero Delay Buffer Features • • • • Key Specifications Well suited to both 100- and 133-MHz designs Ten/Eleven LVCMOS/LVTTL outputs 3.3V power supply Available in 24-pin TSSOP package Operating Voltage: ................................................ 3.3V±10% Operating Range: ........................25 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter: ................................................<150 ps Output to Output Skew: ............................................<100 ps Phase Error Jitter: .....................................................<125 ps Static Phase Error: ....................................................<150 ps Block Diagram )%,1 &/. Pin Configurations 3// 1 24 CLK VDD 2 23 AVDD 4 Q0 3 22 VDD 4 Q1 4 21 Q8 20 Q7 19 GND 18 GND 17 Q6 Q2 5 GND 6 4 GND 7 4 Q3 8 4 2( 2( Q4 9 16 Q5 VDD 10 15 VDD OE0:4 11 14 OE5:8 FBOUT 12 13 FBIN $*1' &/. 9'' $9'' 4 9'' 4 4 4 *1' *1' 4 4 2( 4 : AGND )%287 4 4 &RQILJXUDWLRQ RI WKHVH EORFNV GHSHQGHQW XSRQ VSHFLILF RSWLRQ EHLQJ XVHG : 4 *1' *1' 4 4 4 4 9'' 4 2( 9'' )%287 )%,1 Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 8, 2000, rev. *C W232 Pin Definitions Pin Name Pin No. (-09) Pin No. (-10) Pin Type CLK 24 24 I Reference Input: Output signals Q0:9 will be synchronized to this signal. FBIN 13 13 I Feedback Input: This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Q0:8 3, 4, 5, 8, 9, 16, 17, 20, 21 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 O Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. FBOUT 12 12 O Feedback Output: Typically this is connected directly to the FBIN input with a trace equal in length to the traces between outputs Q0:9 and the destination points of these output signals. AVDD 23 23 P Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. AGND 1 1 G Analog Ground Connection: Connect to common system ground plane. VDD 2, 10, 15, 22 2, 10, 14 22 P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. GND 6, 7, 18, 19 6, 7, 18, 19 G Ground Connections: Connect to common system ground plane. OE0:4 11 -- I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state. OE -- 11 I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state. OE5:8 14 -- I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state. Pin Description Overview The W232 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay buffers which are not designed to pass this feature through may cause skewing failures. The W232 is a PLL-based clock driver designed for use in systems requiring a large number of synchronous timing signals. The clock driver has output frequencies of up to 140 MHz and output-to-output skews of less than 100 ps. The W232 provides minimum cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications. Output enable pins allow for shutdown of output when they are not being used. This reduces EMI and power consumption. 2 W232 9'' 0.1 µ) $*1' 9'' *1' $9'' 4 9'' 4 4 4 4 *1' *1' *1' *1' 4 4 4 4 9'' 4 2( 9'' )%287 )%,1 : 9'' 0.1 µ) 0.1 µ) )% 9 10 µ) 0.1 µ) 10 µ) )% 9'' 0.1 µ ) 9'' Figure 1. Schematic Spread Aware™ If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. 5HIHUHQFH 6LJQDO =HUR 'HOD\ %XIIHU External feedback is the trait that allows for this compensation. Since the PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL. )HHGEDFN $6,& %XIIHU ,QSXW Figure 2. 6 Output Buffer in the Feedback Path 3 $ W232 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any Pin with Respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10% Parameter Description IDD Supply Current Test Condition Min. Typ. Unloaded, 100 MHz Max. Unit 200 mA VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 12 mA VOH Output High Voltage IOH = –12 mA IIL Input Low Current VIN = 0V 50 µA IIH Input High Current VIN = VDD 50 µA Max. Unit 140 MHz 0.8 2.0 V V 0.8 2.1 V V AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10% Parameter Description Test Condition [4] Min. Typ. fOUT Output Frequency 30-pF load tR Output Rise Time 0.8V to 2.0V, 30-pF load 2.1 ns tF Output Fall Time 2.0V to 0.8V, 30-pF load 2.5 ns 4.5 ns 4.5 ns tICLKR tICLKF Input Clock Rise Time Input Clock Fall Time 25 [1] [1] tPEJ CLK to FBIN Skew Variation tSK [2, 3] Measured at VDD/2 –350 0 350 ps Output to Output Skew All outputs loaded equally –100 0 100 ps tD Duty Cycle 30-pF load 43 50 58 % tLOCK PLL Lock Time 1.0 ms 150 ps tJC Power supply stable Jitter, Cycle-to-Cycle [5] Notes: 1. Longer input rise and fall time will degrade skew and jitter performance. 2. Skew is measured at VDD/2 on rising edges. 3. Duty cycle is measured at VDD/2. 4. Production tests are run at 133 MHz. 5. For frequencies below 40 MHz, Cycle-to-Cycle Jitter degrades to 175 ps. Ordering Information Ordering Code W232 Option Number -09, -10 Package Type 24-pin TSSOP Document #: 38-00827-C 4 W232 Package Diagram 24-Pin Thin Shrink Small Outline Package (TSSOP) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.