RENESAS R2S15901SP

R2S15901SP
Digital Delay IC for “Lip Sync”
REJ03F0151-0100
Rev.1.0
Apr 28, 2005
Description
R2S15901SP is a digital audio delay chip to synchronize the TV video and audio signals.
Features
•
•
•
•
CMOS Technology
2-Channel 24-bit Audio signals delay
Delay time is controlled by DC voltage (9steps: 1, 7/8, 3/4, 5/8, 1/2, 3/8, 1/4, 1/8 times)
43K bytes RAM up to delay 224ms(@fs = 32kHz)
When fs = 48kHz, maximum delay is 149ms.
• 2 3-state pins for 9-step configuration
• 3.3V signal input available
Recommended Operating Condition
Supply Voltage Range
VDD = 2.5V (typ.)
Circuit Current
IDD = 1.0mA (typ.)
Operation Temperature
Topr= –20 to 75ºC
Applications
LCD TV, PDP, DVD Recorder, AV Amplifier
Rev.1.0 Apr 28, 2005 page 1 of 7
R2S15901SP
Block Diagram
BCKI
LRI
SDI
LRI
BCKI
L/R
Serial
Audio
I/F
Input
RD
WR
RAM
I/F
Di
Do
SRAM
Addr
L/R
Serial
Audio
I/F
Output
SDO
COU NT 0
COU NT 1
Contol
Input/Output Configuration
The schematic diagrams of the input and output circuits of the logic section are shown below:
VSS
Input pin 1, 2, 3
Rev.1.0 Apr 28, 2005 page 2 of 7
VDD
VDD
VDD
31K
H
31K
L
VSS
Input Pin 5, 6
VSS
Output Pin 7
R2S15901SP
Pin Configuration
SDI
1
8
VDD
LRI
2
7
SDO
BCKI
3
6
COUNT1
VSS
4
5
COUNT0
Pin Description
Pin No.
Pin Name
I/O
Description
1
SDI
I
• Serial audio data input
• The input audio data are fetched at every LRI edge.
2
LRI
I
•
•
•
•
3
BCKI
I
• Bit clock input
• BCK clock is 64 times as large as LRI and input audio data.
4
VSS
—
• Ground
5
6
COUNT0
COUNT1
I
• Delay time control 0
• Delay time control 1
• Delay time control pin. These two inputs are 3-state input pins that may be set high
LR clock
Audio sample frequency.
Low indicates the audio input data SDI and output data SDO are left channel data.
High indicates the audio input data SDI and output data SDO are right channel data.
or low, or left unconnected to generate the third state. With the 3-state condition, 9step delay time may be organized.
7
SDO
O
• Audio data output
• This SDO is the delayed audio data output.
8
VDD
—
• Power supply +2.5V
Rev.1.0 Apr 28, 2005 page 3 of 7
R2S15901SP
Function Description
Serial Interface
LRI
BCK
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The input audio data format is I2S 24-bit 64fs as above with the same as output.
Delay Time
The R2S15901SP provides 9 steps time delay by using two control pin COUNT0 and COUNT1. The two control pins
provide 3-state respectively to generate 9 steps time delay. COUNT0 and COUNT1 may be tied to high, low or left
unconnected. Internal comparator circuitry monitor input state to determine the input is high, low or middle state.
Internal Pull high and low resistor keep input at VDD/2. The comparator distinguishes terminal voltage level as below.
L
0
M
0.7
1.0
H
1.5 1.7
2.5
Input
voltage(V)
Sampling Rate
(fs)
Max
COUNT[1:0]=HH
7/8
COUNT[1:0]=HM
6/8
COUNT[1:0]=HL
5/8
COUNT[1:0]=MH
192kHz
96kHz
37ms
75ms
33ms
65ms
28ms
56ms
23ms
47ms
88.2kHz
48kHz
81ms
149ms
71ms
131ms
61ms
112ms
51ms
93ms
44.1kHz
32kHz
163ms
224ms
142ms
196ms
122ms
168ms
102ms
140ms
(Sampling Counts)
(7168)
(6272)
(5376)
(4480)
Sampling Rate
(fs)
4/8
COUNT[1:0]=MM
3/8
COUNT[1:0]=ML
2/8
COUNT[1:0]=LH
1/8
COUNT[1:0]=LM
0
COUNT[1:0]=LL
192kHz
96kHz
19ms
37ms
14ms
28ms
9ms
19ms
5ms
9ms
0ms
0ms
88.2kHz
48kHz
41ms
75ms
30ms
56ms
20ms
37ms
10ms
19ms
0ms
0ms
44.1kHz
32kHz
81ms
112ms
61ms
84ms
41ms
56ms
20ms
28ms
0ms
0ms
(Sampling Counts)
(3584)
(2688)
(1792)
(896)
(0)
The delay time is evaluated by the following formula:
Delay Time = (1/fs) × (sampling counts + 1) sec
Rev.1.0 Apr 28, 2005 page 4 of 7
R2S15901SP
Mode Change
The R2S15901SP samples COUNT0 and COUNT1 pins while LRI is low by BCKI. When COUNT0 and COUNT1 are
sampled and changed, they are detected at low interval of LRI. The delay counts start from the following falling edge of
LRI with SDO to be delayed by sample counts + 1.
The SDO output is muted before the first new delay data being issued, when the new mode is recognized. An internal
POR(Power On Reset) circuitry is to setup the initial mode right after power applied.
Digital Audio Delay
COUNT0, 1
Mode switch detect
Sample counts + 1
LRI
BCKI
SDO
23 22 21 20
23 22 21 20
SDI
23 22 21 20
23 22 21 20
Mode change timing
Absolute Maximum Ratings
(Unless otherwise stated, VDD = 2.5V, VSS = 0V, Ta = 25°C)
Parameter
Symbol
Ratings
Unit
Power supply voltage
Input pin voltage
VDD
VI
–0.3 to +2.75
–0.3 to 3.6
V
V
Power dissipation
Operating temperature
PD
Topr
100
–20 to +75
mW
°C
Storage temperature
Tstg
–40 to +125
°C
Rev.1.0 Apr 28, 2005 page 5 of 7
R2S15901SP
Electrical Characteristics
(Unless otherwise stated, VDD = 2.5V, VSS = 0V, Ta = 25°C)
Parameter
Operating VDD voltage
Symbol
VDD
Min.
2.25
Typ.
2.5
Max.
2.75
Unit
V
Operating current
Test Condition
IDD
—
1
—
mA
BCKI: 13MHz
SDO: CL=25pF
High level input voltage
VIH
1.7
—
3.3
V
LRI, SDI, BCKI
Low level input voltage
VIL
—
—
0.7
V
LRI, SDI, BCKI
Output high voltage
VOH
1.85
—
VDD
V
IOH = -2mA
Output low voltage
VOL
0
—
0.4
V
IOL = 2mA
Input high current
IIH
–10
—
10
µA
VIN = VDD
Input high current with 31kΩ pull down
IIH(PD)
40
80
160
µA
VIN = VDD
COUNT0, COUNT1
Input low current
IIL
–10
10
µA
Input low current with 31 kΩ pull up
IIL(PU)
–160
–80
–40
µA
Input capacitance
Input rise/fall transition time
CIN
Tr/Tf
—
—
10
—
—
100
pF
nS
VIN = VSS
VIN = VSS
COUNT0, COUNT1
Serial Audio Timing
Serial Audio Input Timing Parameters
Parameter
Min.
Typ.
Max.
Unit
fBCK
tSIL
—
35
—
—
13
—
MHz
ns
BCKI to LRI time
tSIH
tSLI
35
15
—
—
ns
ns
LRI to BCKI time
Data Setup time
tLSI
tDS
15
15
—
—
—
—
ns
ns
Data Hold time
Data output delay
tDH
tDOD
15
—
—
—
—
15
ns
ns
tSIL
tSLI
BCKI frequency
BCKI period
L pulse width
H pulse width
Symbol
LRI
tSIH
tLSI
BCKI
tDS
SDI
SDO
tDOD
Rev.1.0 Apr 28, 2005 page 6 of 7
tDH
Test Condition
SDO: CL = 25pF
R2S15901SP
Package Dimensions
8-Pin, SOP Package
Rev.1.0 Apr 28, 2005 page 7 of 7
Body Size : 150mil Pin pitch : 1.27mm
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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