P1750AE/SOS
SINGLE CHIP, 30MHz, ENHANCED
SPACE PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
Single Chip MIL-STD-1750AE Processor
Form-Fit-Functionally Compatible with the
P1750A CMOS Processor
DAIS Instruction Mix Execution Performance
Including Floating Point Arithmetic
1.8 MIPS at 20 MHz
2.25 MIPS at 25 MHz
2.7 MIPS at 30 MHz
BIF Instructions Allow for High Throughput
Implementations of Transcedental Functions,
Navigational Algorithms, and DSP Functions
20, 25 and 30 MHz Operation over the Military
Temperature Range (-55 to +125°c)
Extensive Error and Fault Management and
Interrupt Handling Capability. Built in Self Test.
Two programmable Timers
26 User Accessible Registers
TTL Signal Level Compatible Inputs and
Outputs
Single 5V ± 10% Power Supply
Multiprocessor and Co-processor Capability
Available in:
– 68-Lead Quad Pack (Leaded Chip Carrier)
Space Radiation Tolerant
- Absolute latch up immunity
- Total Dose: > 100K Rad/Si
- SEU Tolerance
< 10-10 errors per day
GENERAL DESCRIPTION
The P1750AE/SOS is a general purpose, single chip, 16bit CMOS/SOS microprocessor designed for high
performance floating point and integer arithmetic, with
extensive real time environment support. It offers a variety
of data types, including bits, bytes, 16-bit and 32-bit
integers, and 32-bit and 48-bit floating point numbers. It
provides 13 addressing modes, including direct, indirect,
indexed, based, based indexed and immediate long and
short, and it can access 2 MWords memory.
The P1750AE/SOS offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer, floating point, integer-to-floating point and floating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions such
as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, as well as supports executive and user
modes, and provides an escape mechanism which allows
user-defined instructions, using a coprocessor.
The chip includes an array of real time application support
resources, such as 2 programmable timers, a complete
interrupt controller supporting 16 levels of prioritized
internal and external interrupts, and a faults and exceptions
handler controlling internally and externally generated
faults.
The P1750AE/SOS uses a single multiplexed 16-bit parallel
bus. Status signals are provided to determine whether
the processor is in the memory or I/O bus cycle, reading
and writing, and whether the bus cycle is for data or
instructions.
The P1750AE/SOS is fabricated using insulated substrate
silicon on sapphire technology to provide absolute immunity
from destructive latch up caused by natural space radiation
as well as increased total dose and SEU tollerance.
Document # MICRO-7 REV B
Revised August 2005
P1750AE/SOS
P1750A, P1750A/SOS, P1750AE, &
P1750AE/SOS PROCESSORS
Pyramid Semiconductor offers four single chip MIL-STD1750A Processors. Two of these processors, the P1750A
and the P1750AE are manufactured with industry standard
CMOS Technology. The P1750A/SOS and the P1750 AE/
SOS are derivatives of the P1750A and P1750AE and are
manufactured with insulated substrate Silicon on Sapphire,
CMOS/SOS Technology to provide absolute immunity
from destructive latch up caused by the exposure of a
space vehicle to natural space radiation.
The P1750AE is architecturally more efficient than the
P1750A and provides higher throughput at the same clock
frequency. All four processors are mechanically
interchangeable, they have the same pinouts. The
processors are electrically interchangeable as long as the
specification limits for the slowest processor in the
interchangeability matrix are not violated. All four processors
are stand alone single chip, fully compliant MIL-STD1750A Processors.
the SOS Processor are utilized in the design. Processors
manufactured with SOS Technology have higher power
requirements and, for some signals, longer delays than the
standard CMOS Processors. However, both the CMOS
and CMOS/SOS Processors operate the MIL-STD-1750A
Instructions with the same number of clocks.
In space, CMOS/SOS provides absolute immunity from
destructive Single Event Latchup which can occur when
high energy ionizing particles, found naturally in space,
enter the space craft when passing through an integrated
circuit, these particles introduce enough charge in standard
CMOS devices to cause a destructive internal short circuit
from the device power supply through the standard CMOS
substrate to ground. This latchup current can be more than
the integrated circuit can safely carry and the device is
either severely weakened reducing its operational life time
or is immediately destroyed.
The P1750AE is a second generation MIL-STD-1750A
Processor that has been designed as a direct ("plug in")
electrical, mechanical, and software compatible
replacement for the P1750A. The P1750A and the P1750AE
are also proven replacements for other MIL-STD-1750A
Processors that are no longer available. The P1750AE has
been application proven in a number of critical applications
aboard a wide range of platforms including combat aircraft,
helicopters, submarines, surface vehicles, and satellites.
The P1750AE operates the MIL-STD-1750A Instruction
Set in fewer "clocks" than the P1750A. Depending upon
the number of arithmetic instructions used, the P1750AE
can easily provide more than 3X the throughput of the
P1750A at the same clock frequency with the same
operational software; see Tables 1 and 2. The P1750A and
P1750AE have the same bus cycle. Basic execution
instructions such as add/subtract, set/test/reset bit, load
& store, byte manipulation, logical OR/NAND/AND, etc. all
execute with the same number of "clocks" in both the
P1750A and P1750AE. The standard CMOS P1750A and
P1750AE are specified by DSCC SMD 5962-87665.
The P1750A/SOS and P1750AE/SOS are derivatives of
the P1750A and P1750AE. These SOS processors are
targeted for use aboard space vehicles and are manufactured
with insulated substrate Silicon on Sapphire (SOS)
Technology so as to provide high tolerance to the natural
space radiation environment which can degrade or destroy
standard CMOS Technology processors. The space
radiation tolerance for the P1750AE/SOS is shown in
Table 4. The P1750A/SOS is interchangeable with the
P1750A and the P1750AE/SOS is interchangeable with
the P1750AE provided that the electrical specifications for
Document # MICRO-7 REV B
Page 2 of 22
P1750AE/SOS
DIFFERENCES BETWEEN THE P1750A AND P1750AE
The P1750AE achieves a 40% boost in performance (in clock cycles) over the P1750A. This reduction in clocks per
instruction is because of three architectural enhancements:
1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with the
CPU's peripheral chips).
3) Branch calculation logic.
Table 1. P1750A vs. P1750AE
# of "Clocks" Required to Execute Selected Instructions
P1750A
# of Clocks
P1750AE
# of Clocks
Integer Multiply
23
4
5.75
Compare Between Limits
24
20
1.2
Flt. Point Add/Subtract
28
18
1.56
Flt. Point Multiply
43
9
4.78
Flt. Point Compare
6
4
1.5
Convert Flt. Point To Integer
22
16
1.38
Shift Logical Left/Right
9
6
1.5
Exchange
6
4
1.5
Branch
12
8
1.5
Instruction
Throughput Increase
(1)
Note:
1. Number of P1750A Clocks divided by number of P1750AE Clocks.
Table 2. P1750AE BUILT-IN FUNCTIONS
A core set of additional instructions has been included in the PACE1750AE. These instructions utilize the Built-In
Function (BIF) opcode space. The objective of these new opcodes is to enhance the performance of the 1750AE in
critical application areas such as navigation, DSP, transcendentals, and other LINPAK and matrix instructions.
Below is a list of the BIFs and their execution times (N = the number of elements in the vector being processed).
Address
Number of
Instruction
Memory Parametric Dot Product - Single
Mnemonic
VDPS
Mode
4F3(RA)
Clocks
10+8
Notes
Interruptable
Memory Parametric Dot Product - Double
VDPD
4F1(RA)
10+16N
Interruptable
3 x 3 Register Dot Product
R3DP
4F03
6
Double Precision Multiply Accumulate
MACD
4F02
8
N-2
N
Polynomial
POLY
4F06
Clear Accumulator
CLAC
4F00
4
Store Accumulator (32-Bit)
STA
4F08
7
Store Accumulator (48-Bit)
STAL
4F04
11
Load Accumulator (32-Bit)
LAC
4F05
9
Load Accumulator Long (48-Bit)
LACL
4F07
9
MMPG
4F0F
16+8N
Load Timer A Reset Register
LTAR
4F0D
4
Load Timer B Reset Register
LTBR
4F0E
4
Move MMU Page Block
Document # MICRO-7 REV B
7
Privileged
Page 3 of 22
P1750AE/SOS
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage Range
-0.5V to +7.0V
Input Voltage Range
-0.5V to VCC +0.5V
Storage Temperature Range
-65°C to +150°C
Input Current Range
-30mA to +5mA
Voltage applied to Inputs
-0.5V to VCC +0.5V
Current applied to Output3
150 mA
Maximum Power Dissipation2
1.5W
MAXIMUM CONTINUOUS OPERATING
RANGE
Case Temperature
GND
VCC
-55°C to +125°C
0
4.5V to +5.5V
SPACE RADIATION TOLERANCE
Requirement
Specification
Comment
Total Dose
(Ionizing Radiation)
≥ 100 K Rads
MIL-STD-883 TM 1019 Cond. B Processor
meets all data sheet specification limits
following exposure to ≥ 100K Rad (Si).
Single Event Upset
(SEU)
< 10-10 Errors
per day
Adams 90% worst case cosmic Ray
environment upset rate calculated with
creme.
Absolute
Immunity
CMOS/SOS Technology eliminates the
latchup mechanism.
Single Event
Latchup (SEL)
(Si)
NOTES:
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2. Must withstand the added power dissipation due to short circuit
test e.g., los.
3. Duration: 1 second or less.
Document # MICRO-7 REV B
Page 4 of 22
P1750AE/SOS
DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions)
Symbol
Parameter
Min
Max
Unit
VIH
Input HIGH Level Voltage
2.0
VCC + 0.5
V
VIL
Input LOW Level Voltage2
–0.5
0.8
V
VOH
Output HIGH Level Voltage
VOL
Output LOW Level Voltage
Conditions1
2.4
V
VCC = 4.5V
IOH = –8.0mA
VCC – 0.2
V
VCC = 4.5V
IOH = –300µA
0.5
V
VCC = 4.5V
IOL = 8.0mA
0.2
V
VCC = 4.5V
IOL = 300µA
100
µA
VIN = VCC, VCC = 5.5V
IIH2
Input HIGH Level Current,
IB0 – IB15,
BUS BUSY, BUS LOCK
100
µA
VIN = VCC, VCC = 5.5V
IIL1
Input LOW Level Current,
except IB0 – IB15,
BUS BUSY, BUS LOCK
–50
µA
VIN = GND, VCC = 5.5V
IIL2
Input LOW Level Current,
IB0 – IB15,
BUS BUSY, BUS LOCK
–50
µA
VIN = GND, VCC = 5.5V
IOZH
Output Three-State Current
50
µA
VOUT = 2.4V, VCC = 5.5V
IOZL
Output Three-State Current
–50
µA
VOUT = 0.5V, VCC = 5.5V
ICCQC
Quiescent Power Supply
Current (CMOS Input
Levels)
25
mA
VIN < 0.2V or < VCC – 0.2V,
f = 0MHz, Outputs Open,
VCC = 5.5V
ICCQT
Quiescent Power Supply
Current (TTL Input
Levels)
100
mA
VIN < 3.4V, f = 0MHz,
Outputs Open,
VCC = 5.5V
ICCD
Dynamic Power
20 MHz
140
mA
VIN = 0V to VCC, tr = tf = 2.5 ns,
Supply Current
25 MHz
150
mA
Outputs Open,
30 MHz
160
mA
VCC = 5.5V
mA
VOUT = GND, VCC = 5.5V
Input HIGH Level Current,
IIH1
except IB0 – IB15,
BUS BUSY, BUS LOCK
IOS
Output Short Circuit Current3
CIN
Input Capacitance
10
pF
COUT
Output Capacitance
15
pF
CI/O
Bi-directional Capacitance
15
pF
–25
Notes
1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. VIL = –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
Document # MICRO-7 REV B
Page 5 of 22
P1750AE/SOS
SIGNAL PROPAGATION DELAYS
1,2
20 MHz
Symbol
Parameter
Min
25 MHz
Max
Min
30 MHz
Max
Min
Max
Unit
tC(BR)L
BUS REQ
33
30
26
ns
tC(BR)H
BUS REQ
33
30
26
ns
tBGV(C)
BUS GNT setup
5
5
5
ns
tC(BG)X
BUS GNT hold
5
5
5
ns
tC(BB)L
BUS BUSY LOW
38
33
25
ns
tC(BB)H
BUS BUSY HIGH
38
33
25
ns
tBBV(C)
BUS BUSY setup
5
5
5
ns
tC(BB)X
BUS BUSY hold
5
5
5
ns
tC(BL)L
BUS LOCK LOW
38
34
32
ns
tC(BL)H
BUS LOCK HIGH
34
30
32
ns
tBLV(C)
BUS LOCK setup
tC(BL)X (IN) BUS LOCK hold
5
5
5
ns
5
5
5
ns
tC(ST)V
D/ I Status, AS0-AS3, AK0-AK3,
M/ IO, R/ W
tC(ST)X
M/ IO, R/ W, D/ I Status,
AS0-AS3, AK0-AK3
tC(SA)H
STRBA HIGH
24
20
18
ns
tC(SA)L
STRBA LOW
24
20
18
ns
tSAL(IBA)X Address hold from STRBA LOW
32
32
0
28
28
0
25
25
0
ns
ns
ns
5
5
5
ns
tRAV(C)
RDYA setup
5
5
5
ns
tC(RA)X
RDYA hold
5
5
5
ns
tC(SDW)L
tC(SD)H
STRBD LOW write
24
20
18
ns
STRBD HIGH
24
20
18
ns
24
20
18
ns
tFC(SDR)L STRBD LOW read
tSDRH(IBD)X STRBD HIGH
0
0
0
ns
tSDWH(IBD)X STRBD HIGH
28
27
25
ns
tSDL(SD)H STRBD write
28
26
24
ns
tRDV(C)
RDYD setup
5
5
5
ns
tC(RD)X
RDYD hold
5
5
5
ns
tC(IBA)V
IB0-IB15
tFC(IBA)X
IB0-IB15
tIBDRV(C) IB0-IB15 setup
36
32
28
ns
0
0
0
ns
5
5
5
ns
tC(IBD)X
IB0-IB15 hold (read)
5
5
5
ns
tC(IBD)X
Data valid out (write)
0
0
0
ns
Document # MICRO-7 REV B
Page 6 of 22
P1750AE/SOS
SIGNAL PROPAGATION DELAYS
1,2
(continued)
20 MHz
Unit
34
32
ns
34
30
28
ns
TRIGO RST
34
30
28
ns
tRSTL(DMA ENL) DMA enable
44
40
38
ns
tC(DME)
DMA enable
44
40
38
ns
tFC(NPU)
Normal power up
44
40
38
ns
Clock to major error unrecoverable
60
55
52
ns
RESET
50
45
40
ns
Parameter
Max
tFC(IBD)V
IB0-IB15
38
tC(SNW)
SNEW
tFC(TGO)
tC(ER)
tRSTL(NPU)
Min
30 MHz
Max
Symbol
Min
25 MHz
Max
Min
tREQV(C)
Console request
0
0
0
ns
tC(REQ)X
Console request
15
15
15
ns
tFV(BB)H
Level sensitive faults
5
5
5
ns
tBBH(F)X
Level sensitive faults
5
5
5
ns
tIRV(C)
IOL1-2INT user interrupt (0-5) setup
0
0
0
ns
tC(IR)X
Power down interrupt level sensitive
hold
15
15
15
ns
25
25
20
ns
tRSTL (tRSTH) Reset pulse width
tC(XX)Z
tf(F), t1(1)
tr, tf
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
24
5
20
5
5
18
5
4
ns
ns
3
ns
Notes
1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third
in parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is
referenced. When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" valid, "Z" - high impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
3. Functional test shal consist of the same functional test patterns used when testing the equivalent standard CMOS SMD 5962-87665
processor.
Document # MICRO-7 REV B
Page 7 of 22
P1750AE/SOS
MINIMUM WRITE BUS CYCLE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Document # MICRO-7 REV B
Page 8 of 22
P1750AE/SOS
MINIMUM READ BUS CYCLE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Document # MICRO-7 REV B
Page 9 of 22
P1750AE/SOS
MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Document # MICRO-7 REV B
Page 10 of 22
P1750AE/SOS
TRIGO RST DISCRETE TIMING DIAGRAM
DMA EN DISCRETE TIMING DIAGRAM
NORMAL POWER UP DISCRETE TIMING DIAGRAM
XIO OPERATIONS
SNEW DISCRETE TIMING DIAGRAM
Note:
All time measurements on active signals relate to the 1.5 volt level.
Document # MICRO-7 REV B
Page 11 of 22
P1750AE/SOS
EXTERNAL FAULTS AND INTERRUPTS TIMING DIAGRAM
Edge-sensitive interrupts and faults (SYSFLT0,
SYSFLT1) min. pulse width
Level-sensitive interrupts
Note:
tC(IR)X max = 35 clocks
Level-sensitive faults
Note:
All time measurements on active signals relate to the 1.5 volt level.
CON REQ
Document # MICRO-7 REV B
Page 12 of 22
P1750AE/SOS
BUS ACQUISITION
Note:
A CPU contending for the BUS, will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked (BUS
LOCK is high).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State)
Three-State
Note:
All time measurements on active signals relate to the 1.5 volt level.
Parameter
V0
VMEA
tPLZ
≥ 3V
0.5V
tPHZ
0V
VCC – 0.5V
tPXL
VCC/2
1.5V
tPXH
VCC/2
1.5V
Document # MICRO-7 REV B
Page 13 of 22
P1750AE/SOS
P1750 AE/SOS Terminal Connections
Case Types - QL and QG
Document # MICRO-7 REV B
Page 14 of 22
P1750AE/SOS
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
A single phase input clock signal (0-30 MHz, 40 percent to 60 percent
duty cycle.
TIMER CLK
Timer clock
A 100 kHz input that, after synchronization with CPU CLK provides the
clock for timer A and timer B. If timers are used, the CPU CLK signal
frequency must be > 300 kHz.
RESET
Reset
An active LOW input that initializes the device.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt
An interrupt request input that cannot be masked or disabled. This
signal is active on the positive going edge or the high level, according to
the interrupt mode bit in the configuration register.
USR0INT USR5INT
User interrupt
Interrupt request input signals that are active on the positive going
edge or the high level, according to the interrupt mode bit in the
configuration register.
IOL1INT
IOL2INT
I/O level interrupts
Active HIGH interrupt request inputs that can be used to expand the
number of user interrupts.
Mnemonic
Name
Description
MEM PRT ER
Memory protect error
An active LOW input generated by the MMU or BPU, or both and
sampled by the BUS BUSY signal into the Fault Register (bit 0 CPU bus
cycle, bit 1 if non-CPU bus cycle).
MEM PAR ER
Memory parity error
An active LOW input sampled by the BUS BUSY signal into bit 2 of the
fault register.
EXT ADR ER
External address
error
An active LOW input sampled by the BUS BUSY signal into the Fault
register (bit 5 or 8), depending on the cycle (memory or I/O).
SYSFLT0
SYSFLT1
System fault 0,
System fault 1,
Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT0)
or bits 13 and 15 (SYSFLT1) in the Fault register.
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major.
FAULTS
ERROR CONTROL
Document # MICRO-7 REV B
Page 15 of 22
P1750AE/SOS
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
D/l
Data or instruction
An output signal that indicates whether the current bus cycle access is
for Data (HIGH) or Instruction (LOW). It is three-state during bus cycles
not assigned to this CPU. This line can be used as an additional
memory address bit for systems that require separate data and program
memory.
R/W
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOW indicates a write or output operation. The signal is three-state
during bus cycles not assigned to this CPU.
M/IO
Memory or I/O
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to this CPU.
STRBA
Address strobe
An active HIGH output that can be used to externally latch the memory
or I/O address at the high-to-low transition of the strobe. The signal is
three-state during bus cycles not assigned to this CPU.
RDYA
Address ready
An active HIGH input that can be used to extend the address phase of a
bus cycle. When RDYA is not active wait states are inserted by the
device to accommodate slower memory or I/O devices.
STRBD
Data strobe
An active LOW output that can be used to strobe data in memory and
XIO cycles. This signal is three-state during bus cycles not assigned to
this CPU.
RDYD
Data ready
An active HIGH input that extends the data phase of a bus cycle. When
RDYD is not active, wait states are inserted by the device to
accommodate slower memory or I/O devlces.
INFORMATION BUS
Mnemonic
Name
Description
IB0 - IB15
Information bus
A bidirectional time-multiplexed address/data bus that is three-state
during bus cycles not assigned to this CPU. IB0 is the most significant
bit.
Mnemonic
Name
Description
AK0 - AK3
Access key
Outputs used to match the access lock in the MMU for memory
accesses (a mismatch will cause the MMU to pull the MEM PRT ER
signal LOW), and also indicates processor state (PS). Privileged
instructions can be executed with PS = 0 only. These signals are
three-state during bus cycles not assigned to this CPU.
AS0 - AS3
Address state
Outputs that select the page register group in the MMU. It is threestate during bus cycles not assigned to this CPU. [These outputs
together with D/l can be used to expand the device direct addressing
space to 4 MBytes, in a nonprotected mode (no MMU)]. However,
using this addressing mode may produce situations not specified in
MIL-STD-1750A.
STATUS BUS
Document # MICRO-7 REV B
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P1750AE/SOS
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION
Mnemonic
Name
Description
BUS REQ
Bus request
An active LOW output that indicates the CPU requires the bus. It
becomes inactive when the CPU has acquired the bus and started the
bus cycle.
BUS GNT
Bus grant
An active LOW input from an external arbiter that indicates the CPU
currently has the highest priority bus request. If the bus is not used
and not locked, the CPU may begin a bus cycle, commencing with the
next CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz),
three-stating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA,
STRBD), and all the other lines that go three-state when this CPU
does not have the bus.
BUS BUSY
Bus busy
An active LOW, bidirectional signal used to establish the beginning and
end of a bus cycle. The trailing edge (low-to-high transition) is used for
sampling bits into the fault register. It is three-state in bus cycles not
assigned to this CPU. However, the CPU monitors the BUS BUSY line
for latching non-CPU bus cycle faults into the fault register.
BUS LOCK
Bus lock
An active LOW, bi-directional signal used to lock the bus for successive
bus cycles. During non-locked bus cycles, the BUS LOCK signal
mimics the BUS BUSY signal. It is three-state during bus cycles not
assigned to this CPU. The following instructions will lock the bus:
INCM, DECM, SB, RB, TSB, SRM, STUB and STLB.
DISCRETE CONTROL
Mnemonic
Name
Description
DMA EN
Direct memory
Access enable
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
NML PWRUP
Normal power up
An active HIGH output that is set when the CPU has successfully
completed the built-in self test in the initialization sequence. It can be
reset by the I/O command RNS.
SNEW
Start new
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle.
TRIGO RST
Trigger-go reset
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
Document # MICRO-7 REV B
Page 17 of 22
P1750AE/SOS
ORDERING INFORMATION
Document # MICRO-7 REV B
Page 18 of 22
P1750AE/SOS
CASE OUTLINE 1:
68 Lead Quad Pack with Straight Leads (Ordering Code QL)
Inches
.002
.003
.006
.010
.015
.018
.050
.060
.080
.095
.225
.570
.800
.955
mm
0.05
0.08
0.15
0.25
0.38
0.45
1.27
1.52
2.03
2.41
5.72
14.48
20.32
24.25
NOTES:
1)
2)
3)
4)
5)
Dimensions are in inches.
Metric equivalents are given for general information only.
Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner.
Corners indicated as notched may be either notched or square.
Document # MICRO-7 REV B
Page 19 of 22
P1750AE/SOS
CASE OUTLINE 2:
68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)
Inches
.003
.010
.015
.018
.020
.050
.570
.800
.955
1.230
mm
0.08
0.25
0.38
0.45
0.51
1.27
14.48
20.32
24.25
31.26
NOTES:
1)
2)
3)
4)
5)
6)
Dimensions are in inches.
Metric equivalents are given for general information only.
Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner.
Corners indicated as notched my be either notched or square (with radius).
Case 2 is derived from Case 1 by forming the leads to the shown gullwing configuration.
Document # MICRO-7 REV B
Page 20 of 22
P1750AE/SOS
LEAD FORM DETAIL
Symbol
INCHES
Min
Max
A
0.048
0.090
A1
0.011
0.031
B
0.016
0.021
C
0.004
0.008
e1
0.050 BSC
D
1.210
1.250
D1
0.945
0.965
D2
0.800 BSC
E
1.210
1.250
E1
0.945
0.965
E2
0.800 BSC
L*
0.270 Nominal
L0
0.120
0.210
L3
0.040
0.050
L4
0.086
0.109
R1
0.018
0.020
R2
0.018
0.020
Φ1
Φ2
4°
8°
A0**
-1°
7°
0.141
* Lead length in the straight lead configuration, prior to leadforming (used for all test and in-process WIP operations).
** Measured from the highest of the top of the leads or the top of the lid.
Document # MICRO-7 REV B
Page 21 of 22
P1750AE/SOS
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
MICRO-7
PACE1750AE SOS 16-BIT PROCESSOR
REV.
ISSUE
DATE
ORIG. OF
CHANGE
ORIG
May-89
RKK
New Data Sheet
A
Jul-04
JDB
Added Pyramid logo
B
Aug-05
JDB
Re-created electronic version
Document # MICRO-7 REV B
DESCRIPTION OF CHANGE
Page 22 of 22