PACE1754/SOS PROCESSOR INTERFACE CIRCUIT (PIC) CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processors. It eliminates the SSI/MSI Logic and external system functions required in typical 1750A implementations. Single 5V ± 10% Power Supply Available in: — 68-Lead Quad Pack with optional Gull Wing Surface Mount Provides a significant savings in part-count and power dissipation enhancing reliability and overall system speed performance. Provides an optimal interface when used with the PACE1753 MMU/COMBO in a full 1750A implementation. Provides the following additional important system functions: — Programmable READY for memory and I/O — Automatic READY during self-test and internal I/O instructions — 100KHz timer clock output provided — Programmable system watchdog—ranges from 1 µs to 1 minute — Programmable Bus time-out function — Memory Parity generation/detection — Error detection of unimplemented memory and/or I/O space addressing — First failing memory address register for diagnostics — High drive three-state address latches — Built-in system test program—automatically tests the PACE1750A/AE CPUs, PACE1753 MMU/COMBO, PACE1754 PIC and system address lines as well as memory and I/O strobes — System configuration decoding and buffering — Interrupt acknowledge decoder and strobe — Start up ROM support per MIL-STD-1750A — Memory or I/O READ/WRITE three-state strobes with external three-state control for DMA applications Available with Class S manufacturing, screening, and testing. SOS insulated substrate technology provides absolute latch-up immunity and excellent SEU tolerance. SOS devices are fully interchangeable with application-proven SMD CMOS P1754 devices. 20, 25 and 30 MHz operation over full Military Temperature Range PACE1754 PROCESSOR INTERFACE CIRCUIT DESCRIPTION The PACE1754 Processor Interface Circuit (PIC) is a single chip implementation of many special system functions that are often required when using the PACE1750A/AE, a single chip microprocessor. The PIC allows a system designer to design a higher performance, more effecient microprocessor system which uses less power and takes up less board space. The PIC provides many important system functions. These functions are governed by respective bit positions in a programmable Control Register which is incorporated in the PIC. The individual bits of the control register are set to select the various features and are set to a specified default value upon Reset. Document # MICRO-9 REV B Revised August 2005 PACE1754/SOS ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to VCC + 0.5V Storage Temperature Range –65°C to +150°C Input Current Range –30mA to +5mA Current applied to any output3 150mA Maximum Power Dissipation2 1.5W Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance (θJC): Packages QL and QG 8°C/W RECOMMENDED OPERATING CONDITIONS Case Temperature GND VCC –55°C to +125°C 0 4.5V to +5.5V Notes: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. Document # MICRO-9 REV B Page 2 of 16 PACE1754/SOS DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions1 VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V VCC = 4.5V, IIN = –18mA VOH Output HIGH Voltage 2.4 V VCC = 4.5V, IOH = –8.0mA VCC – 0.2 V VIN = 0.8V, 2.0V IOH = –300µA VOL VOL IIH Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 8.0mA except A0 – A15 0.2 V VIN = 0.8V, 2.0V IOL = 300µA Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 20.0mA A0 – A15 0.2 V VIN = 0.8V, 2.0V IOL = 300µA 300 µA VIN = VCC, VCC = 5.5V Input HIGH Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBA IIH Input HIGH Current, IB0 – IB15, parity/IB16, A0/EXT AD0, A1/EXT AD1 100 µA IIH Input HIGH Current, STRBA, SING ERR 300 µA –50 µA IIL Input LOW Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBD, TEST ON VIN = VCC, VCC = 5.5V VIN = VCC, VCC = 5.5V VIN = GND, VCC = 5.5V IIL Input LOW Current, IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1 –50 µA IIL Input LOW Current, STRBD, TEST ON 300 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels) 25 mA VIN < 0.2V or > VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V ICCQT Quiescent Power Supply Current (TTL Input Levels) 100 mA VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V ICCD VIN = GND, VCC = 5.5V Dynamic Power f = 20MHz 90 mA VIN = 0V to VCC, Supply Current f = 25MHz 100 mA tr = tf = 2.5 ns typ., f = 30MHz 125 mA Outputs Open, VCC = 5.5V mA VOUT = GND, VCC = 5.5V IOS Output Short Circuit Current2 CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional Capacitance 15 pF Outputs Only (Including I/O Buffers) –25 Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-9 REV B Page 3 of 16 PACE1754/SOS AC ELECTRICAL CHARACTERISTICS1, 2 (VCC = 5V ± 10% Over Recommended Operating Conditions) 20 MHz Symbol Parameter Min Max 25MHz Min Max 30 MHz Min Max Unit tEX RDY (RDYD)V Time from External Ready to Ready Data Valid 19 15 14 ns tC (RDYD)V Time from Clock Read to Ready Data Valid 29 25 23 ns tSTRBAH (A)V Time from Strobe Address HIGH to Address Bus Valid 29 25 23 ns tIBAV (A)V Time from Information Bus Address to Address Bus Valid 31 27 25 ns tFC (R)L Time from Falling Clock to Read LOW 25 21 19 ns tSTRBDH (R)H Time from Strobe Data HIGH to Read HIGH 25 21 19 ns tSTRBDL (W)L Time from Strobe Data LOW to Write LOW 27 23 21 ns tSTRBDH (W)H Time from Strobe Data HIGH to Write HIGH 27 23 21 ns tIBDIN (ME PA ER)L Time from Information Bus Data into Memory Parity Error LOW 24 20 18 ns tIBAIN (EX AD ER) Time from Information Bus Address into External Address Error 32 28 26 ns tSTRBDL – (STRT ROM)V Time from Strobe Data LOW to Start-up ROM Valid 27 23 21 ns tFC (IB OUT)V Time from Falling Clock to Information Bus Valid 32 28 26 ns tC (TIMER CLK) Time from Rising Edge of Clock to Timer Clock 32 28 26 ns tIB INV (IB16) Time from Information Bus Data to Parity Valid 26 23 21 ns tEXT AD (CLKB3) Extended Address Setup Time tEX RDY1 (RDYD)V Time from External Ready Data to Ready Data Valid 30 26 24 ns tSTRBDH (SCR EN) Time from STRBD HIGH to SCR Enable; 32 28 26 ns 10 10 10 ns Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All measurements of delay times on active signals are related to the 1.5V levels. Document # MICRO-9 REV B Page 4 of 16 PACE1754/SOS TERMINAL CONNECTIONS - PACKAGES QL AND QG Case Outlines Terminal Number Terminal Symbol U and Y Terminal Number Terminal Symbol Terminal Number Terminal Symbol 1 GND 24 IB12 47 A3 2 SC0 25 IB13 48 GND 3 SC1 26 IB14 49 A2 4 TEST ON 27 IB15 50 A1/EXT AD1 5 RESET 28 PARITY/IB16 51 A0/EXT AD0 6 TEST END 29 ME PA ER/RAM DIS 52 SC4 7 TIMER CLK 30 EX AD ER/SING ERR 53 SC3 8 SC2 31 INTA 54 TC 9 VCC 32 STRT ROM 55 CPU CLK 10 IB0 33 VCC 56 STRBA 11 IB1 34 GND 57 STRBD 12 IB2 35 A15 58 STRB EN 13 IB3 36 A14 59 EX RDY 14 IB4 37 A13 60 RDYD 15 lB5 38 A12 61 R/W 16 IB6 39 A11 62 GND 17 IB7 40 A10 63 M/IO 18 EX RDY1 41 A9 64 MEMW 19 IB8 42 A8 65 MEMR 20 IB9 43 A7 66 IOW 21 GND 44 A6 67 IOR 22 IB10 45 A5 68 VCC 23 IB11 46 A4 Document # MICRO-9 REV B Page 5 of 16 PACE1754/SOS STRT ROM Timer Clk IB Bus Output (0:15) EX AD ER Extended Addresses (0:1) Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-9 REV B Page 6 of 16 PACE1754/SOS RDYD Timing TEST END Timing1 Notes: 1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two fetch cycles from the "old PC" (from addresses XXXX & XXXX+1). The data will be taken from system memory (because TEST END is asserted) but both the address and data are irrelevent. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now from the system memory to start user's program execution. 2. All time measurements on active signals relate to 1.5V levels. Document # MICRO-9 REV B Page 7 of 16 PACE1754/SOS Address Bus and Strobes Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-9 REV B Page 8 of 16 PACE1754/SOS TEST CIRCUITS Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Parameter VO VMEA TPLZ ≥ 3V 0.5V TPHZ 0V VCC – 0.5V TPXL VCC/2 1.5V TPXH VCC/2 1.5V Document # MICRO-9 REV B Page 9 of 16 PACE1754/SOS PIN FUNCTIONS Symbol Name Description CPU CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) STRBA Strobe Address An active HIGH input which latches the contents of IB(0:15) into the address latches. STRBD Strobe Data An active LOW input which is used for writing or reading data to or from the device and also to produce the external memory and I/O strobes. TIMER CLK Timer Clock A 100KHz output (fixed frequency) based on the programmed operating frequency of the CPU clock. MEMW Memory Write Strobe An active LOW output produced in memory write cycles. MEMR Memory Read Strobe An active LOW output produced in memory read cycles. IOW I/O Write Strobe An active LOW output produced in output write cycles. IOR I/O Read Strobe An active LOW output produced in input read cycles. INTA Interrupt Acknowledge Strobe An active LOW output produced after any interrupt, corresponding to an output write to address 1000 (hex). SCR EN System Configuration An active LOW output (in 64 pin only) produced any time an input read from address 8410 (hex), read system configuration is executed. STRB EN Strobe Enable An active LOW input, enabling the active state of the address outputs and the MEMR, MEMQ, IOR, and IOW outputs. When at a logic "1" (if enabled by bits EST, EAD of the control register) it will correspondingly enable the three-state state of the above signals. IB0 - IB15 Information Bus (0:15) A bi-directional time multiplexed bus. It is an input during the address phase of any bus cycle and also during the data phase when writing. It is an output during the data phase when reading from the device. IB16 Information Bus (16) A bi-directional line. It is an output during write cycles and an input during read cycles. It is used to implement the parity function at the system level. A(0:1)/ EX AD(0:1), A(2:15) Address Bus (0:15) An active HIGH output bus. Contains the address of the current bus cycle as latched by the end of STRBA. In system configurations including the MMU function, the only active lines during memory are A(4:15). In this case, A(2:3) are high impedance (don't care) and A(0:1) turn into inputs called Extended Addresses, EXT ADR (0:1). In this case, these two lines supplied by the MMU, will be used to operate the programmable ready generation during bus cycles. M/IO Memory I/O An input qualifier indicating the nature of the current bus cycle. Document # MICRO-9 REV B Page 10 of 16 PACE1754/SOS PIN FUNCTIONS (Continued) Symbol Name Description R/W Read or Write An input qualifier indicating the nature of the current bus cycle, either Read (1) or Write (0). RESET External Reset An active LOW input used to initialize the device's hardware. TEST ON System Test Enable An active LOW input used to enable the execution of the System Test built into the device, immediately after completion of the P1750A/AE initialization and before fetching any instruction from the user program. TEST END System Test End An active HIGH output indicating whether the system test in the device has been completed. Whenever the system test is disabled by the TEST ON signal, the TEST END output will be at a logical "1" immediately after RESET is removed. STRT ROM Start Up ROM An output following the execution of the ESUR and DSUR, I/O commands as defined in MIL-STD-1750A. It will be at the logical "1" level after executing ESUR and at the logical "0" level after executing DSUR. Initially, it defaults to a logical "1". RDYD Ready Data An active HIGH output to be connected to the P1750A/AE input to control the bus cycle termination. EX RDY External Ready Data An active HIGH input which at logical "0" overrides the internal RDYD generation and forces it to a logical "0". EX RDY1 External Ready Data An active LOW input which at logical "1" overrides the internal RDYD generation and forces it to a logical "0". ME PA ER/ RAM DIS Memory Parity Error An active LOW output indicating a parity error when reading from memory. It becomes an active HIGH output called RAM DISABLE for handshaking with the P1753 MMU when the device is programmed to support EDAC. EX AD ER/ SING ERR Illegal Address Error An active LOW output indicating an illegal address error when referencing memory or I/O. It becomes an active HIGH output called SINGLE ERROR for handshaking with the P1753 MMU when the device is programmed to support EDAC. TC Terminal Count An active HIGH output indicating a Bus time out or a watchdog trigger. SC0–SC4 System Configuration Inputs which are buffered onto IB0–IB4 when executing an I/O read from I/O address 8410 (hex), system configuration. GND Ground 0 volts system ground. VCC Power Supply 5 volts ± 10% power supply. Document # MICRO-9 REV B Page 11 of 16 PACE1754/SOS Standardized Military Drawing Part Number Pyramid Semiconductor CAGE Number Pyramid Semiconductor Part Number 5962-8864201UX 3DTT2 P1754-20QLMB 5962-8864201YX 3DTT2 P1754-20QGMB 5962-8864201ZX 3DTT2 P1754-20PGMB 5962-8864202UX 3DTT2 P1754-30QLMB 5962-8864202YX 3DTT2 P1754-30QGMB 5962-8864202ZX 3DTT2 P1754-30PGMB 5962-8864203UX 3DTT2 P1754-40QLMB 5962-8864203YX 3DTT2 P1754-40QGMB 5962-8864203ZX 3DTT2 P1754-40PGMB 5962-8864204TX 3DTT2 P1754-20GMB 5962-8864204XX 3DTT2 P1754-20CMB 5962-8864205TX 3DTT2 P1754-30GMB 5962-8864205XX 3DTT2 P1754-30CMB 5962-8864206TX 3DTT2 P1754-40GMB 5962-8864206XX 3DTT2 P1754-40CMB ORDERING INFORMATION Document # MICRO-9 REV B Page 12 of 16 PACE1754/SOS CASE OUTLINE 1: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .003 .006 .010 .015 .018 .050 .060 .080 .095 .225 .570 .800 .955 mm 0.05 0.08 0.15 0.25 0.38 0.45 1.27 1.52 2.03 2.41 5.72 14.48 20.32 24.25 NOTES: 1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square. Document # MICRO-9 REV B Page 13 of 16 PACE1754/SOS CASE OUTLINE 2: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .003 .010 .015 .018 .020 .050 .570 .800 .955 1.230 mm 0.08 0.25 0.38 0.45 0.51 1.27 14.48 20.32 24.25 31.26 NOTES: 1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case 2 is derived from Case 1 by forming the leads to the shown gullwing configuration. Document # MICRO-9 REV B Page 14 of 16 PACE1754/SOS LEAD FORM DETAIL Symbol INCHES Min Max A 0.048 A1 0.011 0.031 B 0.016 0.021 C 0.004 0.008 e1 0.090 0.050 BSC D 1.210 1.250 D1 0.945 0.965 D2 0.800 BSC E 1.210 1.250 E1 0.945 0.965 E2 L* 0.800 BSC 0.270 Nominal L0 0.120 0.210 L3 0.040 0.050 L4 0.086 0.109 R1 0.018 0.020 R2 Φ1 0.018 0.020 4° 8° Φ2 A0** -1° 7° 0.141 * Lead length in the straight lead configuration, prior to leadforming (used for all test and in-process WIP operations). ** Measured from the highest of the top of the leads or the top of the lid. Document # MICRO-9 REV B Page 15 of 16 PACE1754/SOS REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-9 PACE1754/SOS MMU/COMBO REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version Document # MICRO-9 REV B DESCRIPTION OF CHANGE Page 16 of 16