2015 DSPIS IP Core Serial Peripheral Interface – Slave v. 1.05 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we’re designing solutions tailored to your needs. IP CORE OVERVIEW The DSPIS is a fully configurable SPI slave device, designed to run with passive devices like memories, LCD drivers etc. It allows you to configure polarity and phase of a serial clock signal SCK. A serial clock line (SCK) synchronizes information shifting and sampling on two independent serial data lines. Moreover, data is simultaneously transmitted and received. The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. A clock control logic (CLK/4) allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low), the first portion of data is copied to the address register and then to the ADDRESS bus output. After transmission of the address, the DSPIS generates the read signal (RD) and copies DATAI bus contents to the transmitter shift register and prepares data to be exchanged with SPI Master. During next data portion transmission, the DSPIS simultaneously transfers data out and in. When first data portion is received, the DSPIS asserts DATAO bus, generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepares another data portion to be exchanged with the SPI master. Transmission is ended when the SS line goes high. The DSPIS is a technology independent and can be implemented in various process technologies. It includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. FEATURES ● SPI Slave ○ Slave operation ○ Automatic read and write operations ○ Automatic address incrementation after any data portion transfer ○ Configurable address and data length. ○ Configurable SCK phase and polarity. ○ Supports speeds up ¼ of system clock ○ Simple interface allows easy connection to passive devices, and SPI Master ● Fully synthesizable, static synchronous design with no internal tri-states LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist 1 Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. PINS DESCRIPTION PIN clk rst datai(D:0) cpha cpol sck si ss datao(D:0) addres(A:0) rd we so TYPE input input input input input input input input output output output output output BLOCK DIAGRAM DESCRIPTION Global clock Global reset Data bus input SCK clock phase SCK clock polarity SPI serial clock SPI serial data input Slave select Data bus output Address bus output Read output Write enable Slave serial data output clk rst cpha cpol sck SPI Clock Logic MSB so Shift Reg. Data reg. datai LSB SPI Controller Adr. reg. si ss datao address we rd TRANSFER FORMATS The software can select any of four combinations of serial clock (SCK) phase and polarity, using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI, allows direct interface to almost any existing synchronous serial peripheral. SCK CYCLE# 1 2 MSB 6 6 3 4 5 6 7 8 5 4 3 2 1 LSB 5 4 3 2 1 SCK (CPOL=0) SCK (CPOL=1) MOSI MISO MSB LSB SS SCK CYCLE# 1 2 3 4 5 6 7 8 LSB SCK (CPOL=0) SCK (CPOL=1) MOSI MISO MSB MSB 6 5 4 3 2 1 6 5 4 3 2 1 LSB SS 2 Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. TYPICAL SPI BUS CONNECTION The figure below shows typical connection of the DSPIS Core to SPI Bus, controlled by SPI master and passive SPI devices. VDD RP RP RP MISO MOSI SCK 3*RS NOR data Slave device tri-state buffer Pasive device 8 2 uC 3*RS addr cs rd wr irq datao mi datai addr so cs rd we irq system clk system rst so open drain si DSPI mo address datai si datao sck addr datao datai rd rd we wr open drain ss DSPIS scki clk rst scko tris cpha cpol sckz DSPI ASIC/FPGA chip ss7o-ss0o ss DELIVERABLES ♦ Source code: ● VHDL Source Code or/and ● VERILOG Source Code or/and ● Encrypted, or plain text EDIF ♦ VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros ● ModelSim automatic simulation macros ● Tests with reference responses ♦ Technical documentation ● Installation notes ● HDL core specification ● Datasheet ♦ ♦ ♦ Synthesis scripts Example application Technical support ● IP Core implementation support ● 3 months maintenance ● Delivery of the IP Core and documentation updates, minor and major versions changes ● Phone & email support UNITS SUMMARY SPI Clock logic Controls phase and polarity of the SCK clock line. In the same time it detects correct sample and shift edge for the Shift register. SPI Clock Logic allows user to select any of four combinations of serial clock (SCK) phase and polarity using two pins CPHA and CPOL. The clock polarity is specified by the CPOL, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase CPHA selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPIS allows direct interface to almost any existing synchronous serial peripheral. 3 Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. Shift register – It is the central element in the SPI system. When SPI transfer occurs, an 8-bit character is shifted out on data pin while a different 8-bit character is simultaneously moved in a second data pin. Another way to view this transfer is when an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16bit shift register. When a transfer occurs, this distributed shift register is moved 8-bit positions. Moreover, the characters in the master and slave are effectively exchanged. Data Register - Holds data read from passive device, to be sent serially to the SPI Master. Address Register Holds address presented on Address bus. Its contents is incremented every single data portion sent/received serially through the SPI bus. SPI Controller - Detects the beginning and end of SPI transfer. Manages data exchange between DSPIS and passive device controlled by DSPIS, and increment Address Register (SPAD) after any successful transfer. CONTACT For any modifications or special requests, please contact Digital Core Design or local distributors. DCD’s headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: : firstname.lastname@example.org tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: Please check: http://dcd.pl/sales PERFORMANCE The following table gives a survey about the Core performance in ALTERA® devices after Place & Route (all key features have been included): Speed grade Logic Cells Fmax CYCLONE Device -6 79 354 MHz CYCLONE2 -6 87 329 MHz STRATIX -5 79 386 MHz STRATIX2 -3 84 422 MHz STRATIXGX -5 79 382 MHz MERCURY -5 95 347 MHz EXCALIBUR -1 82 224 MHz APEX2A -7 82 320 MHz APEX20KC -7 82 241 MHz APEX20KE -1 82 202 MHz APEX20K -1 82 140 MHz ACEX1K -1 87 196 MHz FLEX10KE -1 87 204 MHz MAX2 -3 79 257 MHz MAX3K -5 57 114 MHz MAX7K -5 57 114 MHz Core performance in ALTERA® devices 4 Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.