ADCDS-1603

ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
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FEATURES
PRODUCT OVERVIEW
„ 2.3 MPPS
The ADCDS-1603 is an application-specific CCD
image converter designed for electronic-imaging
applications that employ CCD's (charge coupled
devices) as their photodetector. The ADCDS-1603
incorporates a "user configurable" input amplifier,
a CDS (correlated double sampler) and a 16-bit
resolution sampling A/D converter in a single
package, providing the user with a complete, high
performance, low-cost, low-power, integrated
solution.
„ Internal 16-bit resolution A/D
„ Internal correlated doubler sampler (CDS)
„ Resistor programmable gain adjustment
from 0dB to 15.5dB
„ 1.7 LSB RMS Noise @ 2.3MPPS
„ Low-Profile 44 Pin SMT Quad Pak or 40 Pin TDIP
„ Analog front end programmable bandwidth
„ Extended temperature range –40ºC to +100ºC
„ Low power, 645mW
„ Low cost, functionally complete
The key to the ADCDS-1603's performance is a
unique, high-speed, high-accuracy CDS circuit,
which eliminates the effects of residual charge,
charge injection and "kT/C" noise on the CCD's
output floating capacitor, producing a pixel data
output signal. The ADCDS-1603 digitizes this
resultant pixel data signal using a high-speed,
low-noise sampling A/D converter.
The ADCDS-1603 requires only the rising edge
of start convert pulse to initiate its conversion
process and a Reference Hold command to
acquire and hold the CCD reference level output.
Additional features of the ADCDS-1603 include
gain adjust, offset adjust, precision +2.048V
reference, and a programmable analog bandwidth
function. OVDD selectable 2.5V to 3.3V supply
voltage offered in Quad Pak version.
FUNCTIONAL BLOCK DIAGRAM
+5VA
–5VA
+5V D
499
INVERTING INPUT
100
INPUT AMPLIFIER
0.01μF
DIRECT INPUT
NON-INVERTING INPUT
5K 7
22pf
CORRELATED
DOUBLE
SAMPLER
BIT 1 (MSB)
SAMPLING
A/D
BIT 16 (LSB)
OFFSET ADJUST
REFERENCE HOLD
START CONVERT
TIMING
AND
CONTROL
+2.048V REFERENCE OUTPUT
DIGITAL GROUND
DATA VALID
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
ANALOG GROUND
AØ A1
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 1 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
ABSOLUTE MAXIMUM RATINGS
Parameters
Min.
Typ.
Max.
Units
Noise
A1
A0
–5V Supply
–6.5
–
+0.3
Volts
+5V Supply
–0.3
–
+6.5
Volts
DC Noise Gain = 1 (INV-IN = NC) ➀
Start Convert Rate
2.3 MHz
LO
LO
OVDD
–0.3
–
+3.8
Volts
1.7
53
LSB RMS
uV RMS
Digital Input
–0.3
–
Vdd+0.3V
Volts
1.8 MHz
LO
HI
Analog Input
–6
–
+6
Volts
1.5
48
LSB RMS
uV RMS
Lead Temperature
–
–
300
°C
1.0 MHz
HI
LO
1.3
41
LSB RMS
uV RMS
800 kHz
HI
HI
1.3
41
LSB RMS
uV RMS
DC Noise Gain = 5.99 (INV-IN = GND) ➀
Start Convert Rate
2.3 MHz
LO
LO
2.5
13
LSB RMS
uV RMS
1.8 MHz
LO
HI
2.0
10.8
LSB RMS
uV RMS
1.0 MHz
HI
LO
1.6
8.5
LSB RMS
uV RMS
800 kHz
HI
HI
1.6
8.5
LSB RMS
uV RMS
FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range, under the
following conditions: +5VA = +5V, OVDD = 3.3V, –5VA = –5V, sample rate = 2.3MHz.
Analog Input
Min.
Typ.
Max.
Units
Input Voltage Range (Reference
Signal - Pixel data Signal)
Gain of 5.99 (INV-IN to GND)
Gain of 1 (INV-IN Open)
–
–
–
–
0.342
2.048
V p-p
V p-p
Input Resistance
–
5000
–
Ohms
Input Capacitance
–
22
–
pF
Digital Inputs
Logic Levels
Logic 1 A0, A1
Logic 0 A0, A1
Logic 1 (REF HLD, START CON)
Logic 0 (REF HLD, START CON)
Logic Loading
Logic 1
Logic 0
4.5
–
+2.4
–
–
–
–
–
+Vdd
0.4
–
+0.8
Volts
Volts
Volts
Volts
–
–
–
–
+10
-10
uA
uA
Digital Outputs
Logic Levels
Logic 1 (0.5mA)
Logic 0 (0.5mA)
2.8
–
3.0
–
Logic Levels
Logic 1 (0.5mA)
Logic 0 (0.5mA)
4.5
–
5.0
–
Offset/Gain
Min.
Typ.
Max.
Units
Min.
Typ.
Max.
Units
Offset Error Gain = 1
+25°C
0 to 70°C
–40 to +100ºC
–
–
–
0.5
0.5
0.5
1
1
1.5
%FSR
%FSR
%FSR
Gain Error Gain = 1
+25°C
0 to 70°C
–40 to +100ºC
–
–
–
±0.5
±0.5
±0.5
±1
±1
±1.5
%FSR
%FSR
%FSR
3.3
+0.4
Volts
Volts
Bandwidth
Min.
Typ.
Max.
Units
+0.4
Volts
Volts
Input Amplifier –3db BW ➄
Input Common Mode Voltage
Output Voltage Swing
13.5
–3.5
–2.5
–
–
–
–
3.5
2.5
MHz
Volts
Volts
Reference
Linearity
Differential Nonlinearity
(Histogram, 98kHz)
+25°C
0 to 70°C
–40 to +100ºC
–0.90
–0.90
–0.98
±0.5
±0.5
±0.6
+1.2
+1.2
+2
LSB
LSB
LSB
Integral Nonlinearity
+25°C
0 to 70°C
–40 to +100ºC
–
–
–
±1
±1
±2
–
–
–
LSB
LSB
LSB
Guaranteed No Missing Codes
0 to 70°C
–40 to +100ºC
16
16
–
–
–
–
LSB
LSB
+25ºC
2.038
2.048
2.058
Volts
0 to +70ºC
2.038
2.048
2.058
Volts
-40 to +100ºC
2.028
2.048
2.068
Volts
0.2
mA
Reference Current
–
Signal Timing ➁
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
0.001
–
2.3➂
MHz
Conversion Time
434
–
–
nSec
Start Convert Pulse Width
300
–
–
nSec
Conversion Rate (–40 to 100°C)
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 2 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Power Requirements
Min.
Typ.
Max.
Units
Power Supply Range
+5V A Supply
–5V Supply
+5V D Supply ➃
OVDD Supply ➃
+4.75
–4.75
–4.75
2.3
+5.0
–5.0
+5.0
3.3
+5.25
–5.25
+5.25
3.6
Volts
Volts
Volts
Volts
Power Supply Currents
+5V Supply
–5V Supply
OVDD Supply
–
–
+78
–47
+10
+83
–52
+12
mA
mA
mA
Power Dissipation
–
645
680
mW
Power Supply Rejection
(5%) @25°C
–
±0.01
±0.03
3. Offset adjustment resistor (Figure 3), Rext (Figure 2b, 2c, & 2f),
and Rext1 & Rext2 (Figure 2d) should be placed as close to the
ADCDS-1603 as possible.
4. A0 and A1 (INV-IN = NC) should be bypassed with 0.1μf capacitors to
ground to reduce susceptibility to noise.
ADCDS-1603 MODES OF OPERATION
The input amplifier stage of the ADCDS-1603 provides the designer with
a tremendous amount of flexibility. The architecture of the ADCDS-1603
allows its input-amplifier to be configured in any of the following
configurations:
• Direct Mode (AC coupled)
• Non-Inverting Mode
• Inverting Mode
%FSR/%V
Environmental
Operating Temperature Range
ADCDS-1603
ADCDS-1603EX
0
–40
–
–
+70
+100
°C
°C
Storage Temperature
–65
–
+150
°C
Package Type
When applying inputs that are less than 2.048Vp-p, a coarse gain
adjustment (applying an external resistor to Inverting Input) must be
performed to ensure that the full scale pixel data input signal (saturated
signal) produces 2.048Vp-p signal at the input-amplifier's output (VOUT)
(See figure 2b & 2C).
In all three modes of operation, the pixel data portion of the signal at
the CDS input (i.e. input-amplifier's VOUT) must be more negative than its
associated reference level and VOUT should not exceed 2.048Vdc.
40-Pin, TDIP, 2.24"×1.27" FR4 PCB TDIP
44-Pin Quad Pak 0.99"x 0.99"×0.29
LCP Package, FR4 PCB
Weight
18.1 Grams
Pin Type
.025 diameter Au Plate, Copper Quad Pak
Cover (TDIP Package)
The ADCDS-1603 achieves its specified accuracies without the need for
external calibration. If required, the device's small initial offset error can be
reduced to zero using the OFFSET ADJUST feature (See figure 3). For fine
gain adjustment model, contact the factory.
Tin Plate Steel
DIRECT MODE (AC COUPLED)
This is the most common input configuration as it allows the ADCDS-1603
to interface directly to the output of the CCD with a minimum amount of
analog "front-end" circuitry. This mode of operation is used with full-scale
pixel data input signals from 0.342Vp-p to 2.048Vp-p.
➀ See Table 3.
➁ See Timing Specs, Table 2.
➂ See Technical Note: Optimal Performance.
➃ +5VD TDIP version, OVDD Quad Pak version. CMOS Output Loading
➄ A0, A1 = LO
TECHNICAL NOTES
Figure 2a. describes the configuration for applications using a pixel data
input signal with a maximum amplitude of 0.342Vp-p. In this case the input
amplifier is configured for the maximum gain of 5.99 (VOUT = 1+(499/100)).
All input resistors having a 0.1% tolerance.
1. Obtaining fully specified performance from the ADCDS-1603 requires
careful attention to pc-board layout and power supply decoupling.
The device's analog and digital grounds are connected to each other
internally. Depending on the level of digital switching noise in the overall
CCD system, the performance of the ADCDS-1603 may be improved by
connecting all ground pins to a large analog ground plane beneath the
package.
Figure 2b. describes the configuration for applications using a pixel
data input signal with an amplitude greater than 0.342Vp-p and less
than 2.048Vp-p. Using a single external series resistor, the coarse gain
of the ADCDS-1603 can be set. The coarse gain of the input amplifier
can be determined fron the following equation: VOUT = 2.048Vp-p = VIN*
(1+(499/(100+Rext))) (all internal resistors having a 0.1% tolerance).
2. Bypass all power supplies to ground with a 4.7μf ceramic capacitor in
parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to
the package as possible.
100
499
Rext
100
INV-IN
0.01μF
VIN
N.C.
VOUT
= 2.048Vp-p
Direct
NON-IN
Rext
499
100
INV-IN
5k
22pf
Figure 2a. Direct Mode
0.01μF
VIN
0.01μF
V OUT
= 2.048Vp-p
Direct
N.C. NON-IN
5k
N.C.
VIN
22pf
Figure 2b. Direct Mode
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
499
INV-IN
• Tel: (508) 339-3000
V OUT
= 2.048Vp-p
Direct
NON-IN
5k
22pf
Figure 2c. Non-inverting Mode
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 3 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Non-Inverting Mode
The non-inverting mode of the ADCDS-1603 allows the designer to either
attenuate or add non-inverting gain to the pixel data input signal. This
configuration also allows bypassing the ADCDS-1603's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c. describes the typical configuration for applications using pixel
data input signals with amplitudes greater than 0.342Vp-p and less than
2.048Vp-p. Using a single external series resistor, the coarse gain of the
ADCDS-1603 can be set. The coarse gain of the circuit can be determined
from the following equation:
VOUT = 2.048Vp-p = VIN*(1+(499/(100+Rext))),
with all internal resistors having a 0.1% tolerance.
Figure 2d. describes the typical configuration for applications using a
pixel data input signal whose amplitude is greater than 2.048Vp-p. Using
a single external series resistor (Rext 1) in conjunction with the internal
5K (1%) resistor to ground, an attenuation of the input signal can be
achieved. The coarse gain of this circuit can be determined from the
following equation:
VOUT = 2.048Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(499/(100+Rext2))],
with all internal resistors having a 0.1% tolerance.
Inverting Mode
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1603 has a pixel data input signal whose
amplitude is more positive than its associated reference level. The
ADCDS-1603's correlated double sampler (i.e. input amplifier's VOUT)
requires that the pixel data signal's amplitude be more negative than its
reference level at all times (see timing diagram for details). Using the
Rext2
100
ADCDS-1603 in the inverting mode allows the designer to perform an
additional signal inversion to correct for any analog "front end" preprocessing that may have occurred prior to the ADCDS-1603.
Figure 2e. describes the typical configuration for applications using a pixel
data input signal with a maximum amplitude of 0.342Vp-p. The coarse
gain of this circuit can be determined from the following equation:
VOUT = 2.048Vp-p = –VIN*(499/100),
with all internal resistors having a 0.1% tolerance.
Figure 2f. describes the typical configuration used in applications
needing to invert pixel data input signals whose amplitude is greater
than 0.342Vp-p. Using a single external series resistor, the initial gain
of the ADCDS-1603 can be set. The coarse gain of this circuit can be
determined from the following equation:
VOUT = 2.048Vp-p = –VIN*(499/100+Rext),
with all internal resistors having a 0.1% tolerance.
Offset Adjustment
Manual offset adjustment for the ADCDS-1603 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20KΩ potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1603 until the output bits are 0000 0000 0000 0000 and
the LSB flickers between 0 and 1. The ADCDS-1603's offset adjustment
is dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3) and the gain of the input-amplifier.
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1603 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
Rext
499
100
–VIN
INV-IN
0.01μf
0.01μF
NO CONNECT
499
INV-IN
V OUT = 2.048Vp-p
Direct
NO CONNECT
VOUT = 2.048Vp-p
Direct
Rext1
VIN
NON-IN
5k
NON-IN
22pf
Figure 2d. Non-inverting Mode
–VIN
100
22pf
Figure 2f. Inverting Mode
499
ADCDS-1603
INV-IN
+5V
0.01μf
NO CONNECT
5k
VOUT = 2.048Vp-p
Direct
NON-IN
5k
External
Series
Resistor
Offset
Adjust
2
20k
22pf
–5V
Figure 2e. Inverting Mode
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
Figure 3. Offset Adjustment Circuit
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 4 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Fine Gain Adjustment
Optimal Performance
For fine gain adjustment model, contact the factory.
Disturbances to the system while the A/D is undergoing a conversion can
result in degradation of performance. It is therefore recommended that
both digital and analog signals (including the Reference/Pixel data inputs
to the ADCDS) not be allowed to switch during a time window of 50ns
to 300ns following the rising edge of the Start Convert command when
operating in the 0°C to 70°C temperature range. For extended temperature range devices it may be required to have no signals switching until
after 300ns. See timing Figure 7 "A/D Critical Conversion Window."
Output Coding
The ADCDS-1603's output coding is Straight Binary as indicated in
Table 1. The table shows the relationship between the output data
coding and the difference between the reference signal voltage and
its corresponding pixel data signal voltage. Digital circuitry supply uses
+5VD for TDIP package version, and OVDD for Quad Pak version. OVDD is
a user selectable supply range.
While an ongoing conversion is in process the ADCDS-1603 is susceptible
to disturbances that could affect the quality of the conversion process.
This period of time would be the first 300ns following the rising edge of
the Start Convert command.
Table 1. Output Coding
Reference – Pixel Data
(V)
Scale
Digital Output
>+2.048
2.048
1.536
1.024
0.512
0.256
0.00003125
0
<0
>Full Scale
Full Scale -1LSB
3/4FS
1/2FS
1/4FS
1/8FS
1LSB
0
<0
1111 1111 1111 1111
1111 1111 1111 1110
1111 0000 0000 0000
1000 0000 0000 0000
0100 0000 0000 0000
0010 1000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
➀
➁
Note that the internal A/D of the ADCDS-1603 is performing the conversion process during the 300ns immediately following the rising edge of
the Start Convert signal. Disturbances to the device during this time can
result in a degradation of the quality of the conversion. Therefore, it may
be necessary to assure that no digital or analog signals be allowed to
switch during this time period. In this case, acquisition and settling limitations may require that the overall conversion rate of the ADCDS-1603
be reduced.
Note: At initial power-up, the first 186 conversions should be ignored.
Resultant signal from internal CDS (Input to A/D). Assumes Input Amplifier gain set properly.
See "Modes of Operation" section.
The pixel data portion of the differential signal must be more negative than its associated
reference level and VOUT should not exceed +2.048V DC.
+5VD
4.7μF
–5VA
4.7μF
+5VA
4.7μF
0.1μF
0.1μF
0.1μF
34
6
4.7μF
+5V
38
36
23 BIT 1 (MSB)
+2.048V REFERENCE OUT
22 BIT 2
0.1μF
External Series
Resistor
2
21 BIT 3
ADCDS-1603
TDIP Pkg
OFFSET ADJUST
20 BIT 4
19 BIT 5
18 BIT 6
20K7
3
–5V
See
Figures
2a–2f
4
17 BIT 7
DIRECT INPUT
16 BIT 8
INVERTING INPUT
15 BIT 9
14 BIT 10
5
13 BIT 11
NON-INVERTING INPUT
12 BIT 12
30
A0
11 BIT 13
10 BIT 14
31
0.1μF
A1
0.1μF
25
BIT 15
8
BIT 16 (LSB)
START CONVERT
27
REF. HOLD
32, 33 DIGITAL GROUND
26
7, 35, 37
9
DATA VALID
ANALOG GROUND
Figure 6A. ADCDS-1603 TDIP Pkg Connection Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 5 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
+5VD
4.7μF
–5VA
4.7μF
OVDD
4.7μF
0.1μF
0.1μF
0.1μF
31, 32, 65, 66
11
4.7μF
+5V
External Series
Resistor
2
See
Figures
2a–2f
6
8
60
61
0.1μF
+2.048V REFERENCE OUT
ADCDS-1603
4
0.1μF
18, 19
0.1μF
20.ȍ
–5V
13, 14,
54
56
1, 12, 15, 16, 20, 21
OFFSET ADJUST
Quad Pak
DIRECT INPUT
INVERTING INPUT
NON-INVERTING INPUT
A0
A1
START CONVERT
58
REF. HOLD
50
BIT 1 (MSB)
49
BIT 2
48
BIT 3
47
BIT 4
46
BIT 5
45
BIT 6
44
BIT 7
43
BIT 8
42
BIT 9
41
BIT 10
40
BIT 11
39
BIT 12
38
BIT 13
37
BIT 14
36
BIT 15
35
BIT 16 (LSB)
DATA VALID
DIGITAL GROUND
ANALOG GROUND
29, 30, 33, 34, 51, 52,
53, 63, 64, 67, 68
Figure 6B. ADCDS-1603 L Quad Pak Connection Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 6 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1603's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle ➂. If only a single analog
bandwidth was offered, the ADCDS-1603's bandwidth would be set
to acquire and digitize CCD output signals to 16-bit accuracy, at the
maximum conversion rate of 2.3MHz (434ns see Figure 8 for details).
Applications not requiring the maximum conversion rate would be
forced to use the full analog bandwidth at the possible expense of noise
performance.
Table 2. Timing Specification ➂
Parameters
2.3 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
1.8 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
1 MHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
800 kHz Conversion
Conversion Time
A0
A1
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
➂
Symbol➂
Min.
Typ.
Max.
Units
T1
–
–
–
–
–
300
434
LO
LO
180
120
–
3
–
–
–
134
–
ns
–
–
–
–
–
300
555
HI
LO
230
205
–
–
–
–
–
–
–
ns
–
–
–
–
–
300
1000
LO
HI
370
520
–
–
–
–
–
–
–
ns
–
–
–
–
–
300
1250
HI
HI
470
680
–
–
–
–
–
–
–
ns
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
The ADCDS-1603 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1603 allows the user to
"bandwidth limit" the input stage in order to realize the highest level of
noise performance for the application being considered. Table 2 describes
recommendations in selecting the appropriate reference hold (Reference
Aquisition Time) and CDS output (Pixel Data Settling Time) needed for a
particular application. Each of the selections listed in the Noise section
of Functional Specifications have been optimized to provide only enough
analog bandwidth to acquire a full scale input step (Vsat), to 16-bit
accuracy, in a single conversion. Increasing the analog bandwidth (using a
faster settling and acquisition time) would only serve to potentially increase
the amount of noise at the ADCDS-1603's output. The ADCDS-1603
uses a two bit digital word to select four different analog bandwidths
for the ADCDS-1603's input stage (See Table 2 for details). Functional
Specifications show typical RMS noise for given bandwidth and gain
settings.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See timing figures 7 and 8.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 7 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Timing
Once the reference signal has been "held" and the pixel data portion of
the CCD's analog output signal appears at the ADCDS-1603's input, the
internal correlated double sampler produces a "CDS Output" signal (see
Figure 8.) which is the difference between the "held" reference level
and its associated pixel data level (Reference-Pixel Data). When the "CDS
Output" signal has settled to the desired accuracy (t3), the A/D conversion
process can be initiated with the rising edge of the Start Convert signal.
The ADCDS-1603 requires two independently operated signals to
accurately digitize the analog output signal from the CCD array.
•
Reference Hold
•
Start Convert
The "Reference Hold" signal controls the operation of the internal
correlated double sampler (CDS) circuit. A logic "1" capture the value of
the CCD's reference signal. The Reference Hold Signal allows the user to
control the exact moment when the internal CDS is placed into the "hold"
mode. For optimal performance the internal CDS should be placed into the
"hold" mode once the reference signal has fully settled from all switching
transients to the desired accuracy (t2).
Once the A/D conversion has been initiated, the Reference Hold can be
placed back into the "Acquisition" mode in order to begin aquiring the
next reference level. For optimal performance the ADCDS-1603's should
be placed back into the "Aquisition" mode (Reference Hold to logic "0")
during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is
defined as the period when the CCD's reference signal has settled from
all switching transients to the desired accuracy (see Figure 7.) Placing the
sample-hold back into the "aquisition" mode during the "Reference Quiet
Time" prevents the ADCDS-1603's internal amplifiers from unnecessarily
tracking (reproducing) the reset feedthrough glitch that occurs during the
CCD's reset to reference transition.
Note that while an ongoing conversion is in process the ADCDS-1603 is
susceptible to disturbances that could affect the quality of the conversion
process. This period of time would be the first 300ns following the rising
edge of the Start Convert command.
Note that the internal A/D of the ADCDS-1603 is performing the
conversion process during the 300ns immediately following the rising
edge of the Start Convert signal. Disturbances to the device during
this time can result in a degradation of the quality of the conversion.
Therefore, it may be necessary to assure that no digital or analog signals
be allowed to switch during this time period. In this case, acquisition
and settling limitations may require that the overall conversion rate of the
ADCDS-1603 be reduced.
Disturbances to the system while the A/D is undergoing a conversion can
result in degradation of performance. It is therefore recommended that
both digital and analog signals (including the Reference/Pixel data inputs
to the ADCDS) not be allowed to switch during a time window of 50ns
to 300ns following the rising edge of the Start Convert command when
operating in the 0°C to 70°C temperature range. For extended temperature range devices it may be required to have no signals switching until
after 300ns. See timing Figure 7 "A/D Critical Conversion Window."
Note: At initial power-up, the first 186 conversions should be ignored.
A/D Critical Conversion Window
300 ns min.
START
CONVERT
Reset
Reference
"Quiet Time"
CCD
OUTPUT
Reference
Pixel Data
Reference
REFERENCE
HOLD
Hold
Acquisition
Time
Acquisition mode during
Reference “Quiet Time”
Figure 7. Reference Hold Timing
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 8 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
Reset
Feedthrough
Glitch
CCD
OUTPUT
Reference N
Ref. N+1
Pixel
Data N
REFERENCE
HOLD
(Pin 26)
Ref. N+3
Ref. N+4
Pixel Data
N+3
t2
Reference Hold
Reference
Acquisition
Time
t3
Pixel Data
Settling Time
Pixel Data
N+2
Ref. N+2
Pixel Data
N+1
Full Scale Step
(Vsat)
CDS
OUTPUT
N+2
N+1
N
t1
N+3
t4
START CONVERT
(Pin 25)
90ns typ.
DATA VALID
(Pin 27)
Data Invalid
DATA
Data Invalid
10ns min.
30ns max.
Data Invalid
Data Invalid
* 20ns min.
N-1 Data Valid
N Data Valid
N+1 Data Valid
N+2 Data Valid
* Output Data guaranteed to remain valid a minimum of 20ns after falling edge of DATA VALID.
++ CDS Output captured by S/H at rising edge of Start Convert.
Figure 8. ADCDS-1603 Timing Diagram
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Figure 9. ADCDS-1603 Differential Nonlinearity, LSBs
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 9 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
ADCDS-1603 Grounded Input Histogram – 2.3 MHz Rate
2.3 MHz Rate Gain = 6, A0=LO, A1=LO
2.29 LSB RMS, 12uV RMS
2.3 MHz Rate Gain = 1, A0=LO, A1=LO
1.64 LSB RMS, 51.1uV RMS
12000
18000
16000
10000
14000
8000
12000
10000
6000
8000
4000
6000
4000
2000
2000
0
0
19
21
23
25
Output Code
27
29
54
31
59
62
65
68
Output Code
71
74
ADCDS-1603 Grounded Input Histogram – 1.8 MHz Rate
1.8 MHz Rate Gain = 1, A0=HI, A1=LO
1.55 LSB RMS, 48.3uV RMS
1.8 MHz Rate Gain = 6, A0=HI, A1=LO
2.07 LSB RMS, 10.8uV RMS
18000
14000
16000
12000
14000
10000
12000
10000
8000
8000
6000
6000
4000
4000
2000
2000
0
0
24
26
28
30
Output Code
32
34
more
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
30
32
34
36
38
40
42
44
46
more
Output Code
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 10 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
ADCDS-1603 Grounded Input Histogram – 1.0 MHz Rate
1.0 MHz Rate Gain = 6, A0=LO, A1=HI
1.62 LSB RMS, 8.5uV RMS
1.0 MHz Rate Gain = 1, A0=LO, A1=HI
1.32 LSB RMS, 41.3uV RMS
20000
20000
18000
18000
16000
16000
14000
14000
12000
12000
10000
10000
8000
8000
6000
6000
4000
4000
2000
2000
0
0
33
35
37
39
Output Code
41
43
33
more
35
37
39
41
43
45
47
Output Code
ADCDS-1603 Grounded Input Histogram – 800 MHz Rate
800 kHz Rate
Gain = 1, A0=HI, A1=HI
1.31 LSB RMS,
800 kHz Rate
41.0uV RMS
Gain = 6, A0=HI, A1=HI
1.65 LSB RMS,
8.6uV RMS
18000
22000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
16000
14000
12000
10000
8000
6000
4000
2000
0
39
41
43
45
47
49
41
43
45
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
47
49
51
53
Output Code
Output Code
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 11 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
MECHANICAL DIMENSIONS inches (mm)
CENTER PICKUP POINT
FOR 8mm PICKUP
NOZZLE
TOP VIEW
.99
END VIEW
.025±.002
(44 PLS)
16-BIT, 2.3MHz
CCD IMAGE PROCESSOR
.99
1.27 TYP.
(32.25)
ADCDS-1603
PIN #1 LOCATED
AT 'BEVELED'
CORNER
2.24 TYP. (56.90)
ALL SMT PINS
COPLANAR
WITHIN .004"
SIDE VIEW
ADCDS-1603LC-C
16-BIT, 2.3MHZ
IMAGING SIGNAL
PROCESSOR
0.254 TYP.
(6.45)
0.32 TYP
(8.128)
PIN #1
.870
.65
PIN #44
1.900 ±0.008
(48.260)
0.254 TYP.
(6.45)
.435
TDIP
Package
.870
0.900 ±0.010
(22.86)
10 EQUAL
SPACES
@ .050 EA
=.500
TOL NON ACCUM
(4 PLACES)
CL
.250
.65
CL
.050 REF
TDIP Package
.250
REF
.500 REF
.435
BOTTOM VIEW
ISOMETRIC VIEW
Quad Pak
ORDERING INFORMATION
MODEL NUMBER
ADCDS-1603
ADCDS-1603EX
ADCDS-1603-C
OPERATING
TEMP. RANGE
PACKAGE
ROHS
0 to +70°C
TDIP
No
–40 to +100°C
TDIP
No
0 to +70°C
TDIP
Yes
–40 to +100°C
TDIP
Yes
ADCDS-1603LC-C
0 to +70°C
Quad Pak
Yes
ADCDS-1603LEX-C
–40 to +100°C
Quad Pak
Yes
ADCDS-1603EX-C
ACCESSORIES
ADCDS-B1801L-C / ADCDS-B1603L-C EVAL BD.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
Evaluation Board (without ADCDS-1603)
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 12 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
+ 5VA
ANALOG GND
DIGITAL GND
+OVDD
+OVDD
DIGITAL GND
A1
A0
DATA VALID
43
41
40
39
38
37
36
35
34
44
42
INPUT/OUTPUT CONNECTIONS—ADCDS-1603LEX-C 44-Pin Quad Pak
ANALOG GND
FUNCTION
NO CONNECTION
NO CONNECTION
–5VA
ANALOG GROUND
+5VA
ANALOG GROUND
+5VD
DIGITAL GROUND
DIGITAL GROUND
A1
AØ
NO CONNECTION
NO CONNECTION
DATA VALID
REFERENCE HOLD
START CONVERT
NO CONNECTION
BIT 1 (MSB)
BIT 2
BIT 2
ANALOG GND
1
33
REFERENCE HOLD
OFFSET ADJUST
2
32
START CONVERT
DIRECT INPUT
3
31
DIGITAL GND
INVERTING INPUT
4
30
BIT 1 (MSB)
NON-INVERTING INPUT
5
29
BIT 2
ANALOG GND
6
28
BIT 3
+2.048V REF OUTPUT
7
27
BIT 4
ANALOG GND
8
26
BIT 5
-5VA
9
25
BIT 6
ANALOG GND
10
24
BIT 7
-5VA
11
23
BIT 8
13
14
15
16
17
18
19
20
21
22
NC
BIT 16 (LSB)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
44-Pin Package
12
PIN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
FUNCTION
NO CONNECTION
OFFSET ADJUST
DIRECT INPUT
INVERTING INPUT
NON-INVERTING INPUT
+2.048V REF. OUTPUT
ANALOG GROUND
BIT 16 (LSB)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
DIGITAL GND
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+ 5VA
INPUT/OUTPUT CONNECTIONS— ADCDS-1603 TDIP Package
RECOMMENDED FOOTPRINT—ADCDS-1603LEX-C 44-Pin Quad Pak
0.870"
TYP.
0.500"
TYP.
0.250"
TYP.
0.435"
TYP.
PAD OFFSET 0.020" TYP.
PAD 0.120" TYP.
PASTE 0.116" TYP.
0.002" TYP.
PASTE
0.030" PAD 0.04" TYP.
TYP.
0.005"
TYP.
RECOMMENDED PAD AND PASTE DIMENSIONS
0.050" TYP.
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 13 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
EVALUATION BOARD
ASSEMBLY
TOP VIEW
BOTTOM VIEW
BOM
Rev.
1
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Title
QPA
Ref Des
ADCDS-B1801L-C/ADCDS-B1603L-C EVAL BD ASSY DWG
ADCDS-B1801L-C/ADCDS-B1603L-C EVAL BD SCH DWG
PCB ADCDS-B1801L-C/ADCDS-B1603L-C EVALUATION BOARD
IC LIN TO220 NEG VOLT REG 15V 7905C
IC ANA SMT VREG ADJ SINGLE 317 19.1V 4% DPAK INDUSTRIAL 125C
CAP SMT NON POL CERAMIC X7R 0.1UF 50V 10% 0603 STANDARD
CAP SMT NON POL CERAMIC X7R 2.2UF 25V 10% 0805 STANDARD
RES SMT FXD THICK FILM STANDARD 402R 1% 0603 100MW
RES SMT FXD THICK FILM STANDARD 5.11K 1% 0603 100MW
RES SMT FXD THIN FILM STANDARD 249R 0.5% 0603 100MW
CON OTHER JUMPER 0.1IN 3A
CON PTH CONTACT PIN PRESSFIT 3A 0.04IN
CON PTH COAX BNC PCB RECEPT 0DEG
ENGLISH STANDOFF HEX ALUMINIUM 4-40 0.5IN
SCREW MACHINE CARB STEEL PAN HD PHILLIPS #4-40 X .250 LONG
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
1
1
1
9
11
1
1
1
6
18
3
4
4
• Tel: (508) 339-3000
U3
U4
C1, C2, C3, C4, C5, C6, C21, C22, C23
C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20
R3
R1
R2
J3, J4, J5, J6, J7, J8
USE W/J3, J4, J5, J6, J7, J8
•
www.datel.com
•
e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 14 of 15
ADCDS-1603
16-Bit, 2.3 Megapixels/Second CCD Image Converter
EVALUATION BOARD
SCHEMATIC
DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice.
ITAR and ISO 9001/14001 REGISTERED
© 2015 DATEL, Inc.
www.datel.com • e-mail: help@datel.com
08 Jun 2015
MDA_ADCDS-1603.E12 Page 15 of 15