ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor Typical unit PRODUCT OVERVIEW The ADCDS-1410 is an application-specific video signal processor designed for electronic-imaging applications that employ CCD's (charge coupled devices) as their photodetector. The ADCDS-1410 incorporates a "user configurable" input amplifier, a CDS (correlated double sampler) and a sampling A/D converter in a single package, providing the user with a complete, high performance, low-cost, low-power, integrated solution. The key to the ADCDS-1410's performance is a unique, high-speed, high-accuracy CDS circuit, which eliminates the effects of residual charge, charge injection and "kT/C" noise on the CCD's output floating capacitor, producing a "valid video" output signal. The ADCDS-1410 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling A/D converter. The ADCDS-1410 requires only the rising edge of start convert pulse to initiate its conversion process. Additional features of the ADCDS-1410 include gain adjust, offset adjust, precision +2.4V reference, and a programmable analog bandwidth function. FEATURES n n n n n n n n n n 14-bit resolution 10MPPS throughput rate (14-bits) Extended temperature range -55°C to +100°C 1 LSB RMS Noise Excellent Signal-to-Noise ratio Edge triggered Small, 40-pin, TDIP package Low power, 800mW typical Low cost, functionally complete Programmable Analog Bandwidth Pin INPUT/OUTPUT CONNECTIONS Function Pin Function 1 Fine Gain Adjust 40 No Connect 2 Offset Adjust 39 +12v 3 Direct Input 38 –5va 4 Inverting Input 37 Analog Ground 5 Non-Inverting Input 36 +5va 6 +2.4v Ref. Output 35 Analog Ground 7 Analog Ground 34 +5vd 8 No Connect 33 Digital Ground 9 No Connect 32 Digital Ground 10 Bit 14 (Lsb) 31 A1 11 Bit 13 30 AO 12 Bit 12 29 No Connect 13 Bit 11 28 No Connect 14 Bit 10 27 Data Valid 15 Bit 9 26 Reference Hold 16 Bit 8 25 Start Convert 17 Bit 7 24 Out-Of-Range 18 Bit 6 23 Bit 1 (Msb) 19 Bit 5 22 Bit 2 20 Bit 4 21 Bit 3 SIMPLIFIED SCHEMATIC +12VA 75� INVERTING INPUT +5VA –5VA 39 38 +5VD 36 34 523� 4 25 START CONVERT 1 FINE GAIN ADJUST INPUT AMPLIFIER 0.01µF DIRECT INPUT 3 NON-INVERTING INPUT 5 5K � CORRELATED DOUBLE SAMPLER 23 BIT 1 (MSB) SAMPLING A/D 10 BIT 14 (LSB) OFFSET ADJUST 2 REFERENCE HOLD 26 TIMING AND CONTROL 24 OUT-OF-RANGE 6 32, 33 DIGITAL GROUND 27 DATA VALID +2.4V REFERENCE OUTPUT 7, 35, 37 30 31 AØ A1 ANALOG GROUND Figure 1. ADCDS-1410 Functional Block Diagram For full details go to www.murata-ps.com/rohs www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 1 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor STATIC PERFORMANCE, continued Absolute Maximum Ratings MIN. TYP. MAX. UNITS LSB MIN. TYP. MAX. UNITS DC Noise +12V Supply (Pin 32) 0 — +14 Volts +25°C — 0.75 1 –5V Supply (Pin 38) –6.5 — +0.3 Volts 0 to 70°C — 0.75 1 LSB +5V Supply (Pin 34, 36) –0.3 — +6.5 Volts –55 to +100°C — 0.75 1 LSB Digital Input (Pin 25, 26, 30, 31) –0.3 — Vdd+0.3V Volts PARAMETERS Analog Input (Pin 3,4,5) –5 — +5 Volts Lead Temperature (10 seconds) — — 300 °C Functional Specifications The following specifications apply over the operating temperature range, under the following conditions: Vcc=+12V, +Vdd=+5V, Vee=–5V, fin=98KHz, sample rate=10MSPS ANALOG INPUT Input Voltage Range (externally configurable) MIN. TYP. MAX. UNITS 0.350 2.8 — Volts p-p Input Resistance — 5000 — Ohm Input Capacitance — 10 — pF DIGITAL INPUTS Logic 1 +3.5 — — Volts Logic 0 — — +.80 Volts Logic Loading Logic 1 — — +10 uA Logic 0 — — –10 uA DIGITAL OUTPUTS Logic Levels Logic 1 (IOH = .5ma) +2.4 — Logic 1 (IOH = 50µa) +4.5 Logic 0 (IOL = 1.6ma) — Logic 0 (IOL = 50ua) — — Volts — — Volts — +0.4 Volts — +0.1 Volts Internal Reference Voltage (Fine gain adjust pin (1) grounded) +25°C 2.35 2.4 2.45 Volts 0 to 70°C 2.35 2.4 2.45 Volts –55 to +100°C 2.35 2.4 2.45 Volts — 1.0 — mA STATIC PERFORMANCE — ±0.6 ±3.0 %FSR — ±0.6 ±3.0 %FSR –55 to +100°C — ±0.6 ±6.0 %FSR +25°C — ±1.00 ±3.0 %FSR 0 to 70°C — ±1.35 ±3.0 %FSR –55 to +100°C — ±1.35 ±6.0 %FSR — 40 — ns @ 25°C — 25 — mV/us @ –55 to +100°C — 100 — mV/us @ +25 °C 73 75 — dB @ 0 to +70°C 73 75 — dB @ –55 to +100°C 70 73 — dB @ +25 °C 73 75 — dB @ 0 to +70°C 73 75 — dB @ –55 to +100°C 70 73 — dB Gain Error DYNAMIC PERFORMANCE Reference Hold Aquisition Time Signal-to-Noise Ratio Without Distortion (CDD-IN, input on pin (3) Input @ 98kHz) (Input on pin (5) Input @ 98kHz) SIGNAL TIMING Conversion Rate –55 to +100°C 10 — — MSPS Conversion Time — 100 — nsec Start Convert Pulse Width — 150 — nsec +12V Supply +11.4 +12.0 +12.6 Volts +5V Supply +4.75 +5.0 +5.25 Volts –5V Supply –4.75 –5.0 –5.25 Volts POWER REQUIREMENTS Differential Nonlinearity (Histogram, 98kHz) +25°C –.99 ±0.5 +1.5 LSB 0 to 70°C –.99 ±0.5 +1.5 LSB –55 to +100°C +25°C 0 to 70°C Droop Logic Levels External Current Offset Error –.99 ±0.6 +1.5 LSB Integral Nonlinearity +25°C — ±2.5 — LSB 0 to 70°C — ±2.5 — LSB –55 to +100°C — ±2.5 — LSB 0 to 70°C 14 — — LSB –55 to +100°C 14 — — LSB Power Supply Range Guaranteed No Missing Codes www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 2 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor POWER REQUIREMENTS MIN. TYP. MAX. UNITS — +20 +26 mA Power Supply Current +12V Supply Direct Mode (AC Coupled) Power Supply Current +5V Supply — +65 +70 mA -5V Supply — -50 -55 mA — 0.8 0.99 Watts Power Dissipation Power Supply Rejection (5%) @ +25°C — ±0.04 ±0.06 %FSR/%V ENVIRONMENTAL Operating Temperature Range ADCDS-1410 ADCDS-1410EX Storage Temperature external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2) features. 0 — +70 °C –55 — +100 °C –65 — +150 °C Package Type 40-pin, TDIP Weight 16.10 grams TECHNICAL NOTES 1. Obtaining fully specified performance from the ADCDS-1410 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital grounds are connected to each other internally. Depending on the level of digital switching noise in the overall CCD system, the performance of the ADCDS-1410 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. The use of a single +5V analog supply for both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial. This is the most common input configuration as it allows the ADCDS-1410 to interface directly to the output of the CCD with a minimum amount of analog "front-end" circuitry. This mode of operation is used with full-scale video input signals from 0.350Vp-p to 2.8Vp-p. Figure 2a. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. The coarse gain of the input amplifier is determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1% tolerance. Additional fine gain adjustment can be accomplished using the Fine Gain Adjust (pin 1 see Figure 5). Figure 2b. describes the typical configuration for applications using a video input signal with an amplitude greater than 0.350Vp-p and less than 2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1410 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the input amplifier can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance. VIN NO CONNECT 4 75� 3 0.01µF VOUT = 2.8Vp-p 5 5k� 2. Bypass all power supplies to ground with a 4.7µf tantalum capacitor in parallel with a 0.1µf ceramic capacitor. Locate the capacitors as close to the package as possible. 3. If using the suggested offset and gain adjust circuits (Figure 3 & 5), place them as close to the ADCDS-1410's package as possible. Figure 2a. Rext 4. A0 and A1 (pins 30, 31) should be bypassed with 0.1µf capacitors to ground to reduce susceptibility to noise. VIN NO CONNECT ADCDS-1410 Modes of Operation 75� 3 0.01µF VOUT = 2.8Vp-p 5 5k� Figure 2b. Rext When applying inputs which are less than 2.8Vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8Vp-p signal at the input-amplifier's output (Vout). In all three modes of operation, the video portion of the signal at the CDS input (i.e. input-amplifier's Vout) must be more negative than its associated reference level and Vout should not exceed ±2.8V DC. 523� 4 The input amplifier stage of the ADCDS-1410 provides the designer with a tremendous amount of flexibility. The architecture of the ADCDS-1410 allows its input-amplifier to be configured in any of the following configurations: • Direct Mode (AC coupled) • Non-Inverting Mode • Inverting Mode 523� NO CONNECT VIN 4 75� 3 0.01µF 523� VOUT = 2.8Vp-p 5 5k� Figure 2c. The ADCDS-1410 achieves it specified accuracies without the need for www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 3 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor Non-Inverting Mode Inverting Mode The non-inverting mode of the ADCDS-1410 allows the designer to either attenuate or add non-inverting gain to the video input signal. This configuration also allows bypassing the ADCDS-1410's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. The inverting mode of operation can be used in applications where the analog input to the ADCDS-1410 has a video input signal whose amplitude is more positive than its associated reference level. The ADCDS-1410s correlated double sampler (i.e. input amplifier's VOUT) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). Using the ADCDS-1410 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have occurred prior to the ADCDS-1410. Figure 2c. describes the typical configuration for applications using video input signals with amplitudes greater than 0.350Vp-p and less than 2.8Vp-p (with common mode limit of ±2.5V DC). Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1410 can be set with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the circuit can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance. Figure 2e. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. Additional fine gain adjustments can be made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = –VIN*(523/75), with all internal resistors having a 1% tolerance. Figure 2d. describes the typical configuration for applications using a video input signal whose amplitude is greater than 2.8Vp-p. Using a single external series resistor (Rext 1) in conjunction with the internal 5K (1%) resistor to ground, an attenuation of the input signal can be achieved. Additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]* [1+(523/(75+Rext2))], with all internal resistors having a 1% tolerance. Rext2 NO CONNECT Rext1 VIN 4 75� 3 0.01µF Figure 2f. describes the typical configuration used in applications needing to invert video input signals whose amplitude is greater than 0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial gain of the ADCDS-1410 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors having a 1% tolerance. 523� ADCDS-1405 10 VOUT = 2.8Vp-p +5V 5 5k� 20KΩ NO CONNECT 523� 4 75� 3 0.01µf Figure 3. Offset Adjustment Circuit VOUT = 2.8Vp-p 5 Coarse Gain Adjustment Plot External Gain Resistor vs. Full Scale Video Input Figure 2e. Rext NO CONNECT 4 75� 3 0.01µf 523� VOUT = 2.8Vp-p 5 External Gain Resistor (Ohms) 5k� –VIN Offset Adjust 2 –5V Figure 2d. –VIN External Series Resistor 5k� 10000 Direct Mode & Non-Inverting Mode 1000 Inverting Mode 100 10 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 Full Scale Video Signal (Volts) Figure 4. Coarse Gain Adjustment Plot Figure 2f. www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 4 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor Offset Adjustment For Example: Manual offset adjustment for the ADCDS-1410 can be accomplished using the adjustment circuit shown in Figure 3. A software controlled D/A converter can be substituted for the 20KΩ potentiometer. The offset adjustment feature allows the user to adjust the Offset/Dark Current level of the ADCDS-1410 until the output bits are 00 0000 0000 0000 and the LSB flickers between 0 and 1. Offset adjust should be performed before gain adjust to avoid interaction. The ADCDS1410's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing ±5V supplies. External 50KΩ resistor: 1. 10mV of noise or voltage variation at the potentiometer will produce 0.25LSB's of output variation. 2.100mV of noise or voltage variation at the potentiometer will produce 2.5LSB's of output variation. The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. If a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. The ADCDS-1410's +2.4V reference output could be configured to provide the reference voltage for this type of application. Offset Adjustment Sensitivity It should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the ADCDS-1410 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer. 10 ADCDS-1405 20KΩ Fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (Rext) and/or the unavailability of exact coarse gain resistor (Rext) values. Note, the fine gain adjustment will not change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead, the gain of the ADCDS-1410's internal A/D is adjusted allowing the actual input amplifier's full scale VOUT to produce an output code of all ones (11 1111 1111 1111). Fine gain adjustment for the ADCDS-1410 is accomplished using the adjustment circuit shown below (Figure 5). A software controlled D/A converter can be substituted for the 20KΩ potentiometer. The fine gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired Full Scale digital output of 11 1111 1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust should be performed following the offset adjust to avoid interaction. The fine gain adjust provides ±256 codes of adjust when ±5V supplies are used for the Fine Gain Adjust Circuit. Fine Gain Adjust 1 +5V Fine Gain Adjustment –5V Figure 5. Fine Gain Adjustment Circuit Offset Adjustment Sensitivity External Series Resistor vs. Output Variation (LSB's) Offset Adjustment vs. External Series Resistor 100 Output Variation (LSB's) ±LSB's of Adjustment 10000 1000 100 10 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k External Series Resistor (Ohm's) Figure 6. Offset Adjustment vs. External Series Resistor www.murata-ps.com Peak-Peak variation at potentiometer 10 100mV 1 10mV 0.1 0.01 1mV 0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K External Series Resistor Value (Ohms) Figure 7. Offset Adjustment Sensitivity Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 5 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor Out-of-Range Indicator Output Coding The ADCDS-1410 provides a digital Out-of-Range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal A/D converter. The digital output bits and the Out-of-Range signal correspond to a particular sampled video input range, with both of these signals having a common pipeline delay. The ADCDS-1410's output coding is Straight Binary as indicated in Table 2. The table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding video signal voltage. (These voltages are referred to the output of the ADCDS-1410's input amplifier's VOUT). Using the circuit described in Figure 8, both over-range and under-range conditions can be detected (see Table 1). When combined with a D/A converter, digital detection and correction can be performed for both the gain and offset errors. MSB "OVERRANGE" OUT-OF-RANGE "UNDERRANGE" Figure 8. Overrange/ Underrange Circuit Table 1. Out-of-Range Conditions Outover of rangemsb Range 0 0 1 1 0 1 0 1 underinput Rangesignal 0 0 0 1 0 0 1 0 In Range In Range Underrrange Overrange Programmable Analog Bandwidth Function When interfacing to CCD arrays with very high-speed "readout" rates, the ADCDS-1410's input stage must have sufficient analog bandwidth to accurately reproduce the output signals of the CCD array. The amount of analog bandwidth determines how quickly and accurately the "Reference Hold" and the "CDS output" signals will settle. If only a single analog bandwidth was offered, the ADCDS-1410's bandwidth would be set to acquire and digitize CCD output signals to 14-bit accuracy, at maximum conversion rate of 10MHz (100ns see Figure 11. for details). Applications not requiring the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance. The ADCDS-1410 avoids this situation by offering a fully programmable analog bandwidth function. The ADCDS-1410 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise performance for the application being considered. Table 3. describes how to select the appropriate reference hold "aquisition time" and CDS output "settling time" needed for a particular application. Each of the selections listed in Table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. Increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the ADCDS-1410's output. The ADCDS-1410 uses a two bit digital word to select four different analog bandwidths for the ADCDS1410's input stage (See Table 3. for details). Table 2. Output Coding Input amplifier VOUT, ➀ (volts p-p) Video Signal-Reference Signal Video Signal-Reference Signal scale > –2.80000 >Full Scale –1LSB –2.80000 Full Scale –1LSB –2.10000 3/4FS –1.40000 1/2FS –0.70000 1/4FS –0.35000 1/8FS –0.000171 1 LSB 0 0 <0 ➁ <0 digital output 11 1111 1111 1111 11 1111 1111 1111 11 0000 0000 0000 10 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 out-of-range 1 0 0 0 0 0 0 0 1 Notes: ➀ Input Amplifier VOUT = (Video Signal - Reference Level) ➁ The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference level and VOUT should not exceed ±2.8V DC. www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 6 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor Table 3. Programmable Analog Bandwidth REFERENCE HOLD "AQUISITION TIME" CDS OUTPUT "SETTLING TIME" A0 (Pin 30) A1 (Pin 31) ADCDS-1410 MAX. CONVERSION RATE -3dB BW 40ns 40ns 0 0 10MHz 14MHz 80ns 80ns 1 0 5MHz 10MHz 150ns 150ns 0 1 3MHz 5MHz 300ns 300ns 1 1 1.2MHz 3MHz Note: See Figure 11. for timing details +12V 4.7µF + +5VD 4.7µF + –5VA 4.7µF + +5VA 4.7µF + 0.1µF 0.1µF 0.1µF 0.1µF 39 +5V 1 20KΩ –5V External Series Resistor +5V 20KΩ 2 4 5 30 0.1µF 0.1µF 38 36 23 BIT 1 (MSB) FINE GAIN ADJUST 22 BIT 2 21 BIT 3 3 –5V 36 31 25 26 7, 35, 37 20 BIT 4 OFFSET ADJUST 19 BIT 5 DIRECT INPUT 17 BIT 7 INVERTING INPUT 15 BIT 9 18 BIT 6 16 BIT 8 14 BIT 10 13 BIT 11 NON-INVERTING INPUT A 12 BIT 12 ADCDS-1410 11 BIT 13 10 BIT 14 (LSB) A1 START CONVERT 6 +2.4V REFERENCE OUT 24 OUT-OF-RANGE REF. HOLD 27 DATA VALID ANALOG GROUND 32, 33 DIGITAL GROUND Figure 9. ADCDS-1410 Connection Diagram Timing The ADCDS-1410 requires two independently operated signals to accurately digitize the analog output signal from the CCD array. • Reference Hold (pin 26) • Start Convert (pin 25) The "Reference Hold" signal controls the operation of an internal sample-hold circuit. A logic "1" places the sample-hold into the hold mode, capturing the value of the CCD's reference www.murata-ps.com signal. The Reference Hold Signal allows the user to control the exact moment when the sample-hold is placed into the "hold" mode. For optimal performance the sample-hold should be placed into the "hold" mode once the reference signal has fully settled from all switching transients to the desired accuracy (user defined). Once the reference signal has been "held" and the video portion of the CCD's analog output signal appears at the ADCDS-1410's input, the ADCDS-1410's correlated double sampler produces a "CDS Output" signal (see Figure 11.) Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 7 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor should be placed back into the "Aquisition" mode (Reference Hold to logic "0") during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is defined as the period when the CCD's reference signal has settled from all switching transients to the desired accuracy (see Figure 10.)). Placing the samplehold back into the "aquisition" mode during the "Reference Quiet Time" prevents the ADCDS-1410's internal amplifiers from unecessarily tracking (reproducing) the large switching transients that occur during the CCD's reset to reference transition. which is the difference between the "held" reference level and its associated video level. When the "CDS Output" signal has settled to the desired accuracy (user defined), the A/D conversion process can be initiated with the rising edge of a single start convert (Pin 25) signal. Once the A/D conversion has been initiated, Reference Hold (Pin 26) can be placed back into the "Acquisition" mode in order to begin aquiring the next reference level. For optimal performance the ADCDS-1410's internal sample-hold Reset Reference "Quiet Time" CCD OUTPUT Reference Video 50ns HOLD REFERENCE HOLD Acquisition Time Acquisition mode during Reference "Quiet Time" Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1410 should be placed into the Acquisition mode (Reference Hold to logic "0") during the CCD output's Reference "Quiet Time". Reference "Quiet Time" is defined as the period when the reference signal's switching transients have settled to an acceptable (user defined) accuracy. Figure 10. Reference Hold Timing Reset N CCD OUTPUT Reset N+1 Ref. Ref NN Reset N+2 Ref. N+1 Reset N+3 Ref. N+2 Video N+1 Reset N+4 Ref. N+3 Video VideoN+2 N+1 Ref. N+4 Video VideoN+3 N+1 Video N Acquisition Time 100ns 133ns min. min 50ns min. Hold REFERENCE HOLD IN 40ns min. settling time Full Scale Step DATA VALID N N+2 N+1 N+3 30ns min., 50ns max. Invalid data DATA OUTPUT N+3 50ns typ. 20ns START CONVERT N+2 N+1 N CDS OUTPUT DATA N-4 VALID min 20ns max DATA N-3 VALID DATA N-2 VALID DATA N-1 VALID DATA N VALID Figure 11. ADCDS-1410 Timing Diagram www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 8 of 9 ADCDS-1410 14-Bit, 10 Megapixels/Second, CCD Signal Processor MECHANICAL DIMENSIONS INCHES (mm) ® ® ADCDS-1410 1.27 TYP. (32.25) 14-BIT, 10MHz IMAGING SIGNAL PROCESSOR Made in USA 2.24 TYP. (56.90) 0.23 TYP. (5.84) 0.100 TYP. (2.540) 0.900 ±0.010 (22.86) 1.900 ±0.008 (48.260) ORDERING INFORMATION OPERATING MODEL TEMPERATURE RANGE ADCDS-1410 ADCDS-1410EX 0 to 70°C –55 to 100°C USA: 40-PIN PACKAGE TDIP TDIP Mansfield (Ma), Tel: (508) 339-3000, email: [email protected] Canada: Toronto, Tel: (866) 740 1232, email: [email protected] UK: Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Milton Keynes, Tel: +44 (0)1908 615232, email: [email protected] France: Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: [email protected] Germany: München, Tel: +49 (0)89-544334-0, email: [email protected] www.murata-ps.com email: [email protected] ISO 9001 REGISTERED Japan: Tokyo, Tel: 3-3779-1031, email: [email protected] Osaka, Tel: 6-6354-2025, email: [email protected] Website: www.murata-ps.jp China: Shanghai, Tel: +86 215 027 3678, email: [email protected] Guangzhou, Tel: +86 208 221 8066, email: [email protected] 02/02/09 Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. © 2008 Murata Power Solutions, Inc. www.murata-ps.com Technical enquiries email: [email protected], tel: +1 508 339 3000 MDA_ADCDS-1410.B02 Page 9 of 9