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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µPD3778 10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners and so on. FEATURES • Valid photocell : 10600 pixels × 3 • Photocell's pitch : 4 µm • Photocell size : 4 × 4 µm 2 • Line spacing : 48 µm (12 lines) Red line-Green line, Green line-Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 1200 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 5 MHz MAX. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number µPD3778CY Package CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14374EJ2V0DS00 (2nd edition) Date published October 2002 N CP(K) Printed in Japan The mark shows major revised points. © 1999 µPD3778 BLOCK DIAGRAM VOD GND GND φ2 φ1 29 1 16 22 19 CCD analog shift register 18 φ TG1 (Blue) 17 φ TG2 (Green) 15 φ TG3 (Red) D67 D66 D65 S10600 Photocell (Blue) S10599 S2 ........ S1 30 D64 VOUT1 (Blue) D14 Transfer gate Transfer gate CCD analog shift register CCD analog shift register D67 D66 D65 S10600 Photocell (Green) S10599 S2 ........ S1 31 D64 VOUT2 (Green) D14 Transfer gate Transfer gate CCD analog shift register CCD analog shift register D67 D66 D65 S10600 Photocell (Red) S10599 S2 ........ S1 32 D64 VOUT3 (Red) D14 Transfer gate Transfer gate CCD analog shift register 2 3 2 14 11 φ CLB φ RB φ2 φ1 Data Sheet S14374EJ2V0DS µPD3778 PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) • µPD3778CY 32 VOUT3 Output signal 3 (Red) Reset gate clock φ RB 2 31 VOUT2 Output signal 2 (Green) Reset feed-through level clamp clock φ CLB 3 30 VOUT1 Output signal 1 (Blue) No connection NC 4 29 VOD Output drain voltage No connection NC 5 28 NC No connection Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection No connection NC 9 24 NC No connection No connection NC 10 23 NC No connection Shift register clock 1 φ1 11 22 φ2 Shift register clock 2 Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection Shift register clock 2 φ2 14 19 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 15 18 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 16 17 φ TG2 Transfer gate clock 2 (for Green) Blue 10600 Green 10600 Red 10600 1 1 1 GND 1 Ground Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Data Sheet S14374EJ2V0DS 3 µPD3778 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 4 µm 4 µm 2 µm 2 µm 12 lines (48 µm) 4 µm Green photocell array Channel stopper 12 lines (48 µm) 4 µm Aluminum shield 4 Blue photocell array Data Sheet S14374EJ2V0DS Red photocell array µPD3778 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage V φ1 , V φ2 –0.3 to +8 V Reset gate clock voltage VφRB –0.3 to +8 V Reset feed-through level clamp clock voltage VφCLB –0.3 to +8 V Transfer gate clock voltage VφTG1 to VφTG3 –0.3 to +8 V Operating ambient temperatureNote TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ1H, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Reset feed-through level clamp clock high level VφCLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level VφCLBL –0.3 0 +0.5 V Transfer gate clock high level VφTG1H to VφTG3H 4.5 Vφ1HNote Vφ1HNote V Transfer gate clock low level VφTG1L to VφTG3L –0.3 0 +0.5 V Data rate fφRB – 1.0 5.0 MHz Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H), Image lag can increase. Data Sheet S14374EJ2V0DS 5 µPD3778 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, data rate (fφRB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol MIN. TYP. MAX. Unit Vsat 2.0 2.5 – V Red SER – 0.694 – lx•s Green SEG – 0.757 – lx•s Blue SEB – 1.250 – lx•s Saturation voltage Saturation exposure Test Conditions Photo response non-uniformity PRNU VOUT = 1.0 V – 6 20 % Average dark signal ADS Light shielding – 0.2 4.0 mV Dark signal non-uniformity DSNU Light shielding – 1.5 4.0 mV Power consumption PW – 400 600 mW Output impedance ZO – 0.5 1 kΩ Red RR 2.52 3.60 4.68 V/lx•s Green RG 2.31 3.30 4.29 V/lx•s Blue RB 1.40 2.00 2.60 V/lx•s – 2.0 10.0 % 4.0 6.0 7.0 V Response Image lag Offset level IL Note1 Output fall delay time VOUT = 1.0 V VOS Note2 td VOUT = 1.0 V – 50 – ns TTE VOUT = 1.0 V, 92 98 – % 0 1.0 4.0 % Red – 630 – nm Green – 540 – nm Blue – 460 – nm Total transfer efficiency data rate = 5 MHz Register imbalance Response peak RI Dynamic range Reset feed-through noise Random noise (CDS) Note1 VOUT = 1.0 V DR1 Vsat /DSNU – 1666 – times DR2 Vsat /σ CDS – 2500 – times RFTN Light shielding –1000 –300 +500 mV σ CDS Light shielding – 1.0 – mV Notes 1. Refer to TIMING CHART 2. 2. When each fall time of φ1 and φ2 (t2, t1) is the TYP. value (refer to TIMING CHART 2). 6 Data Sheet S14374EJ2V0DS µPD3778 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Pin No. MIN. TYP. MAX. Unit 11 – 400 – pF 19 – 400 – pF 14 – 400 – pF 22 – 400 – pF φRB 2 – 15 – pF Reset feed-through level clamp clock pin capacitance CφCLB φCLB 3 – 15 – pF Transfer gate clock pin capacitance φTG1 18 – 120 – pF φTG2 17 – 120 – pF φTG3 15 – 120 – pF Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Reset gate clock pin capacitance Symbol C φ1 C φ2 CφRB CφTG Pin name φ1 φ2 Remark Pins 11 and 19 (φ1), 14 and 22 (φ2) are each connected inside of the device. Data Sheet S14374EJ2V0DS 7 8 TIMING CHART 1 (for each color) 8 7 6 5 4 3 2 φ1 1 φ TG1 to φ TG3 φ2 φ RB 10663 10664 10665 10666 10667 10668 10669 φ CLB 61 62 63 64 65 66 Data Sheet S14374EJ2V0DS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note Note VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (10600 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) Note Input the φRB and φCLB pulses continuously during this period, too. µPD3778 µPD3778 TIMING CHART 2 (for each color) t2 t1 90 % φ1 10 % 90 % φ2 10 % t5 φ RB t3 t6 t4 90 % 10 % t10 φ CLB t8 t7 t9 t11 90 % 10 % + td td RFTN VOUT _ VOS RFTN 10 % 10 % Data Sheet S14374EJ2V0DS 9 µPD3778 φTG1 to φTG3, φ1, φ2 TIMING CHART t13 t14 t12 90 % φ TG1 to φ TG3 10 % t16 t15 90 % φ1 φ2 Symbol MIN. TYP. MAX. Unit t1, t2 0 25 – ns t3 20 50 – ns t4 70 250 – ns t5, t6 0 25 – ns t7 30 50 – ns t8, t9 0 25 – ns t10 30 50 – ns t11 5 15 – ns t12 5000 10000 – ns t13, t14 0 50 – ns t15, t16 900 1000 – ns φ1, φ2 cross points φ1 2.0 V or more 2.0 V or more φ2 Remark Adjust cross points of φ1 and φ2 with input resistance of each pin. 10 Data Sheet S14374EJ2V0DS µPD3778 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 10600 Σx x= j j=1 10600 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10600 Σd ADS (mV) = j j=1 10600 dj : Dark signal of valid pixel number j 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 10600 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU Data Sheet S14374EJ2V0DS 11 µPD3778 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG Light ON OFF VOUT V1 VOUT V1 IL (%) = 9. VOUT ×100 Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j= 1 RI (%) = n 1 n × 100 ∑ Vj j= 1 n : Number of valid pixels Vj : Output voltage of each pixel 12 Data Sheet S14374EJ2V0DS µPD3778 10. Random noise (CDS): σCDS Random noise (CDS) σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). σCDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the Video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by “VCDSi = VDi – VOi”. 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σCDS using the following formula. 100 σCDS (mV) = Σi=1 (VCDS – V) i 2 , V= 100 1 100 Σ VCDS i 100 i=1 Reset feed-through VOUT Video output Data Sheet S14374EJ2V0DS 13 µPD3778 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 2 1 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA(°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 °C) 100 R G B Response Ratio (%) 80 60 40 G 20 B 0 400 500 600 Wavelength (nm) 14 Data Sheet S14374EJ2V0DS 700 800 µPD3778 APPLICATION CIRCUIT EXAMPLE µ PD3778 1 47 Ω φ RB 47 Ω φ CLB 2 3 32 GND VOUT3 φ RB VOUT2 φ CLB VOUT1 B3 31 B2 +12 V 30 4 B1 10 Ω 29 VOD NC + 5 28 NC NC +5 V 6 0.1 µ F 27 IC IC IC IC NC NC 7 47 µ F/25 V +5 V 26 + 8 25 + 10 µ F/16 V 0.1 µ F 9 24 NC NC 10 4.7 Ω φ1 11 NC NC φ1 φ2 IC IC IC IC φ2 φ1 12 4.7 Ω 4.7 Ω φ TG 14 15 22 10 µ F/16 V 4.7 Ω 21 13 φ2 0.1 µ F 23 20 φ TG3 φ TG1 GND φ TG2 16 19 4.7 Ω 18 4.7 Ω 17 4.7 Ω Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remark The inverters shown in the above application circuit example are the 74HC04 or 74AC04. Data Sheet S14374EJ2V0DS 15 µPD3778 B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 µF/25 V 2SC945 2 kΩ 16 Data Sheet S14374EJ2V0DS µPD3778 PACKAGE DRAWING µ PD3778CY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 55.2±0.5 54.8±0.5 1st valid pixel 6.15±0.3 1 32 1 9.25±0.3 9.05±0.3 17 16 46.7 2.0 12.6±0.5 4.1±0.5 10.16±0.20 4.55±0.5 1.02±0.15 (1.80) 2 2.58±0.3 0.46±0.1 (5.42) 2.54±0.25 4.21±0.5 3 0.25±0.05 10.16 +0.7 −0.2 Name Dimensions Refractive index Plastic cap 52.2×6.4×0.7 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 32C-1CCD-PKG7-1 Data Sheet S14374EJ2V0DS 17 µPD3778 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µPD3778CY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per pin) Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 18 Data Sheet S14374EJ2V0DS µPD3778 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S14374EJ2V0DS 19 µPD3778 [MEMO] 20 Data Sheet S14374EJ2V0DS µPD3778 [MEMO] Data Sheet S14374EJ2V0DS 21 µPD3778 [MEMO] 22 Data Sheet S14374EJ2V0DS µPD3778 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14374EJ2V0DS 23 µPD3778 • The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4