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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µPD4702 INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS DESCRIPTION The µ PD4702 is 8-bit up/down counters for an incremental encoder. Two-phase (A, B) incremental input signals are phase-differentiated, and on each signal edge, an up-count is executed if the A phase is leading, or a down-count if the B phase is leading. Eight-bit count data is output in real time. A carry output and borrow output are also provided for counter overflow and underflow. The µ PD4704 is also available; use of these enables the count width to be extended. PIN CONFIGURATION (Top View) FEATURES • Incremental inputs (A, B) • On-chip phase discrimination circuit (up-count mode when the phase order is A → B, down-count mode when B → A) 4-multiplication count method • On-chip edge detection circuit • 8-bit up/down counter latch output • Carry output, borrow output • Count data output controllable (3-state output) • CMOS, single +5 V power supply ★ ORDERING INFORMATION Part Number Package µPD4702C 20-pin plastic DIP µ PD4702G 20-pin plastic SOP (7.62 mm (300) ) Reset 1 20 VDD A 2 19 Carry B 3 18 Borrow NC 4 17 STB CD0 5 16 OE CD1 6 15 CD7 CD2 7 14 CD6 CD3 8 13 CD5 NC 9 12 CD4 VSS 10 11 NC (7.62 mm (300) ) PIN NAMES A B Reset : STB : OE : CD0 to CD 7 : Carry : Borrow : 2-phase incremental signal inputs Counter reset input Latch strobe signal input Output control signal input Count data outputs Carry pulse output Borrow pulse output The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S14940EJ3V0DS00 (3rd edition) (Previous No. IC-3304A) Date Published January 2004 N CP(K) Printed in Japan The mark shows major revised points. 1993 µPD4702 BLOCK DIAGRAM Reset A Carry Phase Discrimination Edge Detection 8-Bit Up/Down Counter B Borrow 8-Bit Latch 3-State Output STB OE CD0 to CD7 PIN FUNCTIONS Pin Name 2 Input/Output Function A, B Input (Schmitt) Incremental signal A phase and B phase signal input pins (Schmitt input) CD0 to CD 7 Output (3-state) Count data output pins. Activated when OE is “L”, high impedance outputs when OE is “H”. 8-bit counter carry signal output pin (active-low) Carry Output 8-bit counter borrow signal output pin (active-low) Borrow Output 8-bit counter reset signal output pin RESET Input (Schmitt) Counter is reset when this pin is “H”. OE Input Count data output control signal input pin STB Input Counter data output latch signal. Data is latched on the fall of STB, and is held while STB = “L”. VDD – Power supply input pin GND – Ground pin Data Sheet S14940EJ3V0DS µPD4702 1. DESCRIPTION OF OPERATIONS (1) Count operation The µ PD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2-phase pulses. Therefore, a count operation is performed by an A input edge and a B input edge. Figure 1–1. Count Operation Timing Chart Forward (Up-Count) Reverse (Down-Count) A Input Count Operation 1 2 3 4 5 4 3 2 1 0 B Input (2) Latch operation An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Figure 1–2, and when STB changes from “H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation. Therefore, the count value is latched correctly even if STB input is performed asynchronously from the A and B input (if STB changes from “H” to “L” within tSABSTB (40 ns) after the A input or B input edge, the latch contents will be either the pre-count or postcount value). However, when a µ PD4704 is added, the correct value cannot be latched if all digits are latched simultaneously when a carry or borrow is generated (the high-order digit may be latched before carry/borrow transmission). Figure 1–2. STB Input Circuit From Phase Discrimination Circuit (Count Pulse) STB STB Latched when L A, B Inputs tSABSTB STB If tSABSTB is 40 ns or longer, the post-count value is input to the latch. Data Sheet S14940EJ3V0DS 3 µPD4702 (3) Carry & borrow outputs If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the Carry output (the pulse width is 25 ns MIN. 120 ns MAX. irrespective of the A/B phase input cycle. Similarly, if the counter performs a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output. A Borrow pulse is also output if a down-count operation is performed while RESET is “H” (during a reset), and therefore, when a µPD4704 is added, a reset must be executed at the same time. 4 Data Sheet S14940EJ3V0DS µPD4702 2. OPERATING PRECAUTIONS As the µPD4702 incorporates an 8-bit counter, a large transient current flows in the case of a count value which changes all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 µF) be connected between VDD and V SS right next to the IC as shown in Figure 2–1. Figure 2–1. Decoupling Capacitor +5 V C VDD µ PD4702 C : 0.1 µ F tantalum electrolytic laminated ceramic capacitor, etc. VSS Also, if a pulse shorter than the phase difference time tSAB (70 ns) is input to the A/ B phase inputs, this will result in a miscount. Therefore, if this kind of pulse is to be input because of encoder bounds, etc., a filter should be inserted in the A & B phase inputs. Figure 2–2. A & B Phase Input Pulses A Phase (or B Phase) B Phase (or A Phase) PW If a pulse such that PW < 70 ns is input in the A or B phase, there is a danger of a miscount. If PW is at 70 ns or more, the count value remains the same before and after pulse input. (UP count → DOWN count or DOWN count → UP count is implemented, and therefore the the result is no change in the count value.) Data Sheet S14940EJ3V0DS 5 µPD4702 3. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, V SS = 0 V) PARAMETER SYMBOL RATING UNIT VDD –0.5 to +7.0 V Input voltage VI –1.0 to VDD +1.0 V Output voltage VO –0.5 to VDD +0.5 V Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Permissible loss PD Supply voltage 500 (DIP) 200 (SOP) mW DC CHARACTERISTICS (T A = –40 to +85 °C, VDD = +5 V ±10 %) RATING PARAMETER SYMBOL TEST CONDITIONS UNIT MIN. Input voltage high VIL MAX. 0.8 V VIH A, B, Reset 2.6 V VIH Other than the above 2.2 V Output voltage low VOL I OL = 12 mA Output voltage high VOH I OH = –4 mA Static consumption current I DD VI = VDD, V SS II VI = VDD, V SS Input voltage low Input current 3-state output leak current Dynamic consumption current Hysteresis voltage I OFF I DD dyn VH 0.45 VDD – 0.8 V 50 µA –1.0 1.0 µA –10 10 µA 12 mA f IN = 3.6 MHz, CL = 50 pF A, B, Reset V 0.2 V AC CHARACTERISTICS (TA = –40 to +85 °C, V DD = +5 V ±10 %) PARAMETER Cycle t CYAB High-level width Low-level width TEST CONDITIONS MAX. UNIT ns tPWABH 140 ns tPWABL 140 ns t SAB 70 ns Setting time t SRSAB 0 ns Reset time t DRSCD 60 ns Output delay tDABCD 100 ns Output delay t DOECD 50 ns Output delay t DSTBCD 60 ns Float time tFOECD 40 ns Carry Output delay tDABCB 120 ns Borrow Output pulse width t PWCB 25 120 ns RESET Reset pulse width t PWRS 40 ns STB Setting time t SABSTB 40 ns Phase difference time CD0 to CD7 f IN = 3.6 MHz MIN. 280 A, B 6 SYMBOL Data Sheet S14940EJ3V0DS µPD4702 AC Timings Figure 3–1. Two-Phase Signal Input Timing tCYAB tPWABH tPWABL A tSAB tSAB tSAB tSAB B tPWABH tPWABL tCYAB Figure 3–2. Count Data Output Timing tPWRS Reset tSRSAB tSABSTB A/B tDRSCD tDABCD tDSTBCD CD0–7 tDOECD tFOECD OE STB Figure 3–3. Carry/Borrow Signal Output Timing A/B (CD) (0FEH) (0FFH) (00) (01) (00) (0FFH) (0FEH) (0FDH) tDABCB Carry tPWCB tDABCB Borrow tPWCB Data Sheet S14940EJ3V0DS 7 µPD4702 Consumption Current Measurement Circuit Measurement Conditions A, B inputs fIN = 3.6 MHz A D0 CL B 2.6 V D1 CL 0.8 V STB input connected to VDD or VDD OE input connected to VSS. STB Load on all outputs, CL = 50 pF. OE D7 CL AC Test Input Waveform VIH VIL VIH = 2.6 V (A, B, RESET inputs) VIH = 2.2 V (inputs other than A, B, RESET) VIL = 0.8 V Timing measurement is performed at 1.5 V. 8 Data Sheet S14940EJ3V0DS µPD4702 4. SAMPLE APPLICATION CIRCUITS 16-bit counter 8 Data Bus Incremental Rotary Encoder A 8 Carry B Borrow 8 UP Down CD0 CD0 STB STB OE OE R CD7 RCD7 RESET µ PD4702 µPD4704 CSL CSH The application circuits and their parameters are for references only and are not intended for use in actual design-in's. Data Sheet S14940EJ3V0DS 9 µPD4702 ★ 5. PACKAGE DRAWINGS 20-PIN PLASTIC DIP (7.62mm(300)) 20 11 1 10 A K J H L P I C F B G D N R M M NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. ltem "K" to center of leads when formed parallel. ITEM MILLIMETERS A B 25.40 MAX. 1.27 MAX. C 2.54 (T.P.) D F 0.50±0.10 1.1 MIN. G H 3.5±0.3 0.51 MIN. I 4.31 MAX. J 5.08 MAX. K 7.62 (T.P.) L 6.4 M 0.25 +0.10 −0.05 N 0.25 P 0.9 MIN. R 0∼15° P20C-100-300A,C-2 10 Data Sheet S14940EJ3V0DS µPD4702 20-PIN PLASTIC SOP (7.62 mm (300)) 20 11 detail of lead end P 1 10 A H I G J S L B C D M M N K S E F NOTE ITEM Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 12.7±0.3 B 0.78 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.1±0.1 F 1.8 MAX. G 1.55±0.05 H 7.7±0.3 I 5.6±0.2 J 1.1 K 0.22 +0.08 −0.07 L M 0.6±0.2 0.12 N 0.10 P 3° +7° −3° P20GM-50-300B, C-7 Data Sheet S14940EJ3V0DS 11 µPD4702 ★ 6. RECOMMENDED SOLDERING CONDITIONS The µPD4702 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) TYPES OF SURFACE MOUNT DEVICE µPD4702G Soldering process * Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Number of reflow process: 3, Exposure limit* : None IR35-00-3 VPS Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Number of reflow process: 3, Exposure limit* : None VP15-00-3 Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit* : None WS60-00-1 Partial heating method Terminal temperature: 300 °C or below, Flow time: 10 seconds or below, Exposure limit* : None Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Caution Do not use different soldering methods together (except for partial heating) . TYPES OF THROUGH HOLE MOUNT DEVICE µPD4702C Process Conditions Wave soldering (only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or below Partial Heating Method Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per each lead). Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered. 12 Data Sheet S14940EJ3V0DS µPD4702 ★ REFERENCE DOCUMENTS NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades on NEC Semiconductor Devices (C11531E) Guide to Quality Assurance for Semiconductor devices (MEI-1202) Semiconductor Selection Guide - Products and Packages - (X13769X) Data Sheet S14940EJ3V0DS 13 µPD4702 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 14 Data Sheet S14940EJ3V0DS µPD4702 • The information in this document is current as of January, 2004. The information is subject to change without notice. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1