PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer FEATURES • • • • • • • • • • • Four differential 2.5V/3.3V LVPECL output pairs. Output Frequency: ≤ 1GHz. Two selectable differential input pairs. Translates any standard single-ended or differential input format to LVPECL output. It can accept the following standard input formats and more: o LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML. Output Skew: 25ps (typ.). Part-to-part skew: 140ps (typ.). Propagation delay: 1.5ns (typ.). Additive Jitter: <100 fs (typ.). Operating Supply Voltage: 2.375V ~ 3.63V. Operating temperature range from -40°C to 85°C. Package availability: 20-pin TSSOP. DESCRIPTION The PL138-48 is a high performance low-cost 1: 4 outputs Differential LVPECL fanout buffer. PhaseLink’s family of Differential LVPECL buffers are designed to operate from a single power supply of 2.5V±5% or 3.3V±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to lot skew. Designed to fit in a small form-factor package, PL138 family offers up to 1GHz of output operation with very low-power consumption, and lowest additive jitter of any comparable device. BLOCK DIAGRAM VEE 1 20 Q0 CLK-EN 2 19 Q0B CLK_SEL 3 18 VCC CLK-IN0 4 17 Q1 CLK-IN0B 5 16 Q1B CLK-IN1 6 15 Q2 CLK-IN1B 7 14 Q2B DNC 8 13 VCC DNC 9 12 Q3 10 11 Q3B VCC 20-Pin TSSOP Package 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 1 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer PIN DESCRIPTIONS Package Pin # LQFP-20 Type (Mode) VEE 1 Power CLK-EN 2 Input (Pullup) CLK-SEL 3 Input (Pulldown) CLK-IN0 4 Input (Pulldown) CLK-IN0B 5 Input (Pullup/Pulldown) CLK-IN1 6 Input (Pulldown) CLK-IN1B 7 Input (Pullup/Pulldown) DNC 8, 9 - Vcc 10, 13, 18 Power Power Supply pin connection QB0 ~ QB3 11, 14, 16, 19 Output LVPECL Complementary output Q0 ~ Q3 12, 15, 17, 20 Output LVPECL True output Name Description Power Supply pin connection Synchronizing clock enable. When HIGH, clock outputs follow clock input. When ‘Low’, Q outputs are forced low, QB outputs are forced high. LVTTL / LVCMOS interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVTTL / LVCMOS interface levels. True part of differential clock input signal. Complementary part of differential clock input signal. True part of differential clock input signal. Complementary part of differential clock input signal. Do Not Connect. INPUT PIN CHARACTERISTICS INPUT LOGIC BLOCK DIAGRAM Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Min. Typ. 75 100 Max. Units kΩ kΩ INPUT CLOCK CONTROL SELECTION CLK_SEL 0 1 Selected Source CLK-IN0 CLK-IN1 INPUT CLOCK FUNCTION Inputs Outputs CLK-EN CLKSEL Source Q0:Q3 Q0B:Q3B 0 0 CLK-IN0 Disabled Low Disabled High 0 1 CLK-IN1 Disabled Low Disabled High 1 0 CLK-IN0 Enabled Enabled 1 1 CLK-IN1 Enabled Enabled 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 2 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 110 °C 260 °C Lead Temperature (soldering, 10s) ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Parameter Output High Voltage* Output Low Voltage* Input High Voltage Input Low Voltage Output Voltage Reference** Input High Voltage Common Mode Range † †† Input High CLK-IN0, Current CLK-IN1 CLK-IN0B, Input Low Current CLK-IN1B Symbol Min VOH VOL VIH VIL VBB 2.215 1.470 2.075 1.470 1.86 VCMR 1.2 IIH IIL -40°C Typ 2.320 1.610 Max Min 2.420 1.745 2.420 1.890 1.98 2.275 1.490 2.135 1.490 1.92 3.3 1.2 75 -75 25°C Typ 2.350 1.585 Max 2.420 1.680 2.420 1.825 2.04 3.3 Min 80°C Typ Units 2.275 2.35 2.420 1.490 1.585 1.680 2.135 2.420 1.490 1.825 1.92 2.04 1.2 75 -75 Max 3.3 V 75 µA -75 µA Input and output parameters vary 1:1 with VCC when VCC varies ±10%. * Outputs terminated with 50Ω to VCCO – 2V. ** Single-ended input operation is limited to VCC ≥ 3V in LVPECL mode. . † Common mode voltage is defined as VIH †† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com V V V V V Rev 06/06/12 Page 3 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Parameter Symbol Output High Voltage* Output Low Voltage* Input High Voltage Input Low Voltage Input High Voltage Common Mode Range† Input High CLK-IN0, Current CLK-IN1 CLK-IN0B, Input Low Current CLK-IN1B -40°C Typ Min VOH VOL VIH VIL 1.415 0.670 1.275 0.670 VCMR 1.2 1.520 0.810 Max Min 1.620 0.945 1.620 1.090 1.475 0.690 1.335 0.690 2.5 1.2 IIH 25°C Typ 1.550 0.785 -60 1.620 0.880 1.620 1.025 2.5 60 IIL Max Min 80°C Typ V V V V 1.475 1.55 1.620 0.690 0.785 0.880 1.335 1.620 0.690 1.025 1.2 2.5 V 60 µA 60 -60 Units Max -60 µA Input and output parameters vary 1:1 with VCC when VCC varies ±5%. * Outputs terminated with 50Ω to VCCO – 2V. V . ** Common mode voltage is defined as IH † For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V AC Electrical Characteristics VCC = -3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Parameter Symbol Output Frequency fMAX Propagation Delay* tPD Min -40°C Typ Max Min 25°C Typ 700 600 680 750 Max Min 80°C Typ 700 650 725 790 690 Max Units 700 MHz 790 890 ps Output Skew ** † tsk(o) 25 37 25 37 25 37 ps Part-to-Part Skew *** † tsk(pp) 85 225 85 225 85 225 ps tAPJ 0.10 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Peak-to-Peak Input Voltage (Differential Configuration) Output Rise/Fall Time 20% to 80% VPP 150 tR / tF 200 800 0.10 1200 150 700 200 800 0.10 1200 150 700 200 800 ps 1200 mV 700 ps All parameters are measured at f ≤ 700MHz, unless otherwise noted. * Measured from the differential input crossing point to the differential output crossing point. ** Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. *** Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. †This parameter is defined in accordance with JEDEC Standard 65. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 4 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter tAPJ Description Test Conditions Additive Phase Jitter Typ. Max. Unit V DD = 3.3V, Frequency = 622.08MHz Offset = 12KHz ~ 20MHz 20 40 fs V DD = 3.3V, Frequency = 156.25MHz Offset = 12KHz ~ 20MHz 50 100 fs V DD = 3.3V, Frequency = 50MHz Offset = 1KHz ~ 1MHz 50 100 fs V DD = 3.3V, Frequency = 25MHz Offset = 1KHz ~ 1MHz 50 100 fs REF Input Min. PL138-48 Output -60 Carrier = 622.08MHz -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 2 www.phaselink.com Rev 06/06/12 Page 5 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer PARAMETER MEASUREMENT INFORMATION Output W aveform Test Circuit: Differential Input Level: +2.0V VCC OSCILLOSCOPE VCC 50 Ω Channel 50 Ω Line LVPECL CLK-INxB Cross Points V PP CLK-INx VEE 50 Ω Channel 50 Ω Line V CMR VEE -1.80V to -0.375V Part-to-Part Skew: Output Skew: QBx QBx Part 1 Qx Qx QBy QBy Part 2 Qy Qy tsk(o) tsk(pp) Output Rise/Fall Time: Qx 80% Propagation Delay: CLK-INxB 80% CLK-INx QBx 20% 20% tR QBy tF Qy t PD 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 6 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer APPLICATION INFORMATION The following circuits show different configurations for different input logic type signals. For good signal integrity at the PL138 input, the signals need to be properly terminated according to the logic type requirements. The signals need to be presented at the PL138 input according to V CMR , V PP and other input requirements. CLK-IN Input Driven by a 3.3V LVPECL Driver: +3.3V +3.3V 130 +3.3V 3.3V LVPECL Driver, Alternative Termination: +3.3V +3.3V PL138 130 PL138 50 Ω Line 50 Ω Line LVPECL CLK-INx LVPECL 50 Ω Line CLK-INx 50 Ω Line 82 82 50 50 50 CLK-IN Input Driven by a CML Driver: +3.3V CLK-IN Input Driven by an SSTL Driver: +3.3V 50 +3.3V +2.5V +2.5V PL138 50 120 50 Ω Line PL138 120 50 Ω Line CML CLK-INx SSTL CLK-INx 50 Ω Line 50 Ω Line 120 CLK-IN Input Driven by an LVDS Driver: +2.5V or +3.3V 120 LVDS Driver, Alternative AC Coupling: +2.5V or +3.3V +2.5V or +3.3V +2.5V or +3.3V 1K PL138 PL138 1K 50 Ω Line 50 Ω Line LVDS +3.3V 100 CLK-INx LVDS CLK-INx 100 50 Ω Line 50 Ω Line 1K 1K This circuit is for compatibility only. AC coupling is not really required for LVDS. The V CMR range of the PL138 reaches low enough that LVDS signals can be connected directly to the PL138 input like in the circuit to the left. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 7 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer CLK-IN Input Driven by a CMOS Driver: CLK-IN Input Driven by Single Ended LVPECL: +3.3V +2.5V or +3.3V +3.3V PL138 PL138 130 1K CMOS LVPECL CLK-INx 1K 50 Ω Line 0.1µF CLK-INx 1K 82 0.1µF CLK-IN Input Driven by an HCSL Driver: +2.5V or +3.3V +2.5V or +3.3V 1K PL138 1K 50 Ω Line HCSL CLK-INx HCSL presents its signals very close to the ground rail, below the V CMR range, so the HCSL signals can not be connected to the PL138 input directly. AC coupling is required for HCSL signals on the PL138 input. 50 Ω Line 50 50 1K 1K TERMINATION FOR LVPECL OUTPUTS The required termination for LVPECL is 50Ω to a V CC -2V DC voltage level. Below are two schematics to implement this termination. LVPECL Termination Schematic #1: VCC R1 PL138 Qx Buffer LVPECL Termination Schematic #2: VCC VCC R1 50 Ω Line Target LVPECL Input 50 Ω Line R2 PL138 Qx Buffer 50 Ω Line Target LVPECL Input 50 Ω Line R2 50 50 RT VCC=3.3V, Ideal values: R1=127 Ω , R2=82.5 Ω Commercial values (E24): R1=130 Ω , R2=82 Ω VCC=2.5V, Ideal values: R1=250 Ω , R2=62.5 Ω Commercial values (E24): R1=240 Ω , R2=62 Ω Schematic #2 is an alternative simplified termination. VCC=3.3V, Ideal value: RT=48.7 Ω Commercial value: RT=50 Ω (E24: 51 Ω) VCC=2.5V, Ideal value: RT=18.7 Ω Commercial value: RT=18 Ω 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 8 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer POWER CONSIDERATIONS Driving LVPECL outputs requires an amount of power that can warm up the chip significantly. The general requirement for the chip is that the junction temperature should not exceed +110°C. The power consumption can be divided into two parts: 1) Core power dissipation 2) Output buffers power dissipation CORE POWER DISSIPATION The chip core power is equal to VCC×IEE. With a worst case VCC and IEE the power dissipation in the core is 3.63V×45mA=163mW. OUTPUT BUFFER POWER DISSIPATION The output buffers are not exposed to the full VCC-VEE voltage. On the differential output, one line is at logic 1 with a small voltage across the buffer and a large output current. The other line is at logic 0 with a larger voltage across the buffer and a smaller output current. The power dissipation per output buffer is 32mW. Only buffers that are loaded will have power dissipation. With all 4 buffers loaded the worst case output buffer power dissipation will be 128mW. Total Chip Power Dissipation, worst case, is 163mW + 128mW = 291mW. JUNCTION TEMPERATURE How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to the environment, also known as “junction to ambient”. The thermal resistance depends upon the type of package, how the package is assembled to the PCB and if there is additional air flow for improved cooling. For the TSSOP package the thermal resistance is as follows: TSSOP 20-pin Package JEDEC Standard Multi Layer PCB Air Flow Velocity in Linear Feet per Minute 0 200 500 θ JA = 73°C/W θ JA = 67°C/W θ JA = 64°C/W The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θ JA × Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature T J = 85°C+73×0.291 = 106°C. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 9 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer PACKAGE DRAWING (GREEN PACKAGE COMPLIANT) TSSOP173 20L 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 10 PL138-48 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer ORDERING INFORMATION (GREEN PACKAGE) For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134 USA Tel (408) 571-1668 Fax (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL138-48OC Marking P138-48 OC LLLLL Package Option 20-Pin TSSOP (Tube) *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/06/12 Page 11