Preliminary Datasheet TBB1016 R07DS0318EJ0300 (Previous: REJ03G1327-0200) Rev.3.00 Mar 28, 2011 Twin Built in Biasing Circuit MOS FET IC VHF/VHF RF Amplifier Features • • • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Very useful for total tuner cost reduction. Suitable for World Standard Tuner RF amplifier. High gain; PG = 32 dB at 200 MHz Low noise; NF = 1.0 dB at 200 MHz Power supply voltage: 5 V Outline RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6) 6 5 4 2 1. Drain(1) 2. Source 3. Drain(2) 4. Gate-1(2) 5. Gate-2 6. Gate-1(1) 3 1 Notes: 1. Marking is “RM”. 2. TBB1016 is indivisual type number of RENESAS TBBFET. Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S Ratings 6 Unit V +6 –0 V Gate2 to source voltage VG2S +6 –0 30 250 150 –55 to +150 V Drain current Channel power dissipation Channel temperature Storage temperature Note: ID PchNote3 Tch Tstg mA mW °C °C 3. Value on the glass epoxy board (50 mm × 40 mm × 1 mm) R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 Page 1 of 9 TBB1016 Preliminary Electrical Characteristics • The below specification are applicable for FET1 and FET2 unit (Ta = 25°C) Drain to source breakdown voltage Item Symbol V(BR)DSS Min 6 Typ — Max — Unit V Test Conditions ID = 200 μA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V(BR)G1SS +6 — — V IG1 = +10 μA, VG2S = VDS = 0 Gate2 to source breakdown voltage Gate1 to source cutoff current V(BR)G2SS +6 — — V IG2 = +10 μA, VG1S = VDS = 0 IG1SS — — +100 nA VG1S = +5 V, VG2S = VDS = 0 Gate2 to source cutoff current IG2SS — — +100 nA VG2S = +5 V, VG1S = VDS = 0 Gate1 to source cutoff voltage VG1S(off) 0.5 0.8 1.1 V VDS = 5 V, VG2S = 4 V, ID = 100 μA Gate2 to source cutoff voltage VDS = 5 V, VG1S = 5 V, ID = 100 μA VG2S(off) 0.4 0.7 1.0 V Drain current ID(op) 11 15 19 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ Forward transfer admittance |yfs| 30 35 42 mS VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 120 kΩ Input capacitance Ciss 1.8 2.2 2.6 pF Output capacitance VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 120 kΩ Coss 0.9 1.3 1.7 pF Power gain PG 27 32 37 dB Noise figure NF — 1.0 1.7 dB R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ, f = 200 MHz Page 2 of 9 TBB1016 Preliminary DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, NF, PG) • Measurement of FET1 VG2 Gate 2 RG Gate 1(1) Open Drain (1) Open VG1 ID VD A Source • Measurement of FET2 VG2 Gate 2 Open Gate1(2) RG VG1 A Drain (2) Open ID VD Source R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 Page 3 of 9 TBB1016 Preliminary 200 MHz Power Gain, Noise Figure Test Circuit 1000 p 1000 p 47 k Input (50 Ω) VT VG2 VT 1000 p 47 k 47 k 1000 p 1000 p L2 L1 10 p max 1000 p 1000 p 36 p Output (50 Ω) RFC HVU202A HVU202A R1 1000 p VG1 1000 p VD Unit : Resistance (Ω) Capacitance (F) R1 : 120 kΩ L1 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns L2 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns RFC : φ1 mm Enameled Copper Wire, Inside dia 5 mm, 2 Turns R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 Page 4 of 9 TBB1016 Preliminary Main Characteristics Typical Output Characteristics 400 25 200 100 0 50 100 150 15 kΩ 0 15 kΩ 0 18 kΩ 0 22 10 5 0 200 R G= 10 82 0k kΩ kΩ Ω 20 0 300 VG2S = 4 V VG1 = VDS 12 Drain Current ID (mA) Channel Power Dissipation Pch* (mW) Maximum Channel Power Dissipation Curve Ambient Temperature Ta (°C) 1 2 3 4 5 Drain to Source Voltage VDS (V) * Value on the glass epoxy board (50 mm × 40 mm × 1 mm) Forward Transfer Admittance vs. Gate1 Voltage Drain Current ID (mA) 25 VDS = 5 V RG = 120 kΩ 20 4V 15 3V 10 2V 5 VG2S = 1 V 0 1 2 3 4 5 Forward Transfer Admittance |yfs| (mS) Drain Current vs. Gate1 Voltage 50 VDS = 5 V RG = 120 kΩ 40 f = 1 kHz 3V 30 2V 20 10 VG2S = 1 V 0 1 Gate1 Voltage VG1 (V) 4 5 5 Input Capacitance Ciss (pF) Drain Current ID (mA) 3 Input Capacitance vs. Gate2 to Source Voltage 30 25 20 15 10 0 10 2 Gate1 Voltage VG1 (V) Drain Current vs. Gate Resistance 5 4V VDS = VG1 = 5 V VG2S = 4 V 4 3 2 0 20 50 100 200 500 1000 Gate Resistance RG (kΩ) R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 VDS = VG1 = 5 V RG = 120 kΩ f = 1 MHz 1 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Page 5 of 9 TBB1016 Preliminary Power Gain vs. Gate Resistance Noise Figure vs. Gate Resistance 3 Noise Figure NF (dB) Power Gain PG (dB) 35 25 15 VDS = VG1 = 5 V VG2S = 4 V f = 200 MHz 5 10 20 50 100 200 1 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage Noise Figure vs. Gate2 to Source Voltage 5 Noise Figure NF (dB) Power Gain PG (dB) 2 0 10 500 1000 40 30 20 10 0 VDS = VG1 = 5 V VG2S = 4 V f = 200 MHz VDS = VG1 = 5 V RG = 120 kΩ f = 200 MHz 1 2 3 VDS = VG1 = 5 V RG = 120 kΩ f = 200 MHz 4 3 2 1 0 4 Gate2 to Source Voltage VG2S (V) 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage Gain Reduction GR (dB) 50 VDS = VG1 = 5 V RG = 120 kΩ f = 200 MHz 40 30 20 10 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 Page 6 of 9 TBB1016 Preliminary S11 Parameter vs. Frequency .8 S21 Parameter vs. Frequency 1 Scale: 5 / div. 90° 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 .2 0 .4 .6 .8 1 1.5 2 3 45 180° 0° –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –.6 –.8 –120° –1.5 –60° –1 –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ 0.05 to 1.0 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ 0.05 to 1.0 GHz (0.05 GHz step) S12 Parameter vs. Frequency 90° S22 Parameter vs. Frequency Scale: 0.05 / div. .8 1 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1 1.5 2 3 45 –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –120° –60° –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ 0.05 to 1.0 GHz (0.05 GHz step) R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 –.6 –.8 –1.5 –1 Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ 0.05 to 1.0 GHz (0.05 GHz step) Page 7 of 9 TBB1016 Preliminary S parameter (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 120 kΩ, Zo = 50 Ω) Freq. (MHz) S11 S21 S12 S22 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 Mag 0.994 0.992 0.987 0.985 0.975 0.967 0.960 0.952 0.940 0.934 0.914 0.904 0.892 0.881 0.870 0.855 Deg –3.7 –7.6 –11.1 –14.8 –18.6 –21.9 –25.4 –28.9 –32.2 –35.7 –38.8 –42.1 –45.4 –48.8 –51.5 –54.4 Mag 3.73 3.72 3.72 3.70 3.71 3.69 3.68 3.65 3.64 3.62 3.58 3.58 3.55 3.52 3.51 3.49 Deg 175.3 170.7 166.1 161.7 157.0 152.9 148.1 143.8 138.9 134.7 130.0 125.9 121.4 116.9 112.5 107.9 Mag 0.002 0.003 0.004 0.004 0.005 0.005 0.004 0.006 0.006 0.006 0.006 0.006 0.005 0.004 0.004 0.004 Deg 88.4 107.7 54.7 62.4 81.1 83.3 65.3 68.8 77.6 69.3 77.0 45.7 66.8 52.5 93.5 92.7 Mag 0.992 0.996 0.992 0.990 0.990 0.984 0.982 0.982 0.972 0.971 0.965 0.959 0.955 0.948 0.949 0.941 Deg –2.4 –5.1 –7.2 –9.6 –12.0 –14.6 –17.1 –19.4 –21.9 –24.6 –26.9 –29.9 –32.5 –35.6 –38.3 –41.4 850 900 950 1000 0.839 0.827 0.809 0.796 –57.5 –60.3 –62.8 –65.7 3.47 3.48 3.43 3.43 103.7 99.3 95.0 90.3 0.004 0.004 0.005 0.007 121.0 140.2 167.7 171.4 0.936 0.929 0.921 0.921 –44.4 –47.7 –50.9 –54.5 R07DS0318EJ0300 Rev.3.00 Mar 28, 2011 Page 8 of 9 TBB1016 Preliminary Package Dimensions JEITA Package Code SC-88 Package Name CMPAK-6 RENESAS Code PTSP0006JA-A D Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g A e Q c E HE LP L A A x M L1 S A3 b A Reference Symbol e A2 A A1 y S S e1 b l1 c b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b c D E e HE L L1 LP x y b2 e1 l1 Q Dimension in Millimeters Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.2 0.15 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.25 0.25 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 1.5 0.9 0.25 Ordering Information Part Name TBB1016RMTL-E TBB1016RMTL-H Note: Quantity 3000 pcs Shipping Container φ178mm reel, 8mm emboss taping For some grades, production may be terminated. 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