Datasheet

74VHC08; 74VHCT08
Quad 2-input AND gate
Rev. 01 — 30 June 2009
Product data sheet
1. General description
The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
2. Features
n
n
n
n
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than VCC
Input levels:
u The 74VHC08 operates with CMOS logic levels
u The 74VHCT08 operates with TTL logic levels
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V
n Multiple package options
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
74VHC08D
Package
Temperature range
Name
Description
Version
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
−40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
−40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74VHCT08D
74VHC08PW
74VHCT08PW
74VHC08BQ
74VHCT08BQ
SOT762-1
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
4. Functional diagram
1
&
3
&
6
2
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
1Y
3
4
2Y
6
5
3Y
8
9
A
Y
&
8
B
10
4Y
mna221
11
12
mna222
&
11
13
mna223
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
1A
terminal 1
index area
14 VCC
74VHC08
74VHCT08
74VHC08
74VHCT08
1
14 VCC
1B
2
13 4B
1B
2
13 4B
1Y
3
12 4A
2A
4
2B
5
2Y
6
1
1A
4
11 4Y
10 3B
2B
5
2Y
6
9
3A
GND
7
8
3Y
11 4Y
GND(1)
10 3B
9
8
2A
3Y
12 4A
7
3
GND
1Y
3A
001aak041
Transparent top view
001aak040
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
2 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A
1
data input
1B
2
data input
1Y
3
data output
2A
4
data input
2B
5
data input
2Y
6
data output
GND
7
ground (0 V)
3Y
8
data output
3A
9
data input
3B
10
data input
4Y
11
data output
4A
12
data input
4B
13
data input
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nY
L
X
L
X
L
L
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
Conditions
Min
Max
Unit
−0.5
+7.0
V
−0.5
+7.0
V
−20
-
mA
-
±20
mA
-
±25
mA
input clamping current
VI < −0.5 V
[1]
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
ICC
supply current
-
75
mA
IGND
ground current
−75
-
mA
Tstg
storage temperature
−65
+150
°C
IIK
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
3 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
Min
Max
Unit
SO14 package
[2]
-
500
mW
TSSOP14 package
[3]
-
500
mW
DHVQFN14 package
[4]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 °C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 °C.
[4]
Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74VHC08
74VHCT08
Unit
Min
Typ
Max
Min
Typ
Max
VCC
supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
0
-
5.5
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
−40
+25
+125
−40
+25
+125
°C
∆t/∆V
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
-
-
100
-
-
-
ns/V
VCC = 5.0 V ± 0.5 V
-
-
20
-
-
20
ns/V
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
1.5
-
-
1.5
-
1.5
-
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
For type 74VHC08
VIH
VIL
VOH
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = −50 µA; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = −50 µA; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = −4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.4
-
V
IO = −8.0 mA; VCC = 4.5 V
3.94
-
-
3.8
-
3.7
-
V
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
4 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
LOW-level
VI = VIH or VIL
output voltage
IO = 50 µA; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
µA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
µA
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
For type 74VHCT08
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = −50 µA
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.8
-
3.7
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
µA
IO = −8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 µA
IO = 8.0 mA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
µA
∆ICC
additional
per input pin;
supply current VI = VCC − 2.1 V; IO = 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
5 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
CL = 15 pF
-
4.0
8.8
1.0
10.5
1.0
11.0
ns
CL = 50 pF
-
5.6
12.3
1.0
14
1.0
15.5
ns
-
3.0
5.9
1.0
7.0
1.0
7.5
ns
4.2
7.9
1.0
9.0
1.0
10.0
ns
-
10.0
-
-
-
-
-
pF
-
3.2
6.9
1.0
8.0
1.0
9.0
ns
-
4.2
7.9
1.0
9.0
1.0
10.0
ns
-
12.0
-
-
-
-
-
pF
For type 74VHC08
tpd
propagation
delay
nA, nB to nY; see Figure 6
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD
power
CL = 50 pF; fi = 1 MHz;
dissipation
VI = GND to VCC
capacitance
[3]
For type 74VHCT08
tpd
propagation
delay
nA, nB to nY; see Figure 6
[2]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD
power
CL = 50 pF; fi = 1 MHz;
dissipation
VI = GND to VCC
capacitance
[3]
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
6 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
11. Waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
mna224
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
The input (nA, nB) to output (nY) propagation delays
Table 8.
Measurement points
Type
Input
Output
VM
VM
74VHC08
0.5VCC
0.5VCC
74VHCT08
1.5 V
0.5VCC
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
7 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
RT
CL
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7.
Load circuit for switching times
Table 9.
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74VHC08
VCC
≤ 3.0 ns
15 pF, 50 pF
1 kΩ
open
GND
VCC
74VHCT08
3.0 V
≤ 3.0 ns
15 pF, 50 pF
1 kΩ
open
GND
VCC
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
8 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT108-1 (SO14)
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
9 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Package outline SOT402-1 (TSSOP14)
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
10 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
mm
c
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
11 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
LSTTL
Low-power Schottky Transistor-Transistor Logic
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
CDM
Charged Device Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74VHC_VHCT08_1
20090630
Product data sheet
-
-
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
12 of 14
74VHC08; 74VHCT08
NXP Semiconductors
Quad 2-input AND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74VHC_VHCT08_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 30 June 2009
13 of 14
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 June 2009
Document identifier: 74VHC_VHCT08_1