SEMTECH SC4524B

SC4524B
16V 2A Step-Down Switching Regulator
POWER MANAGEMENT
Features











Description
Wide input range: 3V to 16V
2A Output Current
200kHz to 2MHz Programmable Frequency
Precision 1V Feedback Voltage
Peak Current-Mode Control
Cycle-by-Cycle Current Limiting
Hiccup Overload Protection with Frequency Foldback
Soft-Start and Enable
Thermal Shutdown
Thermally Enhanced 8-pin SOIC Package
Fully RoHS and WEEE compliant
Applications






XDSL and Cable Modems
Set Top Boxes
Point of Load Applications
CPE Equipment
DSP Power Supplies
LCD and Plasma TVs
The SC4524B is a constant frequency peak current-mode
step-down switching regulator capable of producing 2A
output current from an input ranging from 3V to 16V. The
switching frequency of the SC4524B is programmable
up to 2MHz, allowing the use of small inductors and
ceramic capacitors for miniaturization, and high input/
output conversion ratio. The SC4524B is suitable for
next generation XDSL modems, high-definition TVs and
various point of load applications.
Peak current-mode PWM control employed in the
SC4524B achieves fast transient response with simple loop
compensation. Cycle-by-cycle current limiting and hiccup
overload protection reduces power dissipation during
output overload. Soft-start function reduces input startup current and prevents the output from overshooting
during power-up.
The SC4524B is available in SOIC-8 EDP package.
SS270 REV 4
Typical Application Circuit
Efficiency
IN
10V – 16V
C4
2.2mF
SW
6.8mH
SC4524B
SS/EN
85
1N4148
C1
0.1mF
L1
BST
IN
90
R4
102k
5V/2A
FB
COMP
C7
10nF
C8
10pF
ROSC
R7
30.1k
GND
R5
18.2k
D2
20BQ030
80
OUT
R6
25.5k
C5
1nF
C2
22mF
Efficiency (%)
V
D1
VIN = 12V
75
70
65
60
55
50
45
40
L1: Wurth 744 778 9006
C2: Murata GRM31CR60J226K
C4: Murata GRM31CR61E225K
0
0.5
1
1.5
2
Load Current (A)
Figure 1. 1MHz 10V-16V to 5V/2A Step-down Converter
November 1, 2007
SC4524B
Pin Configuration
Ordering Information
SW
1
8
BST
IN
2
7
FB
ROSC
3
6
COMP
GND
4
5
SS/EN
9
Device
Package
SC4524BSETRT(1)(2)
SOIC-8 EDP
SC4524BEVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 2,500 devices.
(2) Available in lead-free package only. Device is fully WEEE and RoHS
compliant.
(8 - Pin SOIC - EDP)
Marking Information
yyww=Date code (Example: 0752)
xxxxx=Semtech Lot No. (Example: E9010)
SC4524B
Absolute Maximum Ratings
Thermal Information
VIN Supply Voltage ……………………………… -0.3 to 24V
Junction to Ambient (1) ……………………………… 36°C/W
BST Voltage ……………………………………………… 40V
Junction to Case (1) …………………………………
BST Voltage above SW …………………………………… 24V
Maximum Junction Temperature……………………… 150°C
Storage Temperature ………………………… -65 to +150°C
SS Voltage ……………………………………………-0.3 to 3V
FB Voltage …………………………………………… -0.3 to VIN
SW Voltage ………………………………………… -0.6 to VIN
Lead Temperature (Soldering) 10 sec ………………… 300°C
Recommended Operating Conditions
SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V
Peak IR Reflow Temperature ………………………….
5.5°C/W
Input Voltage Range ……………………………… 3V to 16V
260°C
ESD Protection Level(2) ………………………………… 2000V
Maximum Output Current ……………………………… 2A
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not recommended.
NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Max
Units
16
V
2.95
V
Input Supply
Input Voltage Range
VIN Start Voltage
3
VIN Rising
2.70
VIN Start Hysteresis
VIN Quiescent Current
VIN Quiescent Current in Shutdown
2.82
225
mV
VCOMP = 0 (Not Switching)
2
2.6
mA
VSS/EN = 0, VIN = 12V
40
50
µA
1.000
1.020
V
Error Amplifier
Feedback Voltage
Feedback Voltage Line Regulation
FB Pin Input Bias Current
0.980
VIN = 3V to 16V
0.005
VFB = 1V, VCOMP = 0.8V
-170
%/V
-340
nA
Error Amplifier Transconductance
280
µΩ-1
Error Amplifier Open-loop Gain
60
dB
COMP Pin to Switch Current Gain
8
A/V
VFB = 0.9V
2.4
V
COMP Source Current
VFB = 0.8V, VCOMP = 0.8V
17
COMP Sink Current
VFB = 1.2V, VCOMP = 0.8V
25
COMP Maximum Voltage
µA
Internal Power Switch
Switch Current Limit
Switch Saturation Voltage
(Note 1)
ISW = -2.6A
2.6
3.3
4.3
A
250
400
mV
SC4524B
Electrical Characteristics (Cont.)
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Minimum Switch On-time
135
Minimum Switch Off-time
100
Switch Leakage Current
Max
Units
ns
150
ns
10
µA
Minimum Bootstrap Voltage
ISW = -2.6A
1.8
2.3
V
BST Pin Current
ISW = -2.6A
60
95
mA
Oscillator
Switching Frequency
Foldback Frequency
ROSC = 12.1kΩ
1.04
1.3
1.56
MHz
ROSC = 93.1kΩ
240
300
360
kHz
ROSC = 12.1kΩ, VFB = 0
110
230
350
ROSC = 93.1kΩ, VFB = 0
50
100
170
0.2
0.3
0.4
V
1.0
1.13
1.3
V
kHz
Soft Start and Overload Protection
SS/EN Shutdown Threshold
SS/EN Switching Threshold
Soft-start Charging Current
VFB = 0 V
VSS/EN = 0 V
VSS/EN = 1.5 V
1.7
1.2
Soft-start Discharging Current
2.0
2.8
µA
1.5
µA
Hiccup Arming SS/EN Voltage
VSS/EN Rising
2.15
V
Hiccup SS/EN Overload Threshold
VSS/EN Falling
1.9
V
Hiccup Retry SS/EN Voltage
VSS/EN Falling
0.6
1.0
1.2
V
Over Temperature Protection
Thermal Shutdown Temperature
165
°C
Thermal Shutdown Hysteresis
10
°C
Note 1: Switch current limit does not vary with duty cycle.
SC4524B
Pin Descriptions
SO-8
Pin Name
Pin Function
1
SW
Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the
bootstrap capacitor.
2
IN
Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane.
3
ROSC
An external resistor from this pin to ground sets the oscillator frequency.
4
GND
Ground pin
5
SS/EN
Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup
functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off
the regulator to low current state.
6
COMP
The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator.
7
FB
The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to
improve short-circuit robustness (see Applications Information for details).
8
BST
Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive
voltage higher than VIN in order to fully enhance the internal NPN power transistor.
9
Exposed Pad
The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the
PC board.
SC4524B
Block Diagram
IN
SLOPE
COMP
COMP
6
+
2
S
+
+
ISEN
6.1mW
FB
+ EA
+
7
+
ILIM
-
OC
20mV
BST
V1
8
+
PWM
-
S
R
FREQUENCY
FOLDBACK
ROSC
Q
POWER
TRANSISTOR
CLK
OSCILLATOR
3
1
R
R
SW
OVERLOAD
-
PWM
A1
1.23V
+
1
SS/EN
5
1V
1.9V
REFERENCE
& THERMAL
SHUTDOWN
FAULT
SOFT-START
AND
OVERLOAD
HICCUP
CONTROL
GND
4
Figure 2. SC4524B Block Diagram
1.9V
SS/EN
IC
2mA
B4
+
Q
B1
OVERLOAD
R
1V/2.15V
FAULT
S
ID
3.5mA
B2
_
Q
S
OC
R
PWM
B3
Figure 3. Soft-start and Overload Hiccup Control Circuit
(2)
(3)
Typical Characteristics
SC4524A/B
SC4524A/B
SS270 REV 6-7
60
55
V O=1.5V
70
65
VO=1.0V
60
55
1MHz, VIN =12V
D 2 =20BQ030
(5)
45
50
1.01
VFB (V)
V O=1.5V
65
75
Efficiency (%)
70
V IN =12V
V O=2.5V
80
V O=2.5V
75
V O=3.3V
85
V O=3.3V
80
1.02
90
V O=5V
85
Feedback Voltage vs Temperature
Efficiency
Efficiency
90
Efficiency (%)
SC4524B
(6)
45
1MHz, VIN=5V
D2 =20BQ030
50
0
0.5
1
1.5
0.97
0
2
0.5
1
1.5
2
-50
-25
Load Current (A)
Load Current (A)
SS270 REV 6-7
0.99
0.98
40
40
1.00
0
25
50
75
100 125
o
Temperature ( C)
SS270 REV 6-7
Frequency Setting Resistor
vs Frequency
1.25
V IN =12V
Normalized Frequency
R OSC=93.1k
ROSC (k)
100
10
(8)
1
0
0.5
1
1.5
2
1.1
1.0
R OSC=12.1k
0.9
(9)
2.5
ROSC=93.1k
0.75
0.5
TA =25oC
0.25
R OSC=12.1k
-50
-25
0
25
50
75
0.0
100 125
0.2
0.4
Temperature (o C)
SS270 REV 6-7
SS270 REV 6-7
1
0
0.8
Frequency (MHz)
Switch Saturation Voltage
vs Switch Current
300
Foldback Frequency vs VFB
Frequency vs Temperature
1.2
Normalized Frequency
1000
0.6
0.8
1.0
VFB (V)
SS270 REV 6-7
Switch Current Limit vs Temperature
BST Pin Current vs Switch Current
100.0
4.5
V IN =12V
-40oC
125oC
150
25oC
100
4.0
BST Pin Current (mA)
200
Current Limit (A)
V CESAT (mV)
250
3.5
3.0
2.5
50
0.0
0.5
1.0
1.5
Switch Current (A)
2.0
2.5
V BST =15V
75.0
50.0
-40oC
125oC
25.0
0.0
-50
-25
0
25
50
75
o
Temperature ( C)
100 125
0
0.5
1
1.5
2
2.5
3
Switch Current (A)
SC4524B
(12)
(11)
Typical Characteristics (Cont.)
SS270 REV 6-7
SS270 REV 6-7
SS270 REV 6-7
VIN Supply Current
vs Soft-Start Voltage
VIN Thresholds vs Temperature
2.5
Start
2.8
2.7
2.6
(14)
2.5
V SS = 0
125oC
2.0
Current (mA)
VIN Threshold (V)
2.9
40
-40oC
1.5
1.0
UVLO
(15)
-25
0
25
50
75
0
100 125
0.5
Temperature (o C)
1
1.5
0
2
2
4
6
VIN Quiescent Current vs VIN
10
12
14
16
SS270 REV 6-7
Soft-Start Charging Current
vs Soft-Start Voltage
SS Shutdown Threshold
vs Temperature
0.40
2.5
8
VIN (V)
V SS (V)
SS270 REV 6-7
SS270 REV 6-7
125oC
20
0
0.0
-50
-40oC
30
10
0.5
2.4
VIN Shutdown Current vs VIN
50
Current (uA)
3.0
0.0
125oC
-0.5
1.5
1.0
0.5
0.35
Current (uA)
-40oC
SS Threshold (V)
Current (mA)
2.0
0.30
6
8
V IN (V)
10
12
14
-2.0
-3.0
0.20
4
-40oC
-1.5
-2.5
0.0
2
125oC
0.25
VCOMP = 0
0
-1.0
16
-50
-25
0
25
50
75
o
Temperature ( C)
100 125
0
0.5
1
1.5
2
V SS (V)
SC4524B
Applications Information
Operation
The SC4524B is a constant-frequency, peak current-mode,
step-down switching regulator with an integrated 16V,
2.6A power NPN transistor. Programmable switching
frequency makes the regulator design more flexible. With
the peak current-mode control, the double reactive poles
of the output LC filter are reduced to a single real pole by
the inner current loop. This simplifies loop compensation
and achieves fast transient response with a simple Type-2
compensation network.
As shown in Figure 2, the switch collector current is
sensed with an integrated 6.1mW sense resistor. The
sensed current is summed with a slope-compensating
ramp before it is compared with the transconductance
error amplifier (EA) output. The PWM comparator trip
point determines the switch turn-on pulse width. The
current-limit comparator ILIM turns off the power switch
when the sensed signal exceeds the 20mV current-limit
threshold.
Driving the base of the power transistor above the
input power supply rail minimizes the power transistor
saturation voltage and maximizes efficiency. An external
bootstrap circuit (formed by the capacitor C1 and the
diode D1 in Figure 1) generates such a voltage at the BST
pin for driving the power transistor.
Shutdown and Soft-Start
Table 1: SS/EN operation modes
Mode
<0.2V
SS/EN
0.4V to 1.23V
<0.2V
1.23V to 2.1V
0.4V to 1.23V
>2.1V
Supply Current
Shutdown
18uA @ 5Vin
Mode
Supply Current
Not switching
2mA
Shutdown& hiccup disabled
18uA @ 5Vin
Switching
Load dependent
Not
switching
2mA
Switching
& hiccup armed
1.23V to 2.1V
Switching & hiccup disabled
>2.1V
Switching & hiccup armed
The error amplifier EA in Figure 2 has two non-inverting
inputs. The non-inverting input with the lower voltage
predominates. One of the non-inverting inputs is biased
to a precision 1V reference and the other non-inverting
input is tied to the output of the amplifier A1. Amplifier A1
produces an output V1 = 2(VSS/EN -1.23V). V1 is zero and COMP
is forced low when VSS/EN is below 1.23V. During start up,
the effective non-inverting input of EA stays at zero until
the soft-start capacitor is charged above 1.23V. Once VSS/EN
exceeds 1.23V, COMP is released. The regulator starts to
switch when VCOMP rises above 0.4V. If the soft-start interval
is made sufficiently long, then the FB voltage (hence the
output voltage) will track V1 during start up. VSS/EN must be
at least 1.83V for the output to achieve regulation. Proper
soft-start prevents output overshoot. Current drawn from
the input supply is also well controlled.
Overload / Short-Circuit Protection
Table 2 lists various fault conditions and their
corresponding protection schemes in the SC4524B.
Condition
The SS/EN pin is a multiple-function pin. An external
capacitor (4.7nF to 22nF) connected from the SS pin to
ground sets the soft-start and overload shutoff times of
the regulator (Figure 3). The effect of VSS/EN on the SC4524B
is summarized in Table 1.
SS/EN
When the SS/EN pin is released, the soft-start capacitor
is charged with an internal 1.6µA current source (not
shown in Figure 3). As the SS/EN voltage exceeds 0.4V,
the internal bias circuit of the SC4524B turns on and the
SC4524B draws 2mA from VIN. The 1.6µA charging current
turns off and the 2µA current source IC in Figure 3 slowly
charges the soft-start capacitor.
Load dependent
Pulling the SS/EN pin below 0.2V shuts off the regulator
and reduces the input supply current to 18µA (VIN = 5V).
Fault
Protective Action
Table 2: Fault conditions and protections
Cycle-by-cycle limit at
IL>ILimit, VFB>0.8V
Condition
Over current
Fault
IL>ILimit,IL>ILimit,
VFB>0.8V
Over current
VFB<0.8V
Over current
Protective
Action frequency
programmed
Cycle-by-cycle
limit at limit with
Cycle-by-cycle
programmed
frequency
frequency
foldback
Cycle-by-cycle
limit with
VSS/EN Falling
Persistent over current
Shutdown,
then retry
IL>ILimit, VFB<0.8V
Over current
SS/EN<1.9V
or short circuit frequency foldback
(Hiccup)
VSS/EN Falling
Persistent over current
Shutdown, then retry
Tj>160C
Over temperature
Shutdown
SS/EN<1.9V
or short circuit
(Hiccup)
Tj>160C
Over temperature
Shutdown
As summarized in Table 1, overload shutdown is disabled
during soft-start (VSS/EN<2.1V). In Figure 3, the reset input of
the overload latch B2 will remain high if the SS/EN voltage
is below 2.1V. Once the soft-start capacitor is charged
above 2.1V, the output of the Schmitt trigger B1 goes high,
the reset input of B2 goes low and hiccup becomes armed.
SC4524B
AC =
Applications Information (Cont.)
As the load draws more current from the regulator, the
current-limit comparator ILIM (Figure 2) will eventually
limit the switch current on a cycle-by-cycle basis. The
over-current signal OC goes high, setting the latch B3. The
soft-start capacitor is discharged with (ID - IC) (Figure 3). If
the inductor current falls below the current limit and the
PWM comparator instead turns off the switch, then latch
B3 will be reset and IC will recharge the soft-start capacitor.
If over-current condition persists or OC becomes asserted
more often than PWM over a period of time, then the
soft-start capacitor will be discharged below 1.9V. At this
juncture, comparator B4 sets the overload latch B2. The
soft-start capacitor will be continuously discharged with
(ID - IC). The COMP pin is immediately pulled to ground. The
switching regulator is shut off until the soft-start capacitor
is discharged below 1.0V. At this moment, the overload
latch is reset. The soft-start capacitor is recharged and
the converter again undergoes soft-start. The regulator
will go through soft-start, overload shutdown and restart
until it is no longer overloaded.
Fig.4
If the FB voltage falls below 0.8V because of output
overload, then the switching frequency will be reduced.
Frequency foldback helps to limit the inductor current
when the output is hard shorted to ground.
 V

R4 = R6  O − 1 
down switching
in continuous-conduction
 1.0 Vregulator

mode (CCM) is given by
VO + VD
D=
VIN + VD − VCESAT
Closed-loop measurement shows that the SC4524B
 is about 135ns
1
minimum
at room temperature
DVO on
= Dtime
IL ⋅  ESR
+

8switch
⋅ FSW ⋅ Con
(Figure 4). If the required
O time is shorter than

the minimum on time, the regulator will either skip cycles
or it will jitter.
(1)
VO + VD Frequency
SettingDthe
= Switching
VIN + VD − VCESAT
The switching frequency of the SC4524B is set with an
external resistor from the ROSC pin to ground.
( VO + VD ) ⋅ (1 − D)
DIL =On Time
Minimum
FSWConsideration
⋅ L1
The operating duty cycle of a non-synchronous step( V + VD ) ⋅ (1 − D)
L1 = O
20% ⋅ IO ⋅ FSW
R7 =
C5 =
C8 =
Vo
=
Vc
GPWM
R7 =
SS270 REV 6-7
C IN >
IO
Minimum
4⋅D
VIN ⋅ FSWOn Time vs Temperature
C5 =
200
190
V O =1.5V
1MHz
180
C8 =
TON(MIN) (ns)
170
Setting the Output Voltage
V
R4 = R6  O − 1 
 1.0 V

(2)
where VCESAT is the switch saturation voltage and VD is
voltage drop across the rectifying diode.
( V + VD ) ⋅ (1 − D)
DIL = O
FSW ⋅ L 1 control, the PWM modulating
In peak current-mode
ramp is the sensed current ramp of the power switch.
This current( Vramp
+ VD is
) ⋅ (absent
1 − D) unless the switch is turned
L = O
on. The1intersection
of
this ramp with the output of the
20% ⋅ IO ⋅ FSW
voltage feedback error amplifier determines the switch
pulse width. The propagation delay time required to
immediately
the
IRMS _ CINturn
= IO off
⋅ D
⋅ (1switch
− D) after it is turned on is the
minimum controllable switch on time (TON(MIN)).
During normal operation, the soft-start capacitor is
charged to 2.4V.
The regulator output voltage is set with an external
resistive divider (Figure 1) with its center tap tied to the
FB pin. For a given R6 value, R4 can be found by
AC =
160
150
140
130
120
 1
V 
1

A C = − 20 ⋅ log
⋅
⋅ FB 
110
 G CA R S 2πFC C O VO 
100
-50
-25
0
25
50
75
100 125
1 Temperature (OC)
1
1.0 
A C = − 20 ⋅ log
⋅
⋅
 = 15
−3
3
−6
3 .3 
2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10
 28 ⋅ 6.1 ⋅ 10
Figure 4. Variation of Minimum On Time
with Ambient Temperature
15.9
10 20
R7 =
= 22.3k
−3
0.28for
⋅ 10
To allow
transient headroom, the minimum operating
switch on time should
be at least 20% to 30% higher than
1
C5 =
= 0.45nF
3
the worst-case
minimum
on3time.
2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10
C8 =
1
= 12pF
2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3
10
L1 =
O
D
20% ⋅ IO ⋅ FSW
SC4524B
IRMS _ CIN = IO ⋅ D ⋅ (1 − D)
Applications Information (Cont.)
Minimum Off Time Limitation
The PWM latch in Figure 2 is reset every cycle by the
clock. The clock also turns off the power transistor to
refresh the bootstrap capacitor. This minimum off time
limits the attainable duty cycle of the regulator at a given
switching frequency. The measured minimum off time is
100ns typically. If the required duty cycle is higher than
the attainable maximum, then the output voltage will not
 VOits set value in continuous-conduction
be able
R4 to
= Rreach
−1
6
 1.0 V

mode.
Inductor Selection
VO + VD
D=
VIN + VD − VCESAT
The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is
(V V
+ V ) ⋅ (1 − D)
RD4IL==R6 O O D − 1 
FSW
V ⋅ L 1
 1.0
(3)
where FSW is the switching frequency and L1 is the
( V V+ V+ )V⋅ (1 − D)
inductance.
LD1== O O D D
FSW
VIN 20
+ V%D ⋅−IOV⋅CESAT
An inductor ripple current between 20% to 50% of the
maximum load current gives a good compromise among
IRMS _ cost
⋅ )D
⋅ (1 Re-arranging
− D)
CIN
OV
efficiency,
and
size.
Equation (3) and
( VO= I+
D ⋅ (1 − D)
D
I
=
L 35% inductor ripple current, the inductor is
assuming
FSW ⋅ L 1
given by

( V + V D ) ⋅ (1 − D) 1

LD1VO= = DOIL ⋅  ESR
+
(4)
35V% ⋅ IO ⋅ FSW8 ⋅ FSW ⋅ C O 


O
R4 = R6 
−1
If the input voltage
 1.0 V varies
 over a wide range, then choose
L1 based on the nominal input voltage. Always verify
IRMS _ CIN = IO ⋅ D ⋅ (1 − D)
converter
operation
VO I+ VDat the input voltage extremes.
O
D =>
C
IN V + V − V
IN
4 ⋅ DVDIN ⋅ FCESAT
The peak current limitSWof SC4524B power transistor is at
least 2.6A. The maximum
deliverable

 load current for the
1

D
V
=
D
I
⋅
ESR
+
O
L
SC4524B is 2.6A minus one
half
of the inductor ripple
8
⋅
F
⋅
C
SW
O 

( V + VD ) ⋅ (1 − D)
current.
DIL = O
FSW ⋅ L 1
Input Decoupling Capacitor
( V + V ) ⋅ (1 − D)
LC1 => O IOD
IN capacitor
The input
420
⋅ D%
VIN⋅ IO⋅should
F⋅ FSWSW be chosen to handle the RMS
ripple current of a buck converter. This value is given by
IRMS _ CIN = IO ⋅ D ⋅ (1 − D)

DV = DI ⋅  ESR +
1


(5)


1

DVOcapacitance
= DIL ⋅  ESRmust
+
The input
also be high
enough to keep
8 ⋅ FSW ⋅ C O 

input ripple voltage within specification. This is important
in reducing the conductive EMI from the regulator. The
input capacitance can be estimated from
Vo
=
Vc
GPWM
R7 =
AC =
V IO
(6)
C5 =
RC4IN=>R6  O − 1 
4⋅1D.V
0INV ⋅ FSW
AC =


1inputVripple
DV is the 1
allowable
Awhere
⋅
⋅ FB  voltage.
C = − 20 ⋅INlog 
C8 =
GOCA+RVSD 2πFC C O VO 
V
D=
Multi-layerVceramic
capacitors, which have very low ESR
IN + VD − VCESAT
1 handle high RMS1 ripple current,
1.0 
(a few mW) and can easily
A C = − 20 ⋅ log
⋅
⋅
=
R=715
−3
3
−6
are the ideal choice
3.3 
28 ⋅ 6.1for
⋅ 10input2πfiltering.
⋅ 80 ⋅ 10 A ⋅ single
22 ⋅ 10 4.7µF
X5R ceramic( Vcapacitor
is adequate for 500kHz or higher
O + VD ) ⋅ (1 − D)
DIL =frequency
switching
applications, and 10µF is adequate C 5 =
15.9
FSW ⋅ L 1
for 200kHz
500kHz
switching
For high
10 20 to
 =

V frequency.
122.3k 1
R7 =
Avoltage
−.28
20applications,
⋅⋅ 10
log−3
⋅ FB (1µF or 2.2µF) can be
a⋅ small ceramic
C =0
C8 =
R 2πDF)C C O VO 
( VO G
+CA
Vwith
D )S⋅ (1a−low
placedLin
parallel
ESR
electrolytic
capacitor
to
=
1
1
203ESR
% ⋅ IOand
⋅ FSWbulk
Csatisfy
= 0.45nF
5 =
both the
3 capacitance requirements.
2π ⋅ 16 ⋅ 10
⋅
22
.
1
⋅
10
1
1
1.0 
A C = − 20 ⋅ log
⋅
⋅
 = 15
−3
3
−6
3.3  Vo
28
⋅
6
.
1
⋅
10
2
π
⋅
80
⋅
10
⋅
22
⋅
10
 1
Output
Capacitor
=
C8 = I
= IO3 ⋅⋅ 22
D.⋅1(1⋅ 10
− D3) = 12pF
Vc
_ CIN⋅ 10
2 πRMS
⋅ 600
The output15.9ripple voltage DVO of a buck converter can be
10 20as
Rexpressed
= 22.3k
7 =
− 3 (1 + sR
GPWM
Vo 0.28 ⋅ 10
ESR C O )
GPWM
=

21
2 


D
V
=
D
I
⋅
ESR
+
V
(
1
+
s
/
ω
)
(
1
+
s
/
ω
Q
+
s
/
ω
)
(7)
O
c
p L1 
n
n 
8 ⋅3FSW
C5 =
= 0⋅.C
45
O nF

3 
2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10
where CO is the output capacitance.
R7 =
R
1V 
1
1
G
≈ 20 ⋅ log, 31 ⋅ ωp1≈ 3 =⋅ 12
,FBpF
ωZ =
,
C
=−

8
APWM
=
C
⋅R
RC O V DI increases
R ESRasC OD
⋅CA
600
⋅ 22.2
1π⋅ F10Ccurrent
S⋅10
Since2 πG
the
inductor
C O
O  L
 G CAIOR S ripple
C IN >(Equation (3)), the output ripple voltage is C 5 =
decreases
AC
4 ⋅ DVIN ⋅ FSW
therefore
10 20 the highest
1when VIN is at its maximum.
1
1.0 
RAV7oC = − 20 ⋅ log
GPWM
⋅
 (1 + sRESR C−O3) ⋅
 = 15
3
−6
= gm
3 .3
28 ⋅ 6.1 ⋅ 10 2 2π ⋅280 ⋅ 10 ⋅ 22 ⋅ 10
VAc 10µF
(1 +to
s /47µF
ωp)(1X5R
+ s ceramic
/ ωn Q + scapacitor
/ ωn ) is found adequate C 8 =
1
output filtering in most applications. Ripple current
Cfor
5 =
15
2 πFoutput
R.97 capacitor is not a concern because the
Z1 20
in the
10
R
1
1
Rinductor
= of
22a.3kbuck
G
ωp ≈ converter
,
ωZ =feeds C ,,
7 = ≈
−,3
current
directly
PWM
1
0
.
28
⋅
10
GCA ⋅ RS
RC O
R ESRC OO
Cresulting
8 =
in
very
low
ripple
current.
Avoid
using
Z5U
2 πFP1 R7 1
Cand
=
=
0
.
45
nF
Y5V
ceramic
capacitors
for
output
filtering
because
A
C
5
3
3
20
2π
⋅ 16 ⋅of
10capacitors
⋅ 22.1 ⋅ 10
10
types
have high temperature and high
Rthese
=
7
g m coefficients.
voltage
1
C8 =
= 12pF
2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3
1
Diode
CFreewheeling
5 =
2 πFZ1 R7
G (1 + sR diodes
C O ) as freewheeling rectifiers
VUse
of Schottky
o
1 PWM barrierESR
==
CVreduces
recovery
current spikes,
8
(21π+Fsdiode
/ ωp )(1reverse
+ s / ωn Q
+ s 2 / ωn2input
)
c
P1 R 7
easing high-side current sensing in the SC4524B. These
GPWM ≈
R
,
GCA ⋅ RS
ωp ≈
1
,
RC O
ωZ =
1 11
,
R ESRC O
SC4524B
Fig.5
Applications Information (Cont.)
SS270 REV 6-7
The freewheeling diode should be placed close to the
SW pin of the SC4524B to minimize ringing due to trace
inductance. 10BQ015, 20BQ030 (International Rectifier),
B220A (Diodes Inc.), SS13, SS22 (Vishay), CMSH1-20M,
CMSH1-20ML and CMSH2-20M (Central-Semi.) are all
suitable.
Minimum Bootstrap Voltage
vs Temperature
2.2
2.1
Voltage (V)
diodes should have an average forward current rating
at least 2A and a reverse blocking voltage of at least a
few volts higher than the input voltage. For switching
regulators operating at low duty cycles (i.e. low output
voltage to input voltage conversion ratios), it is beneficial
to use freewheeling diodes with somewhat higher
average current ratings (thus lower forward voltages). This
is because the diode conduction interval is much longer
than that of the transistor. Converter efficiency will be
improved if the voltage drop across the diode is lower.
2.0
1.9
1.8
ISW = -2.6A
1.7
1.6
-50
-25
25
100 125
Figure 5. Typical Minimum Bootstrap Voltage required
to Saturate Transistor (ISW= -2.6A).
D1
BST
C1
VOUT
SW
IN
SC4524B
The minimum BST-SW voltage required to fully saturate
the power transistor is shown in Figure 5, which is about
1.96V at room temperature.
VIN
D
2
GND
(a)
D1
D1
BST
VIN
C1
VOUT
SW
IN
SC4524B
D
2
GND
(a)
For the bootstrap circuit, a fast switching PN diode (such
as 1N4148 or 1N914) and a small (0.1µF – 0.47µF) ceramic
capacitor is sufficient for most applications. When
bootstrapping from 2.5V to 3.0V output voltages, use a
low forward drop Schottky diode (BAT-54 or similar) for
D1.
75
Temperature ( C)
VIN
The BST-SW voltage is supplied by a bootstrap circuit
powered from either the input or the output of the
BST
converter (Figure 6). To maximize efficiency,C1 tie the
bootstrap diode toVINthe converter output
if VO>2.5V. VOUT
SW
IN
Since the bootstrap supply current is proportional to the
SC4524B
D to power
converter load current, using a lower
voltage
2
GND
the bootstrap circuit reduces driving loss and improves
efficiency.
50
o
The freewheeling diode should be placed close to the SW
pin of the SC4524B on the PCB to minimize ringing due to
trace inductance.
Bootstrapping the Power Transistor
0
(b)
Figure 6. Methods of Bootstrapping the SC4524B
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.
12
Applications Information (Cont.)
CONTROLLER AND SCHOTTKY DIODE
CA
REF
Including the voltage divider (R4 and R6), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Io
+
EA
FB
Rs
-
Vc
PWM
MODULATOR
SW
Vramp
L1
Vo
COMP
Co
C5
C8
R7
Resr
R4
R6
Figure 7. Block diagram of control loops
VFB 
1
1
 1
1
FB 
AC =
=diagram
− 20
20 ⋅⋅ log
log
⋅shows
⋅V
The block
in
Figure
7
the
control

 loops of a
A
−
⋅
⋅
C
 G
G CA R
RS 2
2π
πFFC C
CO V
VO 
CA
S
C
O
O

buck converter with the SC4524B. The innerloop (current
loop) consists of a current sensing resistor (Rs=6.1mW)
1 gain (G =28). The
1 outer
1
1
amplifier
AC =
=−
− 20
20
log (CA) with
⋅ CA
VFB  and a current
A
⋅⋅ log
⋅
−
3
−6
C
28 ⋅⋅ 6
6..1
1of⋅⋅ 10
10
2π
π amplifier
80 ⋅⋅ 10
10 33 (EA),
22 ⋅⋅ 10
 loop (voltage loop) consists
⋅
2
⋅⋅ 80
⋅⋅ 22
 28
an− 3error
a10 −6
VO 
PWM modulator, and a LC filter.
15.9
15
20.9
20
1
1.0 internally closed, the remaining
10 loop
10
⋅  1Since3 the
⋅  −3is=
15
R71=
=current
22.9
3dB
k
V
R
−
6
FB
7 ⋅ 10
3.3−3 = 22.3k is to design the voltage
2π⋅ 80task
⋅ 10⋅for
⋅ 22
0loop
28
10
⋅ log
⋅ ⋅⋅ 10
the0
compensation
..28
R S 2πFC C O VO 
 G CAcompensator
1 C8).
(C5, R7, and
1
C5 =
=
=0
0..45
45nF
nF
C
=
3
5
2π
π ⋅⋅ 16
16 ⋅⋅ 10
10 3 ⋅⋅ 22
22..1
1 ⋅⋅ 10
10 33
2
1
1
1.0  F , output
with switching
frequency
⋅ log For a converter
⋅
⋅
 = 15
SW.9dB
−3
3
−6
1
.12
3 pF
⋅ 6.1 ⋅ 10
2, πoutput
⋅ 80 ⋅ 10
1 ⋅ 22 ⋅ 10 C =3
 28inductance
L
capacitance
and
loading
R, the
C
=
C 88 = 1
3
3O = 12pF
3
3
2
π
⋅
600
⋅
10
⋅
22
.
1
⋅
10
2
π
⋅
600
⋅
10
⋅
22
.
1
⋅
10
control (VC) to output (VO) transfer function in Figure 7 is
= 0.45nF
given by:
15.9
0 20
= 22.3kV
GPWM ((1
1+
+ ssR
RESR C
C O ))
−3
G
Voo =
⋅ 10
PWM
ESR O
(8)
=
12
pF
=
3
Vc ((1
1+
+ ss // ω
ωp ))((1
1+
+ ss // ω
ωn Q
Q+
+ ss22 // ω
ωn22 ))
V
1
c
p
n
n
= 0.45nF
16 ⋅ 10 3 ⋅This
22.1transfer
⋅ 10 3 function has a finite DC gain
R
1
GPWM ≈
≈= 12RpF ,,
G
PWM
2
2 3
GCA ⋅⋅ R
RS
/ω
600
⋅ 10
⋅ 22.1 ⋅ 10 3 G
CA
S
n)
1
ωp ≈
≈ 1 ,,
ω
p
RC
CO
R
O
AC
an ESR zero FZ at
AC
20
10 20
10
R7C=
=) 1
1GPWM (1 + sRESR
R
,
ω7Z =O g m
,
R/CωOp )(1 + s / ωn Q + sR2gESR
/mωCn2O)
1
1
C5 =
= low-frequency
C
a dominant
pole FP at
5
2π
πFFZ1 R
R7
2
Z1 7
R
1
1
,
ωp ≈
ωZ =
,
1,
1
C
=
⋅
R
R
C
R
C 88 = 2 πOF R
A
S
ESRC O
2 πFPP11 R77
and double poles at half the switching frequency.
V
R4 = R6  O − 1 
 1.0 V

Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at FZ1, and a high frequency pole
at FP1. The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
1..0
060
1
= 15
15..9
9dB
dB
⋅⋅ 3.3  =
3.3 
30
GAIN (dB)
O
SC4524B
Fz1
Fp
0
Fp1
Fc
CO
NV
ER
TER
GA
IN
CO
MP
EN
SA
TO
RG
AIN
LO
OP
GA
IN
-30
-60
1K
10K
Fz
Fsw/2
100K
FREQUENCY (Hz)
1M
10M
Figure 8. Bode plots for voltage loop design
Therefore, the procedure of the voltage loop design for
1 the SC4524B can be summarized as:
ωZ =
= 1 ,,
ω
Z
R ESRC
CO
R
ESR (1)
O Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, FC, between
10% and 20% of the switching frequency. At FC, find the
required compensator gain, AC. In typical applications with
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at FC can be estimated by
 1
V
1
A C = − 20 ⋅ log
⋅
⋅ FB
 G CA R S 2πFC C O VO



(9)
1
1
1.0
13
A C = − 20 ⋅ log
⋅
⋅
−3
3
−6
3.
2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10
 28 ⋅ 6.1 ⋅ 10
C5 =
C8 =
1
3
2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10 3
= 0.45nF
SC4524B
1
= 12pF
2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3
Applications Information (Cont.)
GPWM (1 + sRESR C O )
Vo
capacitor, the main power switch and the freewheeling
(3) Place =the compensator zero, FZ1,2between
10% and
Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn2 )
diode carry pulse current (Figure 9). For jitter-free
20% of the crossover frequency, FC.
operation, the size of the loop formed by these components
(4) Use the compensator pole, FP1, to cancel the ESR zero,
FZ.
R
1
1 should be minimized. Since the power switch is already
GPWM ≈
,
ωp ≈
,
ωZ =
,
(5) Then, the parameters
of the compensation
networkR Cintegrated within the SC4524B, connecting the anode of
GCA ⋅ RS
RC O
ESR O
the freewheeling diode close to the negative terminal of
can be calculated by
AC
the input bypass capacitor minimizes size of the switched
10 20
current loop. The input bypass capacitor should be placed
R7 =
gm
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
1
C5 =
nodes. This not only reduces EMI but also decreases
2 πFZ1 R7
switching voltage spikes at these nodes.
1
C8 =
2 πFP1 R7
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
where gm=0.28mA/V is the EA gain of the SC4524B.
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
V IN
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator
 1 zero 1and pole
VFB at FZ1=16kHz


A
=
−
20
⋅
log
⋅
⋅
C
(20% of FC), and
F 1=600kHz.
(9), the
V  From Equation
1
G CA R
A C = − 20 ⋅ log
⋅ P1
⋅ SFB 2πFC C O VO 

C O Vat
required compensator
O F is
 G CA R S 2πFCgain
C
VOUT
1 1
1 
1.0  1
A C = −A
20
⋅ log 20 ⋅ log − 3 ⋅
⋅
 = 315.9dB
3− 3 ⋅
−6
C = −
2
π
⋅
80
⋅
10
⋅
22
⋅
10
 28 ⋅ 6.1 ⋅ 10

2π ⋅ 803.⋅310
⋅ 22 ⋅ 10 −6
 28 ⋅ 6.1 ⋅ 10
⋅
1.0 
 = 15.9dB
3 .3 
ZL
Then the compensator parameters are
15.9
10 20
= 2215.3.9k
0.28 ⋅ 10 −3 10 20
R7 = 1
= 22.3k
0.28
⋅ 10 −3 3 = 0.45nF
C5 =
3
2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10
R7 =
C8 =
1
1
= 0.45nF
33 = 12pF
3
3
2
π
⋅
16
⋅
10
2 π⋅ 600 ⋅ 10 ⋅ 22.1 ⋅ 10 ⋅ 22.1 ⋅ 10
C5 =
1
C 8 =G (1 + sR C )3
Vo
PWM
O
2 π⋅ 600ESR⋅ 10
⋅ 22.1 ⋅ 10 3
=
Vc (1 + s / ωp )(1 + s / ωn Q + s 2 / ωn2 )
Figure 9. Heavy lines indicate the critical pulse
current loop. The inductance of this
loop should be minimized.
= 12pF
Select R7=22.1k, C5=0.47nF, and C8=10pF for the design.
1
1
GPWM
ωp ≈(1 + ,sRESR C Oω)Z =
,
R
C
R
parameters for various typical
ESR
2C O applications
Vc (1 + s / ωp )(1 + Os / ωn Q + s 2 / ω
)
n
are listed in Table 4. A MathCAD program is
also available
10
upon
R7 = request for detailed calculation of the compensator
gm
parameters.
R
1
1
GPWM
,
ωp ≈
,
ωZ =
,
1 ≈
C5 =
RC O
R ESRC O
2 πFZ1 R7 GCA ⋅ RS
PCB Layout Considerations
R
GPWM ≈ Vo
= ,
G
Compensator
CA ⋅ RS
AC
20
C8 =
Cu
Vin
1
AC
2 πFP1 R710 20
In a step-down
switching regulator, the input bypass
R7 =
gm
1
C5 =
2 πF R
+
14
SC4524B
Recommended Component Parameters in Typical Applications
Table 4 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output
voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator
parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency
of FSW/10.
Table 4. Recommended inductance (L1) and compensator (R7, C5, C8)
Vin(V)
3.3
5
12
Typical Applications
Vo(V)
Io(A)
Fsw(kHz)
500
1
1000
1.5
500
2
1000
500
1
1000
2.5
500
2
1000
500
1
1000
1.5
500
2
1000
500
1
1000
2.5
500
2
1000
500
1
1000
3.3
500
2
1000
1
500
1.5
2
500
500
1
1000
2.5
500
2
1000
500
1
1000
3.3
500
2
1000
500
1
1000
5
500
2
1000
500
1
1000
7.5
500
2
1000
500
1
1000
10
500
2
1000
C2(uF)
22
Recommended Parameters
L1(uH)
R7(k)
C5(nF)
C8(pF)
6.8
6.65
2.2
3.3
12.4
0.68
3.3
6.65
2.2
1.5
12.4
0.68
4.7
22.1
0.68
2.2
35.7
0.47
2.2
18.2
0.68
1.5
35.7
0.47
6.8
6.65
2.2
3.3
12.7
0.68
3.3
6.65
2.2
2.2
12.7
0.68
8.2
11.3
1.5
4.7
23.7
0.47
4.7
11.3
1
2.2
20
0.47
6.8
15
0.82
3.3
26.7
0.47
3.3
15
0.82
2.2
29.4
0.47
8.2
7.15
2.2
10
4.7
7.15
2.2
15
11.3
1
6.8
20
0.68
6.8
11.3
1
3.3
20
0.47
15
15
0.82
8.2
30.9
0.47
8.2
15
0.82
4.7
30.9
0.47
15
23.7
0.68
10
41.2
0.47
8.2
23.7
0.68
4.7
45.3
0.47
15
35.7
0.68
8.2
63.4
0.47
8.2
35.7
0.68
4.7
63.4
0.47
10
42.2
0.68
4.7
84.5
0.47
4.7
42.2
0.68
2.2
84.5
0.47
15
SC4524B
Typical Application Schematics
V
IN
D1
5V
C4
4.7mF
1N4148
C1
0.1mF
L1
BST
IN
SW
2.2mH
SC4524B
SS/EN
OUT
R4
33.2k
3.3V/2A
FB
COMP
C7
10nF
ROSC
R7
29.4k
C8
10pF
GND
D2
20BQ030
R5
18.2k
R6
14.3k
C2
22mF
C5
0.47nF
L1: Coiltronics LD1-2R2
C2: Murata GRM31CR60J226K
C4: Murata GRM31CR60J475K
Figure 10. 1MHz 5V to 3.3V/2A Step-down Converter
V
IN
D1
10V – 16V
1N4148
C4
4.7mF
C1
0.33mF
L1
BST
IN
SW
4.7mH
SC4524B
SS/EN
OUT
EVB #a
R4
33.2k
1.5V/2A
FB
COMP
C7
10nF
C8
10pF
ROSC
R7
7.15k
GND
R5
47.3k
D2
20BQ030
R6
66.5k
C2
22mF
C5
2.2nF
L1: Coiltronics DR73-4R7
C2: Murata GRM31CR60J226K
C4: Murata GRM31CR60J475K
Figure 11. 500kHz 10V-16V to 1.5V/2A Step-down Converter
EVB #b
16
SC4524B
SS
Typical Performance Characteristics
(For A 12V to 5V/2A Step-down Converter with 1MHz Switching Frequency)
SS270 REV 6-7
Load Characteristic
6
Output Voltage (V)
5
12V Input (5V/DIV)
4
3
5V Output (2V/DIV)
2
1
SS Voltage (1V/DIV)
0
0
0.5
1
1.5
2
2.5
3
10ms/DIV
Load Current (A)
OCP
Figure 12(a). Load Characteristic
Figure 12(b). VIN Start up Transient (IO=2A)
5V Output Short (5V/DIV)
5V Output Response (500mV/DIV, AC Coupling)
Inductor Current (1A/DIV)
Retry Inductor Current (2A/DIV)
SS Voltage (2V/DIV)
40us/DIV
Figure 12(c). Load Transient Response
(IO= 0.3A to 2A)
20ms/DIV
Figure 12(d). Output Short Circuit (Hiccup)
17
SC4524B
SO-8 EDP2 Outline
Outline Drawing - SOIC-8 EDP
A
D
e
N
DIM
A
A1
A2
b
c
D
E1
E
e
F
H
h
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1 E
1
2
ccc C
2X N/2 TIPS
e/2
B
D
aaa C
SEATING
PLANE
A2 A
C
bxN
bbb
A1
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.053
.069
.000
.005
.049
.065
.012
.020
.007
.010
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
.116 .120 .130
.085 .095 .099
.010
.020
.016 .028 .041
(.041)
8
0°
8°
.004
.010
.008
C A-B D
1.35
1.75
0.00
0.13
1.25
1.65
0.31
0.51
0.17
0.25
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
2.95 3.05 3.30
2.15 2.41 2.51
0.25
0.50
0.40 0.72 1.04
(1.05)
8
0°
8°
0.10
0.25
0.20
h
F
EXPOSED PAD
h
H
H
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION BA.
Land Pattern - SOIC-8 EDP
SO-8 EDP2 Landing Pattern
E
SOLDER MASK
D
DIM
(C)
F
G
Z
Y
THERMAL VIA
Ø 0.36mm
P
X
C
D
E
F
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.134
.201
.101
.118
.050
.024
.087
.291
(5.20)
3.40
5.10
2.56
3.00
1.27
0.60
2.20
7.40
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
18