YMF825

YMF825
SD-1
universal Sound Designer 1
■
Overview
YMF825 is a sound generator/controller/amplifier device with high quality melodies
and keypad/alert tones, designed for sophisticated audio user interface on home
appliances and office equipment products.
Yamaha's FM synthesizer produce high fidelity clean vivid sound, in no way
comparable to the traditional beeps and chimes used in such products, yet all the
control required is just a few tens of bytes of setup parameters.
As many as 16 FM voices are supported, and any host controller can manage those
voices using the on-chip melody sequencer that plays tunes autonomously without
host controller interventions.
Simple commands allow real time controls of sound during playback, such as
changing the volume levels or the repetition intervals of tones.
Moreover, the complete system can be built with the minimum number of external
components as the integrated amplifier can directly drive an 8 ohm loudspeaker
attached, up to 900 mW.
YMF825 CATALOG
CATALOG No. LSI-4MF825A40
2011.9
■ Features
■
YMF825
Features
□ 16-voice polyphonic FM synthesizer
□ 29 on-chip operator-waveforms and 8 algorithms offers a whole variety of
sound
□ Synchronous serial data link for host controller interface
□ Integrated loudspeaker driver (Also supports external amplifier connection)
□ Integrated 3-band equalizer
□ Integrated 16-bit monaural DAC
□ Integrated power-on reset
□ Flexible Power Supply Configurations
< Single 5-V Power Supply Configuration >
・Speaker driver supply
・I/O supply
・Core supply
SPVDD
IOVDD
VDD
5.0±0.5V (4.5 V to 5.5 V)
5.0±0.5V (4.5 V to 5.5 V)
Supplied from the on-chip regulator
< Dual Power Supply Configuration >
・Speaker driver supply
・I/O supply
・Core supply
SPVDD
IOVDD
VDD
5.0±0.5V (4.5 V to 5.5 V)
3.3±0.3V (3.0 V to 3.6 V)
3.3±0.3V (3.0 V to 3.6 V)
Configuration details
< Single 5-V power supply configuration>
・No need to supply power to the core supply (VDD).
→ Connect only a bypass capacitor to REG_C / VDD pin.
・SPVDD and IOVDD must be connected to the same power supply.
< Dual power supply configuration >
・IOVDD and VDD must be connected to the same power supply.
□ Lead-free SSOP24 package (YMF825-EZ)
4MF825A40
2
■ Pin Assignments
■
YMF825
Pin Assignments
TESTOUT
1
IRQ_N
●
24
XO
2
23
XI
SO
3
22
TESTINB
SI
4
21
TESTINA
SCK
5
20
TESTMODE1
SS_N
6
19
TESTMODE0
RST_N
7
18
VSS
REG_C / VDD
8
17
A_TEST
IOVDD
9
16
SPOUT2 / LINEOUT2
VREF
10
15
No Connection
SPVDD
11
14
SPOUT1 / LINEOUT1
SPVSS
12
13
No Connection
24-pin SSOP TOP View
4MF825A40
3
■ Pin Functions
■
YMF825
Pin Functions
No.
Name
I/O
Power
Supply
1
TESTOUT
O
IOVDD
2
3
4
5
6
IRQ_N
SO
SI
SCK
SS_N
O
Oe
I
I
I
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
7
RST_N
Is
IOVDD
8
REG_C / VDD
AO / P
IOVDD
/ －
9
10
11
12
IOVDD
VREF
SPVDD
SPVSS
P
AO
P
G
－
VDD
－
－
13
(No Connection)
－
－
14
SPOUT1/LINEOUT1
AO
SPVDD
15
(No Connection)
－
－
16
SPOUT2/LINEOUT2
AO
SPVDD
17
A_TEST
AIO
IOVDD
18
VSS
G
－
19
TESTMODE0
I
IOVDD
20
TESTMODE1
I
IOVDD
21
TESTINA
I
IOVDD
22
TESTINB
I
IOVDD
23
XI
XI / I
IOVDD
24
XO
XO
IOVDD
Function
Test output
→ This pin should be left open (No Connection).
Interrupt output
Serial data output (CPU interface)
Serial data input (CPU interface)
Serial clock (CPU interface)
Chip select (CPU interface)
Reset
→ Pull up to IOVDD when not used.
On-chip regulator capacitor connection / Core power supply
→ < Single 5V power supply configuration >
Connect capacitors only.
< Dual power supply configuration >
Supply 3.3 V (typ.) to VDD from the same power supply as
IOVDD.
I/O power supply and on-chip regulator input
Analog block reference voltage
Speaker amplifier power supply
Speaker amplifier GND
This pin must be left open. (No Connection)
(This pin must be electrically isolated not only from the power supply
and ground pins, and adjacent pins, but also from any other pins.)
Speaker output 1 / Line output 1
This pin must be left open. (No Connection)
(This pin must be electrically isolated not only from the power supply
and ground, pins and adjacent pins, but also from any other pins.)
Speaker output 2 / Line output 2
Analog test pin
→ This pin should be left open (No Connection).
GND
Test mode configuration
→ Connect to the VSS.
Test mode configuration
→ Connect to the VSS.
Test input pin
→ Connect to the VSS.
Test input pin
→ Connect to the VSS.
Crystal connection / Clock input
→ The external clock cannot be used when this device is used in single
5 V power supply configuration. Use a crystal in such designs.
Crystal connection
→ When the external clock is fed to XI pin, this pin must be left open.
AIO : Analog I/O
I
AO : Analog output
Is : Digital input (schmitt)
P
G
O : Digital output
Oe : Digital output (3-state)
4MF825A40
: Power
: GND
: Digital input
4
XI : Crystal resonator
input
XO
: Crystal
resonator output
■ Block Diagram
■
YMF825
Block Diagram
3.3V (for Digital Core &
Analog Core(except SPAMP))
RST_N
Regulator
(5V→3.3V)
IOVDD
Timing Gen
(for Digital I/O)
Dir ect Wr it e Access
VSS
SS_N
Read Access
SCK
SPOUT1／LINEOUT1
Buffer
SI
SO
Delay Wr it e
Access
SPOUT2／LINEOUT2
Speaker
Amp
SPVDD
SPVSS
VREF
IRQ_N
TESTMODE0
TESTMODE1
TESTINA
TESTINB
TESTOUT
VREF
A_TEST
Analog
Power On Reset
Digital
Power On Reset Circuit
< Timing Gen >
The timing generator block generates clocks and other timing signals required for the operations.
< CPU Interface >
The CPU interface block is a 4-wire CPU serial interface. The use of the interface is based on the assumption that
the following four signal lines are connected to host controller CPU: Chip Select (SS_N), Serial Clock (SCK), Data
Input (SI), and Data Output (SO).
< Interface Register >
The interface register can be accessed directly from the host controller CPU via the serial interface.
< Control Register >
The control register mainly controls the synthesizer block.
The control register is accessed for the timed-write operations of the sequencer, and also accessed for the direct write
or the read operations through the interface register.
< FIFO >
The FIFO, an abbreviation of "First In First Out", is a queue allowing data to be read in the same order they are written. The FIFO
is accessed through the interface register and used in the timed-write path to the control register by the sequencer. The size of the
FIFO is 512 Bytes.
4MF825A40
5
■ Block Diagram
YMF825
< Sequencer >
The sequencer controls the de-queuing of the sequenced data queued into the FIFO.
The data structure is as follows:
Timing information (Timer part) + control register address (Address part) + control register data to be written (Data part)
The sequencer waits for the time of the Timer part before writing the Data part to the control register address specified
(timed-write operations). This timed de-queuing of the sequenced data to control the FM synthesizer results in the playing back of
the music tunes.
< FM Synthesizer >
The polyphonic FM synthesizer can generate up to 16 voices.
Variety in sound authoring is provided with the wider choice of operator waveforms.
The sampling frequency for the internal processing is 48 kHz.
< 3-Band Equalizer >
This is a 3-band digital equalizer.
< High Pass Filter >
This filter, a first-order IIR filter, is the DC-cut high-pass filter.
Its cut-off frequency is 20Hz.
< Master Volume >
This is the digital master control of overall volume level.
< 16-bit DAC >
The DAC block converts the digital signals from the digital block into analog signals.
The data resolution is 16 bits.
< Speaker Amp >
The speaker amplifier is the monaural speaker amplifier with four-level gain settings.
< Regulator >
The linear regulator supplies 3.3V (typ.).
< Power-On Reset>
This circuit resets the registers on power up.
This reset works exactly the same as the hardware reset pin.
Notes on Power-On Reset
When this device is powered down and then powered up again, this power-on reset may not function unless
this device is left unpowered for a sufficient time.
4MF825A40
6
■ Electrical Characteristics
■
YMF825
Electrical Characteristics
● Absolute Maximum Ratings
Parameter
SPVDD supply voltage
IOVDD supply voltage
VDD supply voltage
Digital input voltage (See Note 1.)
Analog input voltage
Power dissipation (See Note 2.)
Junction Temperature
Storage Temperature
Symbol
SPVDD
IOVDD
VDD
VIND
VINA
Pd
Tj
TSTG
Min.
−0.3
−0.3
−0.3
−0.3
−0.3
−50
Max.
7.0
7.0
4.6
IOVDD+0.3
IOVDD+0.3
1638
150
150
Unit
V
V
V
V
V
mW
°C
°C
Conditions VSS=SPVSS=0 V
Note1) These limits must be observed even if the supply voltage is out of the recommended operating
voltage range.
For example, when the power supply pin is at 0 V, any voltage over 0.3V is beyond the limit.
Note 2) Conditions:
• Top= 25 °C, PCB (50 mm × 50 mm × 1.6 mm), FR-2 board, trace density 50 %
• Derate the value with 13.1 mW/°C for the temperature above 25 °C.
4MF825A40
7
■ Electrical Characteristics
YMF825
● Recommended Operating Conditions
·
Single 5-V Power Supply Configuration
Parameter
SPVDD supply voltage
IOVDD supply voltage
Speaker load resistance
Operating ambient temperature
Symbol
SPVDD
IOVDD
RL
Ta
Min.
4.5
4.5
6.4
−20
Typ.
5.0
5.0
8.0
25
Max.
5.5
5.5
85
Unit
V
V
Ω
°C
Conditions VSS=SPVSS=0 V
Notes
・IOVDD and SPVDD must be connected to the same power supply.
・Connect only a capacitor to REG_C / VDD pin and do not supply powers.
·
Dual Power Supply Configuration
Parameter
SPVDD supply voltage
IOVDD supply voltage
VDD supply voltage
Speaker load resistance
Operating ambient temperature
Symbol
SPVDD
IOVDD
VDD
RL
Ta
Min.
4.5
3.0
3.0
6.4
−20
Typ.
5.0
3.3
3.3
8.0
25
Conditions VSS=SPVSS=0 V
Note
・IOVDD and VDD must be connected to the same power supply.
4MF825A40
8
Max.
5.5
3.6
3.6
85
Unit
V
V
V
Ω
°C
■ Electrical Characteristics
YMF825
● Power Consumption
All the drawn current values in the tables are typical representative values to help your design decisions.
Single 5-V Power Supply Configuration
·
Parameter
Drawn current, normal operation
(AP*=all “0”, CLKE=“1”)
Drawn current, power-down
(AP0=“0”, AP[1/2/3]= “1”, CLKE=“0”)
Conditions
No signal output
RL=8Ω load, f=1kHz, 400mW
SPVDD
5
200
Unit
mA
mA
5
0
mA
IOVDD
(+ VDD)
SPVDD
Unit
No signal output
RL=8Ω load, f=1kHz, 400mW
15
5
200
mA
mA
VIL=VSS, VIH=IOVDD
3
0
mA
IOVDD
(+ VDD)
SPVDD
Unit
No signal output
RL=8Ω load, f=1kHz, 400mW
14
5
200
mA
mA
VIL=VSS, VIH=IOVDD
2
0
mA
VIL=VSS, VIH=IOVDD
IOVDD
17
Conditions SPVDD = IOVDD = 5.0 V, room temperature.
Dual Power Supply Configuration
·
i)
Use of Crystal Resonator
Parameter
Drawn current, normal operation
(AP*=all “0”, CLKE=“1”)
Drawn current, power-down
(AP0=“0”, AP[1/2/3]= “1”, CLKE=“0”)
Conditions
Conditions SPVDD = 5.0 V, IOVDD = VDD = 3.3 V, room temperature.
ii)
Use of External Clock
Parameter
Drawn current, normal operation
(AP*=all “0”, CLKE=“1”)
Drawn current, power-down
(AP0=“0”, AP[1/2/3]= “1”, CLKE=“0”)
Conditions
Conditions SPVDD = 5.0 V, IOVDD = VDD = 3.3 V, room temperature.
XI pin: 12.288 MHz clock, XO pin: No connection
4MF825A40
9
■ Electrical Characteristics
YMF825
● DC Characteristics
Parameter
Symbol
Input Voltage “H” level (1)
VIH
Input Voltage “L” level (1)
VIL
Input Voltage “H” level (2)
VIH
Input Voltage “L” level (2)
VIL
Output Voltage “H” level (1)
VOH
Output Voltage “L” level (1)
VOL
Schmitt hysteresis width
Input leakage current
Input capacitance
Vsh
IL
CI
Condition
(See Note 1.)
(See Note 1.)
(See Note 2.)
(See Note 2.)
IOH =
(See Note 3.)
IOL =
(See Note 3.)
(See Note 4.)
Min.
0.80  IOVDD
Typ.
Max.
0.20  IOVDD
0.70  IOVDD
0.30  IOVDD
0.80  IOVDD
0.20  IOVDD
V
10
10
mV
A
pF
0.20  IOVDD
−10
Conditions Capacitor load=30pF. For operations under the recommended operating conditions
Note 1: RST_N pin only
Note 2: SI, SCK, SS_N, and XI (only when an external clock is used) pins only
Note 3: IRQ_N: 2mA
SO: 4mA
Note 4: RST_N only
Note
Consider the use of signal damping resistors where appropriate, in product designs.
4MF825A40
10
Unit
V
V
V
V
V
■ Electrical Characteristics
YMF825
● AC Characteristics
Power Supply Timing Requirements
Either requirements A or B must be met:
● Requirement A
Parameter
Supply voltage rise time
Power off interval
(See Note 1.)
(See Note 2.)
Symbol
TVRISE
TVOFF
Min.
Typ.
Max.
10
Unit
ms
ms
Typ.
Max.
10
Unit
ms
ms
μs
100
Conditions For operations under the recommended operating conditions
● Requirement B
Parameter
Supply voltage rise time
(See Note 1.)
Reset_N "L" pulse width
Reset_N (undefined →" L") Setup Time
Symbol
TVRISE
TRSTW
TRSTS
Min.
1
0
Conditions For operations under the recommended operating conditions
Note 1) This specifies the supply voltage rise time requirement (from power up until the minimum supply voltage value of
the recommended operating conditions is reached).
Note 2) This specifies the unpowered interval required before the device can power up again.
If this requirement is not met, the power-on reset may not be performed properly.
Be sure to meet this requirement for the system without using RST_N pin.
< Single 5-V Power Supply Configuration >
TVOFF
TVRISE
4.5V
Power Up
0.4V
TRSTS
TRSTW
VIL= 0.2×IOVDD
↑ Keep RST_N signal within the maximum absolute ratings including these undefined periods.
4MF825A40
11
■ Electrical Characteristics
YMF825
< Dual Power Supply Configuration >
TVRISE
4.5V
Power Up
TVOFF
TVRISE
3.0V
Power Up
0.4V
TRSTS
TRSTW
VIL= 0.2×IOVDD
↑ Keep RST_N signal within the maximum absolute ratings including these undefined periods.
Notes
< Single 5-V Power Supply Configuration >
・IOVDD and SPVDD must be connected to the same power supply.
< Dual Power Supply Configuration >
・IOVDD and VDD must be connected to the same power supply.
4MF825A40
12
■ Electrical Characteristics
YMF825
Input Clock (XI) Requirements
Parameter
XI frequency
XI Rise time, Fall time (See Note 1.)
XI High time (See Note 1.)
XI Low time (See Note 1.)
Frequency tolerance
Symbol
1 / Tfreq
Trckc, Tfckc
Th
Tl
－
Min.
Typ.
12.288
Max.
20
20
20
−100
+100
Unit
MHz
ns
ns
ns
ppm
Conditions For operations under the recommended operating conditions
Note 1) These values specify the requirements for the external clocks on XI pin.
Trckc
Tfckc
Th
Tl
VIH= 0.7×IOVDD
XI
0.5×IOVDD
VIL= 0.3×IOVDD
Tfreq
4MF825A40
13
■ Electrical Characteristics
YMF825
CPU Interface
Parameter
SCK Period
SCK “L” pulse width (See Note 1.)
SCK “H” pulse width (See Note 1.)
SCK Rise time
SCK Fall time
SS_N “H” pulse width (See Note 2.)
SS_N Rise time
SS_N Fall time
SS_N Setup time
SS_N Hold time
SI Rise time
SI Fall time
SI Setup time
SI Hold ime
SO Output Delay 1
SO Output Delay 2
SO Output Delay 3
Symbol
Tsck_period
Tsck_low
Tsck_high
Tsck_rise
Tsck_fall
Tssn_high
Tssn_rize
Tssn_fall
Tssn_setup
Tssn_hold
Tsi_rize
Tsi_fall
Tsi_setup
Tsi_hold
Tso_delay1
Tso_delay2
Tso_delay3
Min.
100
45
45
Typ.
Max.
5
5
500 / 100
5
5
15
10
5
5
15
10
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions Capacitor Load=30pF. For operations under the recommended operating conditions
IOH / IOL= 0 mA (SO pin only)
Input signal levels: VIH = IOVDD, VIL = 0 V
Logic threshold levels: VIH = 0.70 × IOVDD, VIL = 0.30 × IOVDD
VOH= 0.70 × IOVDD, VOL= 0.30 × IOVDD
Note 1) The sum of the two periods Tsck_low + Tsck_high must be equal to the minimum value of Tsck_period or greater.
Note 2) When I_ADR#21 and #22 are used to read a control register, a write to I_ADR#21 must be followed by SS_N kept
"H" for 500 ns before I_ADR#22 is ready for a read.
For other use, SS_N must be "H" for 100 ns between accesses.
4MF825A40
14
■ Electrical Characteristics
4MF825A40
YMF825
15
■ Electrical Characteristics
YMF825
● Analog Characteristics
The measurement conditions are as follows:
TOP=25 °C
IOVDD=SPVDD=5 V
GAIN[1:0]= "1"(6.5 dB), RL=8Ω, CREG_OUT=4.7μF, CVREF=1μF
Parameter
Maximum Output Power GAIN[1:0]= "2’b11"(7.5dB)
Maximum Output Voltage Amplitude GAIN[1:0]=
"2’b11"(7.5dB)
Output Offset Voltage
Quiescent Output Voltage
Frequency Characteristics
(50Hz to 20kHz, with reference to the 1kHz level)
Total Harmonic Distortion
(1kHz, 400mW, 22kHz LPF)
Residual Noise Level (A-weighted)
Capacitive Load on Speaker Output
VREF Voltage
VREF Settling Time
On-chip Regulator Output Voltage
On-chip Regulator Settling Time
4MF825A40
Min.
Typ.
900
7.58
Max.
Unit
mW
Vp-p
10
2.50
50
mV
V
dB
−3.5
0.5
0.3
%
-85
1000
1.65
30
3.3
27
16
100
dBV
pF
V
ms
V
μs
■ Package Information
■
YMF825
Package Information
4MF825A40
17
YMF825
PRECAUTIONS AND INSTRUCTIONS FOR SAFETY
WARNING
Prohibited
Prohibited
Prohibited
Instructions
Do not use the device under stresses beyond those listed in Absolute Maximum Ratings.
Such stresses may become causes of breakdown, damages, or deterioration, causing explosion
or ignition, and this may lead to fire or personal injury.
Do not mount the device reversely or improperly and also do not connect a supply voltage in
wrong polarity. Otherwise, this may cause current and/or power-consumption to exceed the
absolute maximum ratings, causing personal injury due to explosion or ignition as well as causing
breakdown, damages, or deterioration.
And, do not use the device again that has been improperly mounted and powered once.
Do not short between pins.
In particular, when different power supply pins, such as between high-voltage and low-voltage
pins, are shorted, smoke, fire, or explosion may take place.
As to devices capable of generating sound from its speaker outputs, please design with safety of
your products and system in mind, such as the consequences of unusual speaker output due to a
malfunction or failure. A speaker dissipates heat in a voice-coil by air flow accompanying
vibration of a diaphragm. When a DC signal (several Hz or less) is input due to device failure,
heat dissipation characteristics degrade rapidly, thereby leading to voice-coil burnout, smoking or
ignition of the speaker even if it is used within the rated input value.
CAUTION
Prohibited
Instructions
Instructions
Instructions
Instructions
Instructions
Instructions
Instructions
Do not use Yamaha products in close proximity to burning materials, combustible substances, or
inflammable materials, in order to prevent the spread of the fire caused by Yamaha products, and
to prevent the smoke or fire of Yamaha products due to peripheral components.
Generally, semiconductor products may malfunction and break down due to aging, degradation,
etc. It is the responsibility of the designer to take actions such as safety design of products and
the entire system and also fail-safe design according to applications, so as not to cause property
damage and/or bodily injury due to malfunction and/or failure of semiconductor products.
The built-in DSP may output the maximum amplitude waveform suddenly due to malfunction from
disturbances etc. and this may cause damage to headphones, external amplifiers, and human
body (the ear). Please pay attention to safety measures for device malfunction and failure both in
product and system design.
As semiconductor devices are not nonflammable, overcurrent or failure may cause smoke or fire.
Therefore, products should be designed with safety in mind such as using overcurrent protection
circuits to control the amount of current during operation and to shut off on failure.
Products should be designed with fail safe in mind in case of malfunction of the built-in protection
circuits. Note that the built-in protection circuits such as overcurrent protection circuit and
high-temperature protection circuit do not always protect the internal circuits. In some cases,
depending on usage or situations, such protection circuit may not work properly or the device
itself may break down before the protection circuit kicks in.
Use a robust power supply.
The use of an unrobust power supply may lead to malfunctions of the protection circuit, causing
device breakdown, personal injury due to explosion, or smoke or fire.
Product's housing should be designed with the considerations of short-circuiting between pins of
the mounted device due to foreign conductive substances (such as metal pins etc.). Moreover,
the housing should be designed with spatter prevention etc. due to explosion or burning.
Otherwise, the spattered substance may cause bodily injury.
The device may be heated to a high temperature due to internal heat generation during
operation. Therefore, please take care not to touch an operating device directly.
v02
4MF825A40
18
YMF825
eC02