MT88V32 Data Sheet

MT88V32
8 x 4 High Performance Video Switch
Array
Data Sheet
Features
•
March 2006
32 bidirectional CMOS "T" switches in an 8×4
non-blocking array
•
Break-before-make switching configuration
•
Fast setup & hold times for switch programming
•
3 dB bandwidth of 200 MHz
•
Low feedthrough and crosstalk, better than 80 dB at 5 MHz
•
Very low differential gain and phase errors
•
12Vpp bipolar signal capability
•
On-state resistance 75 Ω (max) for VDD=+5V,
VEE=-7V
•
Switch control through 2-stage latches
•
Orthogonal Xi and Yi pin connections for
optimized PCB layout
•
Latch readback capability for monitoring
Ordering Information
MT88V32AP
44 Pin PLCC
MT88V32APR
44 Pin PLCC
MT88V32AP1
44 Pin PLCC*
MT88V32APR1
44 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT88V32 is a digitally programmable (TTL levels)
8×4 crosspoint switch that is designed to control wideband analog (video) signal.
Each of the 32 nodes of the switching matrix has a Tswitch, see Fig.1. This grounds the nodes of all open
connections, which greatly reduces feedthrough noise.
In order to reduce crosstalk, individual analog signal
lines are isolated by interleaving them with ground
lines.
The two stage programmable latch system allows the
state of all switching nodes to be updated
simultaneously. The next state of the switch is written
into the first stage of the latches through individual
write cycles. These changes will not affect the current
state of the switch. The STROBE2 control input is used
to load the state of all first stage latches to the second
stage latches, which updates the complete matrix.
Applications
•
High-end video routing and switching
•
Medical instrumentation
•
Automatic test equipment (ATE)
•
Multi-media communication
Y0-Y7
GND
Tubes
Tape & Reel
Tubes
Tape & Reel
VDD VEE VSS
X0
X1
X2
X3
8x4
"T" Switch Array
MR
Xi
Yi
STROBE2
STROBE1
2nd Stage Latches
I/O
Control
Logic
1st Stage Latches
R/W
DATA
GND
CS
T-Switch Configuration
Address Decode
AX0-AX1
AY0-AY2
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1993-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT88V32
Data Sheet
Therefore, all 32 switching nodes are updated simultaneously.
GND
Y0
GND
GND
X0
GND
X1
GND
X2
GND
X3
The MT88V32 supports separate analog (VEE) and digital (VDD) voltage references. This allows the user to select
an optimum analog signal bias point.
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
GND
NC
MR
STROBE2
STROBE1
R/W
CS
DATA
AY0
AY1
NC
GND
Y7
GND
VEE
IC*
VDD
VSS
AX1
AX0
AY2
NC
Y1
GND
Y2
GND
Y3
GND
Y4
GND
Y5
GND
Y6
* Connects toVEE
Figure 2 - Pin Connections
Pin Description
Pin #*
Name
Description
1, 3, 4, 6,
8, 10, 12,
14, 16,
18, 20,
39, 41,
43
GND
Analog Ground. Connect to system ground for crosstalk noise isolation. Pins 3 and 39
are not bonded internally.
2, 44,
42, 40
X0, X1,
X2, X3
Analog Lines (input/output).
5, 7,
9, 11,
13, 15,
17, 19
Y0, Y1,
Y2, Y3
Y4, Y5,
Y6, Y7
Analog Lines (input/output).
21
VEE
22
IC
23
VDD
Positive Power Supply.
24
VSS
Digital Ground Reference.
25, 26
AX1,AX0
X0-X3 I/O Address Select (inputs).
27, 30,31
AY2-AY0
Y0-Y7 I/O Address Select (inputs).
28, 29
NC
Negative Analog Power Supply.
Internal Connection.
No Connection.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
Pin Description
Pin #*
Name
Description
32
DATA
DATA (input/output). When input, a logic high will close the selected switch and a logic
low will open the selected switch. When output, a logic high indicates a closed switch
and a logic low indicates an opened switch.
33
CS
Chip Select (input). Active low.
34
R/W
READ/WRITE Control (input). When high the DATA pin is an output (for reading from
second stage latch); when low the DATA pin is an input (for writing to first stage latch).
35
STROBE1 STROBE 1 (input). Modifies memory content of first stage latch as determined by the
addess and data lines, but does not change the switch array configuration of entire
switch array. Active low.
36
STROBE2 STROBE 2 (input). Transfers memory content of first stage latch to the second stage
latch and hence, changes the configuration of entire switch array. Active low.
37
MR
MASTER RESET (input). Used to reset the first and second stage latches. Active low.
38
NC
No Connection.
Functional Description
The state of the MT88V32 8 X 4 switching matrix is updated through a simple parallel processor interface. This
interface provides access to 32 two stage latches, which determines the state (open/close) of each switching array
node. Each latch (or node) is addressed by the AX0-AX1 and AY0-AY2 inputs as per Table 2, and the DATA input
will determine if the connection is to be made (DATA=1) or opened (DATA=0).
The second stage of the two stage latches controls the current state of each switching node. The value held in the
first stage is the input to the second stage. This allows the device to be programmed in two ways. That is, individual
switching nodes may be updated one at a time, or all nodes may be updated at once.
To update one node at a time the STROBE2 input should be held low. This makes the second stage latches
transparent and the matrix immediately reflects the state of the first stage latches. A write cycle example follows:
1. STROBE2 is low,
2. CS and R/W are low, MR is high,
3. AX0-AX1 and AY0-AY2 as per Table 2,
4. DATA input high to close or low to open, and
5. STROBE1 toggled from high-to-low-to-high.
These steps (one write cycle) may be repeated for each switch state change. This can also be accomplished by
holding STROBE1 low and toggling STROBE2. See Figure 14 for timing.
To update all nodes simultaneously all switch state changes must be written into the first stage latches. This is
accomplished by holding STROBE2 high and performing steps 2) through 5) above for each switching node that is
to be changed. Writing to the first stage latches only will not affect the switching state of the matrix. When the
changes have been made all the switches of the matrix may be updated simultaneously by toggling the STROBE2
input from high-to-low-to high.
When STROBE2 is used to update the state of the MT88V32 all switch “breaks” are completed before any switch
“makes” occur. There is approximately 10ns delay between “breaks” and “makes”.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
Both the first and second stage latches will be cleared when the master reset (MR) is taken from high-to-low. This
will open all the switch nodes. The operation of MR is independent of CS, AX0-AX1, AY0-AY2 and R/W.
The status of each switching array node (second stage latch) can be read through the bidirectional DATA pin. A
read cycle example follows:
1. CS is low, R/W and MR are high,
2. AX0-AX1 and AY0-AY2 as per Table 2, and
3. DATA output high for closed or low for open.
MR
R/W
CS
DATA
STROBE1
STROBE2
DATA
1
1
0
0
1
0
0
1
1→ 0
1→ 0
1
1
No Change to 1st stage latch.
1st stage latch is loaded with data.
1
1
0
0
0
0
0
1→ 0→ 1
0
0
1
1
1st stage latch is transparent.
Selected latch is cleared and set again (i.e.,
output follows input).
1
1
0
0
0
x
1
x
0→ 1
1
1
1→ 0
1st stage latch output is frozen.
Output of 1st stage latch is transferred to
output of 2nd stage latches.
1
1
0
0
x
0
x
x
1
0
0→1
0
2nd stage latch output is frozen.
Both 1st stage and 2nd stage latches are
transparent.
1
1
0
0
x
x
DATA becomes an output and reflects the
contents of the 2nd stage latch addressed
by AX0-AX1 and AY0-AY2.
0
1
1
1
1
1
All crosspoints opened (data in 1st and 2nd
stage latches are cleared).
Table 1 - Truth Tables
Note:
x = don’t care, 0 = logic "0" state, 1 = logic "1" state
A logic 1 on DATA input closes a connection
A logic 0 on DATA input opens a connection.
AX1
AX0
AY2
AY1
AY0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
0
↓
0
1
↓
1
0
↓
1
0
↓
1
0
↓
1
Y0 to X1
↓
Y7 to X1
1
↓
1
0
↓
0
0
↓
1
0
↓
1
0
↓
1
Y0 to X2
↓
Y7 to X2
1
↓
1
1
↓
1
0
↓
1
0
↓
1
0
↓
1
Y0 to X3
↓
Y7 to X3
Table 2 - Address Decode Truth Table
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Zarlink Semiconductor Inc.
Switch Connections
to
to
to
to
to
to
to
to
X0
X0
X0
X0
X0
X0
X0
X0
MT88V32
Data Sheet
It should be noted that the STROBE1 function is disabled during a read cycle. See Fig. 15 for timing.
The MT88V32 can operate from a dual rail power supply (VDD and VEE) or a single rail power supply (VSS=VEE=0V)
as per the recommended operating conditions. For minimum on-state resistance the supply voltages should be
VDD=5.0 VDC, VSS=0 VDC and VEE=-7 VDC. The analog input signal should be biased at -2.0 VDC to achieve
minimum differential phase and gain error (see AC Electrical Characteristics - Crosspoint Performance).
Applications
Figure 3 illustrates examples of how to connect the signal lines of the MT88V32 to various interfaces. Input buffers
allow the incoming signals to be scaled and biased to the optimum operating range of the MT88V32 (i.e., differential
phase error, differential gain error and RON). Buffers will also allow a more precise input impedance to be
implemented. For low grade video applications, signal lines may be connected directly, as long as the ultimate
source and terminating impedances are matched.
Wideband
Output Buffers
75Ω
10kΩ
75Ω
Wideband
Input Buffers
10kΩ
75Ω
X0
X1
75Ω
X2
X3
75Ω
75Ω
MT88V32
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
10kΩ
Wideband
Output Buffers
10kΩ
Control Interface
10kΩ
To next
switching
stage
10kΩ
R
Figure 3 - High Frequency Switching Applications
Output buffers may be used to provide signal gain and impedance matching for external connections. Additionally,
they may be used to isolate parasitic device capacitance in multiple stage switching applications where high
frequency roll-off is critical. Crosstalk, as well as differential phase and gain error can be minimized by designing a
low source impedance (e.g., 10 ohms), and a high terminating impedance (e.g., 10 k) at each stage. If successive
switching stages are not buffered, then a resistor to ground (R) should be present between the switches. Selection
of R is based on the following compromise:
1. as R is decreased to approach the source and terminating resistance values signal loss will increase and
crosstalk will decrease, and
2. as R increases signal loss will decrease and crosstalk will increase.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
It is recommended that the power supply rails of the MT88V32 be decoupled with 0.1 µF ceramic Z5U and 10 µF
dipped tantalum capacitors. These capacitors should be as close to the device as possible. The signal pins of the
MT88V32 are interleaved with analog ground lines. This allows the circuit designer to run ground tracks on both
sides of each signal line to improve crosstalk immunity.
The 8x4 bidirectional CMOS T-switch configuration is a modular switching element in a convenient package size.
The inherent flexibility of this device permits the designer to build large switching matrices, see analog switch
application notes.
A5
A4
A3
A2
A1
A0
D0
Function
0
0
0
0
0
0
1/0
Y0 to X0
↓
↓
↓
↓
↓
↓
↓
0
1
1
1
1
1
1/0
Y7 to X3
1
X
X
X
X
0
X
MR
1
X
X
X
X
1
X
STB2
↓
↓
Table 3 - Address Decoding for the Processor Interfaces
Note: x = undefined, 1/0 -1 = make, 0 = break
Figures 4, 5 and 6 show methods of interfacing the MT88V32 to Motorola and Intel microcontrollers. The address
decoding for these configurations is in Table 3.
Video Signal Terminology
1. Component Video - separate red (R), blue (B), green (G), and synchronization signals.
2. Composite Video - contains luminance (brightness), chrominance (colour), and synchronization signal components in a single waveform.
3. Synchronization signal - horizontal sync pulses are negative going excursions of the composite video signal that
occur every 63.5 µsec. Their function is to align the horizontal sweep.
4. Luminance - is the black to white brightness component of a composite video signal. Its range is from reference
white (maximum amplitude) to reference black (minimum amplitude).
5. Chrominance - rides on the luminance signal and determines the hue (phase) and brightness (amplitude) of the
colour component of a composite video signal.
6. Colour burst - is about 9 (minimum 8) cycles of a 3.578545 MHz reference signal, which is transmitted with
every horizontal sweep of the composite video signal. A phase comparison between this reference signal and
the chrominance signal determines colour hue.
7. Differential Phase Error - (measured in degrees) is a phase change in the chrominance signal due to a change
in luminance amplitude.
8. Differential Gain Error - (measured in percentage) is a change in amplitude of the chrominance signal due to a
change in luminance amplitude.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
MC6800/
MT88V32
6802/6809
Φ2
STB1
STB2
VMA
A5 + A0 + VMA
11
A5-A15
MR
A5 + A0 + VMA
CS
A0
A5 +VMA
5
A0-A4
AY0-AY1
AX0-AX2
DATA
D0
R/W
R/W
Notes: for the MC6802 Φ2 will be E.
for the MC6809 Φ2 will be E and VMA will be the OR’ed product of Q and E.
Figure 4 - Motorola Non-multiplexed Processor Interface
MC6801/
6803/68HC11
(PC) AD0-AD4
AD0
74HCT574
AD0
3
(PC) AD5-AD7
(PB) A8-A15
MT88V32
5
8
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
DATA
A5
AY0
AY1
AY2
AX0
AX1
CS
A5 + A0
STB2
CLK OC
AS
A5 + A0
MR
E
STB1
R/W
R/W
Figure 5 - Motorola Multiplexed Processor Interface
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Zarlink Semiconductor Inc.
MT88V32
8031/8051
8085
(P0) AD0-AD4
AD0
MT88V32
5
74HCT574
AD0
3
(P0) AD5-AD7
(P2) A8-A15
Data Sheet
8
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
DATA
A5
AY0
AY1
AY2
AX0
AX1
CS
A5 + A0
STB2
CLK OC
ALE
A5 + A0
MR
WR
STB1
RD
R/W
Figure 6 - Intel Processor Interface
Figure 7 - Typical On-state Resistance (RON) vs. DC Bias (Vdc) @ VDD=+5V, VEE=-7V
8
Zarlink Semiconductor Inc.
MT88V32
Figure 8 - Single Channel Feedthrough (all crosspoints open)
Figure 9 - Single Channel Crosstalk (one crosspoint closed)
9
Zarlink Semiconductor Inc.
Data Sheet
MT88V32
Figure 10 - All Channel Crosstalk (all crosspoints closed)
Figure 11 - 3 dB Frequency Response
10
Zarlink Semiconductor Inc.
Data Sheet
MT88V32
Figure 12 - Typical Differential Phase vs. Ramp Voltage
11
Zarlink Semiconductor Inc.
Data Sheet
MT88V32
Figure 13 - Typical Differential Gain vs. Ramp Voltage
12
Zarlink Semiconductor Inc.
Data Sheet
MT88V32
Data Sheet
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
VDD to VSS
VDD to VEE
VSS to VEE
GND to VSS
Min.
Max.
Units
-0.3
-0.3
-0.3
VEE -0.3
15
15
15
VDD+0.3
V
V
V
V
1
Supply Voltage
2
Analog Input Voltage
VIN
VEE-0.3
VDD+0.3
V
3
Digital Input Voltage
VIND
VSS-0.3
VDD+0.3
V
4
Continuous Current (any analog I/O terminal)
±15
mA
5
Storage Temperature
-65
+150
°C
6
Operating Temperature
-40
+85
°C
7
Package Power Dissipation
600
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to 0 V unless otherwise stated.
Characteristics
1
Supply Voltage
Sym.
Min.
Typ.
Max.
Units
12
VDD
VEE
4.5
-8.5
4.5
-8.5
13.2
0
13.2
0
V
V
V
V
VDD-VEE
VEE-VSS
5.0
-7.0
2
Analog Input Voltage
VIN
VEE
VDD
V
3
Digital Input Voltage
VIND
VSS
VDD
V
4
Analog Ground
GND
VEE
VDD
V
0
Test Conditions
VEE=VSS=0V
VDD=4.5V, VSS=0V
DC Electrical Characteristics†- Analog Switch Characteristics
Voltages are with respect to VDD=+5V, VEE =-7V, VSS=0V unless otherwise stated.
25°C
Characteristics
1
On-state Resistance
85°C
Test
Typ.‡
Max.
Max.
Units
50
60
140
65
75
185
75
85
220
Ω
Ω
Ω
∆RON
6
10
10
Ω
IVXi-VYjI = 0.4V
VIN=VDC=(VDD+VEE)/2
Sym.
RON
VEE=-7V
VEE=-5V
VEE=0V
Conditions
VIN=VDC=(VDD+VEE)/2
IVXi-VYjI = 0.4V
See Figure 7.
2
Difference in on-state resistance
between switches
3
Off-state leakage current
IOFF
±10
±200
nA
VIN=VDD or VEE
4
On-state leakage current
ION
±10
±200
nA
VIN=VDD or VEE
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
DC Electrical Characteristics†- Power Supplies - Voltages are with respect to VDD=+5V, VEE =-7V, VSS=0V,
MR = 0.8V unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
Positive Supply Current
IDD
1
0.4
5
100
1.5
15
µA
mA
mA
VIND=VDD or VSS
VIND=2.4V
VDD=12V, VSS=VEE=0V,
VIND=3.4V
2
Negative Supply Current
IEE
1
1
1
100
100
100
µA
µA
µA
VIND=VDD or VSS
VIND=2.4V
VDD=12V, VSS=VEE=0V,
VIND=3.4V
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Digital Input/Output
Voltages are with respect to VDD=5V, VEE=-7V, VSS=0V, unless otherwise stated.
Characteristics
1
2
Input logic "1" level
Input logic "0" level
Typ.‡
Sym.
Min.
Max.
Units
VIH
2
V
VIH
3.3
V
Test Conditions
VEE=VSS=0, VDD=12V
VIL
0.8
V
VIL
0.8
V
VEE=VSS=0, VDD=12V
±10
µA
VIND=VDD or VSS
VDD
V
IOH=7mA@VOH=2.4V
±1
3
Input leakage (digital pins)
ILEAK
4
Data output high voltage
VOH
2.4
5
Data output high current
IOH
7
6
Data output low voltage
VOL
VSS
7
Data output low current
IOL
2
8
Data high impedance leakage
IOZ
20
mA
0.4
5
1
10
V
source VOH=2.4V
IOL=2mA@VOL=0.4V
mA
sink VOL=0.4V
µA
VO=0 to VDD
† DC Electrical Characteristics are over recommended temperature range and recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Algebraic convention is adopted in this data sheet where the most negative value is a minimum and the most positive value is a
maximum.
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Zarlink Semiconductor Inc.
MT88V32
Data Sheet
AC Electrical Characteristics† - Crosspoint Performance- Voltages are with respect to VDD=+5V, VDC=0, VEE=-7V, VSS=0V,
unlesss otherwise stated. Also applicable for VEE=VSS=0, VDD=+12V, VDC=(VDD+VEE)/2.
Characteristics
Sym.
Units
CXi (on)
56
pF
1 Xi to 1 Yi
CYi (on)
56
pF
1 Yi to 1 Xi
CXi (off)
30
pF
CYi (off)
15
pF
2
Off-state Xi
capacitance2
4
Off-state Yi
capacitance2
5
Break-before-Make interval
topen
6
Single channel feedthrough
(all crosspoints open)
(see Fig. 8)
FDT
Single channel feedthrough
(all crosspoints closed)
(See Fig. 9)
Xtalk
(sc)
1
2
3
7
On-state Xi capacitance
On-state Yi capacitance
Typ.‡
Max.
1
Min.
Xtalk
(sc)
Test Conditions
10
ns
-80
-62
dB
dB
RS= RL=75Ω
VIN=0.6Vpp @ 5MHz
VIN=0.6Vpp @ 15MHz
-85
-68
dB
dB
RIN= 10Ω, RL= 10kΩ
VIN=0.6Vpp @ 5MHz
VIN=0.6Vpp @ 15MHz
-70
-50
dB
dB
RIN= 75Ω, RL= 10kΩ
VIN=0.6Vpp @ 5MHz
VIN=0.6Vpp @ 15MHz
8
All channel crosstalk
(all crosspoints closed)
(See Fig. 10)
Xtalk
(ac)
-55
dB
9
Frequency Response
(see Fig.11)
f3dB
200
MHz
10
Differential Phase Error
DP
0.05
o
See Note 1, RS= 50Ω,
RL= 75Ω
11
Differential Gain Error
DG
0.11
%
See Note 1, RS= 50Ω,
RL= 75Ω
RIN= 10Ω, RL= 10kΩ
VIN=0.6Vpp @ 5MHz
RS= RL=50Ω
† Timing is over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1 Valid for V =-7V, V
EE
DD=+5V and VDC=-2.0V. Error will increase slightly if input is biased differently.
Input test signal: 700mV ramp biased @ -2.0 Vdc with a superimposed video signal of 285Vrms @ 3.58 MHz.
2 Guaranteed by design and characterization and not subject to production testing.
15
Zarlink Semiconductor Inc.
MT88V32
Data Sheet
AC Electrical Characteristics† - Timing Characteristics- Voltages are with respect to VDD=+5V,
VEE=-7V,
VSS=0V, RL=1kΩ, CL=50pF unlesss otherwise stated. Also applicable for VEE=VSS=0, VDD=+12V.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
DATA to STROBE1 setup
tds1
20
ns
tdh1 = 20ns min.
2
DATA to STROBE1 hold
tdh1
10
ns
tds1 = 30ns min.
3
CS to STROBE1 setup
tcss1
20
ns
4
CS to STROBE1 hold
tcsh1
20
ns
5
ADDRESS to STROBE1 setup
tass1
20
ns
6
ADDRESS to STROBE1 hold
tash1
20
ns
7
STROBE1 pulse width
tspw1
75
ns
8
STROBE2 pulse width
tspw2
75
ns
9
R/W to STROBE1 setup
trwss1
20
ns
10
R/W to STROBE1 hold
trwsh1
10
ns
11
RESET pulse width
trpw
75
ns
12
CS to High Z
trpw
10
ns
13
CS to DATA output valid
tcsov
14
STROBE2 to STROBE1 setup
ts2s1
0
ns
15
STROBE1 to STROBE2 setup
ts1s2
0
ns
16
MR to switch OPEN delay
50% MR to10% Output
trst
300
ns
17
R/W to DATA output valid
trwov
150
ns
18
Address to DATA output valid
taov
200
ns
19
R/W to High Z
trwz
10
ns
20
Address to High Z
taz
10
ns
21
STROBE2 to switch status delay
50% strobe to10% output change
tstrobe2(on)
tstrobe2(off)
tson
tsoff
200
100
100
300
300
ns
ns
ns
† Timing is over recommended temperature range with VIH=5V, VIL=0V, VOH=2.4V, VOL=0.8V, RL=3kΩ (DATA) and RL=1kΩ (analog).
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
16
Zarlink Semiconductor Inc.
MT88V32
Data Sheet
CS
trpw
MR
tcss1
tcsh1
tspw1
STROBE1
tash1
tass1
ADDRESS
DATA
tds1
tdh1
trwss1
trwsh1
R/W
ts1s2
ts2s1
STROBE2
tspw2
SWITCH
STATUS
trst
tson
tsoff
on
off
Figure 14 - Write Cycle Timing Diagram
tcsov
CS
trwz
trwov
R/W
taov
taz
ADDRESS
tcsz
DATA
Data Valid
High Z
High Z
Note: STROBE1 is disabled when R/W is at logic "1".
Figure 15 - Read Cycle Timing Diagram
17
Zarlink Semiconductor Inc.
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