AN490 U SI N G I S O D R I VE R S I N I S O L A T E D S M P S , U P S , A C I N V ER T ER A N D O T HE R P O W ER S Y S T E M S 1. Introduction The Si823x ISOdriver family combines two independent, isolated drivers in a single package. The Si8230/1/3/4 versions are high-side/low-side drivers, while the Si8232/5/6 versions are dual drivers. A logic high on the IN terminal causes an RF carrier to be transmitted across the differential isolation barrier to the output-side receiver (see Figure 1), which activates the output driver pull-up transistor when sufficient in-band energy is detected. Conversely, a logic low on the IN terminal causes the receiver to activate the output driver pull-down transistor. This architecture offers the benefits of fast 60 ns maximum propagation time, low-power operation, highly stable operation across operating voltage and temperature, and no limitations to external switching device on-time (tON) or duty cycle (D). The differential isolation barrier facilitates high common-mode transient immunity (25 KV/µS). ISOdriver Channel VDD ISOLATION IN INPUT CONDITIONING + XMITTER - + RECVR DRIVER OUT - DIFFERENTIAL ISOLATION BARRIER GND Figure 1. ISOdriver Simplified Channel Diagram This application note emphasizes the power MOSFET gate drive requirements using Silicon Labs' Si823x ISOdriver in a low-side drive application. Rev. 0.1 4/10 Copyright © 2010 by Silicon Laboratories AN490 AN490 2. MOSFET Characteristics A power MOSFET switching model is shown in Figure 2a. For the following discussion, the drain and source parasitic inductances will be neglected allowing for a first-order and more intuitive model. D D Cgd D Crss D Cgd Crss G Cds Rgate_int Cgs G G Cds G Coss CHF CGS Ciss Crss Coss CHF S a) MOSFET Switching Model S S S b) MOSFET Specification Sheet Models Figure 2. Power MOSFET Switching Model As shown in Figure 2a, gate-to-drain capacitance (Cgd), gate to source capacitance (Cgs), and drain to source capacitance (Cds) are key MOSFET dynamic parameters. However, power MOSFET manufacturers data sheets specify equivalent capacitances (Ciss, Crss and Coss at given Vds_test). Figure 2b illustrates these parameters where Ciss is the total input capacitance seen at the gate with the drain and source terminals shorted together using an external high-frequency capacitor, CHF. Crss is the reverse transfer capacitance, and Coss is the common source output capacitance with Cgs shorted. Expressed in equation form: C iss = C gs + C gd ; C ds shorted Equation 1. C rss = C gd Equation 2. C oss C ds + C gd ; C gs shorted Equation 3. Note that capacitors Crss and Coss are non-linear because their values change as the inverse square-root of the applied drain-source voltage, as shown in Equation 4. 1 C oss v ds C oss v ds_test -----------v ds where V ds_test is the applied drain to source voltage used in measuring C oss. V ds_test is obtained from the power MOSFET data sheet. Equation 4. 2 Rev. 0.1 AN490 The average values of non-linear capacitors Crss and Coss must be known to calculate the required driver output current and switching losses. The average value of Coss is derived by calculating the average discharge of Coss when Vds discharges to zero (Equation 5 and Equation 6). Substituting Equation 6 into Equation 7, results in Equation 8, which gives the average value of Coss. Q av = C oss V ds_test 0 v ds 1 - dv ----------v ds Equation 5. Q av = 2 C oss V ds_test V ds Equation 6. But the average discharge is also Q av = C oss_av V ds Equation 7. Therefore the average value of Coss is V ds_test C oss_av = 2 C oss -----------------V ds Equation 8. From Equation 8, the average reverse transfer capacitance is V ds_test C rss_av = 2 C rss -----------------V ds Equation 9. From Equations 3, 8, and 9, the average drain to source capacitance is C ds_av = C oss_av – C rss_av Equation 10. Rev. 0.1 3 AN490 2.1. Power MOSFET Behavior During Turn-On Figure 3a and Figure 4 show the typical gate charge characteristics of a MOSFET throughout turn-on. The ISOdriver output stage is modeled as a pull-up/pull-down configuration (Figure 3b), with source resistances RON(SOURCE) and RON(SINK), and external bypass capacitor CBYPASS. During turn-on, the power MOSFET goes through three different gate charge periods as shown in Figure 3a. The turn-on sequence begins when the power controller asserts a logic high on the ISOdriver input, causing the (pull-up) P-channel FET to turn on, generating current flow path as shown in Figure 3b. VDDB VDDB Third Period sub1 sub2 Cbypass tdelay_on Vgs_miller Vth t(s) tMiller D Cgd Rgate G Rgate_int Cds GNDB tlinear a) MOSFET Gate Charge Characteristics b) Circulating Gate Current Figure 3. MOSFET Turn-On igate(t) VDDB/Rtotal (VDDB-Vgs_miller)/Rtotal Vgs(t) VDD Vgs_Miller Vth Tdelay T_Miller T_linear Period 3 Figure 4. igate vs. Vgate 4 RON(SOURCE) Second (Miller) Period RON(SINK) First Period Si823x Output Stage Vgs(V) Rev. 0.1 Cgs S AN490 In the first period, the Si823x ISOdriver sources current to Ciss through RON(SOURCE). Note that this period contains two sub-intervals. The first sub-interval (sub1) is referred to as turn-on delay where the gate charges to Vth (i.e. the Vgs threshold voltage of the power MOSFET). There are no switching losses during this delay time. For completeness, Equations 11 and 12 are provided to calculate the instantaneous gate charge current and time delay, tdelay(on), over sub-interval 1 respectively. –t -----------------------------V DDB R total C iss i gate t = -------------- e R total 0 t t delay_on where R total = R ON(SOURCE) + R gate + R gate_int Equation 11. V th t delay_on = – R total C iss In 1 – ------------- V DDB Equation 12. At the onset of the second sub-interval of the first period, the power MOSFET enters into the linear operation region where the drain current is proportional to Vgs, and the gate charges from Vth to Vgs-Miller. Gate-to-source voltage, Vgs-Miller, sustains load current through the power MOSFET. Time period tlinear_on, is given by Equation 13. The second sub-interval instantaneous gate charge is given by Equation 14, and the approximate average gate current is given by Equation 15. V DDB – V gs_miller t linear_on = – R total C iss ln ------------------------------------------- V DDB – V th Equation 13. –t -----------------------------V DDB R total C iss i gate t = -------------- e R total t delay_on t t delay_on + t linear_on Equation 14. i gate V gs_miller + V th V DDB – ----------------------------------------2 = --------------------------------------------------------------R total Equation 15. During the second period (also referred to as the Miller period), the ISOdriver sources current through RON(SOURCE) to discharge Crss. During this phase, the gate current and Vgs are essentially constant (Figures 3a and 4), and drain to source voltage, Vds, discharges to nearly zero volts. Gate current is calculated using Equation 16: V DDB – V gs_miller i gate = -----------------------------------------R total Equation 16. The time it takes to discharge Vds to nearly zero volts is given by Equation 17 and shown in Figure 5. Rev. 0.1 5 AN490 C rrs_av V ds_off t Miller = ---------------------------------------i gate where V ds_off is the initial voltage of V ds prior to discharge Equation 17. During the third period, the power MOSFET becomes fully enhanced (Figure 4). Note that during period 3, Vgs reaches its target value of VDDB while gate current falls to zero indicating the gate is fully charged. VDDB determines Rds(on) of the power MOSFET, and its conduction losses. 2.2. MOSFET Switching Loss During the turn_on delay time, the power MOSFET has no switching loss since there is no drain current, as illustrated in Figure 5. During the third period, there is also no switching loss since Vds is almost zero, and the MOSFET is in a static condition. However, during the second sub-interval of the first period and during the second (Miller) period, there are significant switching losses in the power MOSFET since both drain current and Vds are present. The switching loss during turn-on is given by Equation 18. P=1 --- V ds_off I load t linear + t Miller F S 2 Equation 18. Vds(t) I_drain(t) Vds_off I_Drain I_drain(t) Tdelay T_Miller Period 3 T_linear Figure 5. Switching Waveforms of Power MOSFET 6 Rev. 0.1 AN490 2.3. Using the ISOdriver The role of the MOSFET driver is crucial to circuit performance and efficiency. The driver must deliver sufficient current to minimize tlinear and tMiller. In essence, igate (Equation 16) must be sufficiently large to minimize tMiller (Equation 17). The MOSFET driver current rating must be higher than the current calculated by Equation 16. The ISOdriver current rating is measured using the Figure 23 test circuit from the Si823x ISOdriver data sheet (Figure 6), which simulates the linear and Miller periods. VDDB=12V VDDA SCHOTTKY 10O VOA INPUT 100uF 1uF Si823x GNDA 1uF CER 10uF EL RSNS 0.1 5V Figure 6. Measurement Test Circuit for ISOdriver Output Current As shown, the voltage across the output impedance of the ISOdriver is not the entire 12 V supplied by VDDB, but is reduced due to the 5 V source, which simulates Vgs during tMiller. Supplier data sheets typically list the peak current of the driver with the entire VDDB applied across the output impedance of the driver. Therefore, the peak current shown in the Si823X ISOdriver data sheet is conservative and a more useful data point to compare to the average current needed during tlinear (Equation 13) and tMiller (Equation 17). As indicated by Equation 13, Rtotal should be reduced to minimize tlinear. The minimum value of external gate resistor Rgate is dictated by the MOSFET driver current rating and by the minimum value required to damp the ringing in the gate circuitry due to Ciss and source inductance Ls. Equation 19 gives the minimum allowable value for the external series gate resistor Rgate: R gate_min = LS ---------– R ON SOURCE + R gate_int C iss Equation 19. An excessively small value of Rgate reduces switching loss but increases EMI emissions; so, a design trade-off must be made to optimize these two parameters. The Rgate power loss must be known to choose the wattage of Rgate and is calculated using Equation 20. R gate P loss_Rgate = Q gate F S V DDB -------------R total Equation 20. Rev. 0.1 7 AN490 2.4. Power MOSFET Turn-Off MOSFET turn-off begins when the power controller applies a logic low to the ISOdriver input, causing the driver output N-channel-FET to turn on, discharging the gate to GNDB through RON(SINK) (Figure 7). The power MOSFET turn-off process will not be described in detail since it is nearly identical to the turn-on process, but in the reverse order. However, there is one subtle difference: during the Miller period, the voltage across Rtotal is only Vgs_miller since RON(SINK) is pulled to GND. This may lead to reduced gate discharge current, extending tMiller and increasing switching loss during turn-off. The ISODriver’s output stage N-channel FET ensures a reduced Rtotal during turnoff, making Rtotal equal to the sum of RON(SINK), Rgate and Rgate_int. The Si823X ISOdriver has a lower resistance RON(SINK) compared to the resistance of RON(SOURCE) and, therefore, higher sink current. A diode/resistor series network can be added across Rgate if additional current is required to discharge the gate more quickly. RON(SOURCE) RON(SINK) Cbypass Si823x Output Stage VDDB D Cgd Cds Rgate G Rgate_int Cgs S GNDB Figure 7. Gate Drive Circuit and Gate Current During Turn-Off 8 Rev. 0.1 AN490 2.5. Bypass Capacitor Selection Gate to Source Voltage Vgs The bypass capacitor supplies the charge required to turn on the MOSFET, and its value is dependent on the MOSFET gate charge at VDDB and the desired bypass capacitor ripple voltage. The MOSFET gate charge is readily available in MOSFET data sheets. A typical gate charge (QG) versus Vgs is again shown in Figure 8. (V) VDDB Gate Charge Qg (nC) Qg at VDDB Figure 8. Gate Charge vs. Vgs Used for Determining Qg The value of the bypass capacitor is predicated mostly on the acceptable level of ripple. A peak-to-peak ripple voltage that is 5% of VDDB is reasonable. V = 0.05 VDDB Equation 21. Q gate + IDDB Q D max T C bypass = ----------------------------------------------------------------------------V where IDDB(Q) is the quiescent supply current into pin VDDB of the Si823xISODriver. Dmax is the maximum duty cycle of the power MOSFET, and T is the switching period. Equation 22. Ceramic capacitors are highly recommended because of their excellent low impedance and high ripple current characteristics. Furthermore, they are cost effective and are physically small. However, ceramic caps suffer from dc-bias and temperature dependency; it is therefore recommended to use a higher value than the one called for by Equation 22. It is also recommended to use X5R and X7R type ceramic caps and the Y5V type. As stated at the beginning of this application note, the discussion thus far assumed low-side drive. Note that other considerations must be taken into account in a high-side drive application. This topic is covered in Silicon Lab's application note AN486 "High-Side Bootstrap Design ". Rev. 0.1 9 AN490 2.6. Low-Side Driver Design Example Given: VDDB = 12 V High-side MOSFET QG = 85nC @ VDDB=12V IDDB(IQ) = 3 mA from Si823x data sheet = IDDBQ FPWM = 200 kHz, D = 10% to 90%. The design begins with the calculation of the total charge (the numerator of Equation 22) that must be delivered by CBYPASS at maximum duty cycle. Q bypass = Q G + IDDB Q D max T = 85 10 –9 –3 –6 + 3 0.9 5 = 99nC where IDDB Q is the quiescent supply current of the ISOdriver VDDB input Equation 23. The total charge that CBYPASS must deliver is 99nC. The value of CBYPASS is driven by the maximum allowable ripple (V), and is calculated using Equations 21 and 22. 99nC C bypass = -----------------------0.05 12 = 0.165 F C bypass = 0.165 F Since ceramic caps are dc-bias- and temperature-dependent, use a 0.33 µF X5R or X7R ceramic cap. 2.7. Layout Due to high circulating currents and fast transitions in the gate drive circuitry, proper trace routing and component placement are required for gate drive signal integrity. Figure 9 shows the gate's circulating current path during turnon of the power MOSFET. The area enclosed by the current loop should be made as small as possible to minimize ringing and radiated EMI. This can be accomplished using a low-impedance ground plane. To minimize loop inductance, the most direct connection possible must be made between the MOSFET source terminal and the ground plane. If vias are used, it is important that the MOSFET source terminal connection to ground be implemented with multiple vias, depending on the drain current ID. A rule of thumb is to use one via per amp with a minimum drill size of 31 mils. VDDB VDDB Rgate Rgate VOB VOB Cbypass Cbypass Si823x GNDB Source Terminal Si823x GNDB b) Loop Area of Turn-Off igate a) Loop Area of Turn-On igate Figure 9. Loop Area of igate Turn-On and Turn-Off 10 Rev. 0.1 Source Terminal AN490 The bypass capacitor should be placed as close to the Si823x VDDB and GNDB pins as possible, and routed directly using a trace having a minimum thickness of 24 mils. The bypass capacitor can be connected to the ground plane (instead of the GNDB pin) using a single large via with a minimum drill size of 31 mils. If a single via is used to connect the GNDB pin to the ground plane, a minimum drill size of 31 mils should be used. The high-side ISOdriver also has fast and high current circulating in its output circuitry during power MOSFET switching. The VDDA bypass capacitor must be placed as close as possible to pins VDDA and GNDA of the Si823x and routed directly to them. A ground plane cannot be used for a high-side ISOdriver. GNDA pin should be connected directly to the terminal source terminal of the power MOSFET. This trace should be routed in parallel (and as close as possible) to the trace connecting Rgate to the ISOdriver output. This keeps the loop area to a minimum as shown in Figure 10. The trace should be at least 24 mils thick. VDDA Rgate VOA Cbypass Si823x Small Area Source Terminal GNDA Figure 10. Routing Output of ISOdriver to High-Side MOSFET Rev. 0.1 11 AN490 3. Conclusion In addition to providing isolation rated as high as 5 kVrms and 60 ns maximum propagation delay times, the Si823X is a versatile IGBT/ MOSFET driver that can efficiently drive power MOSFETs or IGBTs in a wide variety of power delivery systems. Example systems include isolated dc/dc and ac/dc power supplies, UPS systems, AC inverters, and electronic lighting ballasts among others. Furthermore, the high-side/low-side versions have built-in programmable dead-time delays for protection against overlap timing, ensuring safe and efficient operation. The ISOdriver family provides flexibility and performance to ensure optimum system operation and reliability. 4. Related Documents Silicon Labs Si823x ISOdriver data sheet Silicon Labs Application Note: “AN486: High-Side Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems” Silicon Labs Application Note: “AN441: Using the Si8232/5/6 Dual ISODrivers” 12 Rev. 0.1 AN490 NOTES: Rev. 0.1 13 AN490 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 14 Rev. 0.1

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