TN-41-15: DDR3 VOL/VOH Specifications

TN-41-15: DDR3 VOL/VOH Specifications
Introduction
Technical Note
DDR3 SDRAM VOL and VOH Specifications
Introduction
This technical note describes the proper interpretation and use of V OL and V OH specifications for DDR3 SDRAM, including:
• AC/DC conditions, including single-ended AC/DC output levels
• AC timing and slew rate load, including the value of RON and equations for calculating
RON(PU) and RON(PD)
• Output driver DC linearity, including 34Ω output driver DC electrical characteristics
• Defining system V OL and V OH
• Calculating system V OL and V OH
• VOL and V OH will vary depending on system/application loading.
This technical note references JEDEC document JESD79-3F and Micron DDR3 SDRAM
data sheet specifications.
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tn-41-15_ddr3_vol_voh_specs.pdf - Rev. A 07/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
TN-41-15: DDR3 VOL/VOH Specifications
DDR3 SDRAM VOL/VOH Specifications
DDR3 SDRAM VOL/VOH Specifications
AC and DC Conditions
The DDR3 SDRAM data sheet shows two specific use conditions V OL and V OH are defined for:
• AC Condition – A special condition to check the driver characteristic slew rate with a
specific load. This condition is not a pass/fail condition and must be derated if it is
being compared to a non-JEDEC test load condition. The original JEDEC specification
used a 40Ω load, but it has been changed to 34Ω.
• DC Condition – A measurement only for the current-voltage (I-V) linearity curve. It is
not a system-level measurement; it is a reference point only.
Table 1: Single-Ended AC/DC Output Levels
Symbol
Parameter
DDR3-800, 1066, 1333,
1600
Unit
V
Notes
VOH(DC)
DC output HIGH measurement level (I-V curve linearity)
0.8 × VDDQ
VOM(DC)
DC output mid-measurement level (I-V curve linearity)
0.5 × VDDQ
V
VOL(DC)
DC output LOW measurement level (I-V curve linearity)
0.2 × VDDQ
V
VOH(AC)
AC output HIGH measurement level (output slew rate)
VTT + 0.1 × VDDQ
V
1
VOL(AC)
AC output LOW measurement level (output slew rate)
VTT - 0.1 × VDDQ
V
1
Note:
1. The swing of ±0.1 × VDDQ is based on approximately 50% of the static, single-ended output HIGH or LOW swing with a driver impedance of 40Ω, and an effective test load of
25Ω to VTT = VDDQ/2. See figure: Reference Load for AC Timing and Output Slew Rate.
Figure 1: Reference Load for AC Timing and Output Slew Rate
VDDQ
DUT
CK, CK#
RTT = 25Ω
DQ, DM
DQS, DQS#
Reference
point
Note:
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VTT = VDDQ/2
Reference
point
1. This figure represents the effective reference load of 25Ω used in defining the relevant
AC timing parameters of the device as well as output slew rate measurements. It is not
intended to be a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use
IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, which generally consist of one or more coaxial transmission lines terminated at the tester electronics.
2
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TN-41-15: DDR3 VOL/VOH Specifications
DDR3 SDRAM VOL/VOH Specifications
AC Timing and Slew Rate Load
All timings and slew rate measurements are referenced to an output driver impedance
of 34Ω.
Note: Originally, JEDEC specified the default output driver impedance as 40Ω, but it has
been changed to 34Ω.
Output driver impedance (RON) is defined by the value of the external reference resistor
RZQ (RZQ = 240Ω nominal):
RON(34) = RZQ/7 = 34.3Ω ±10% nominal.
The individual pull-up and pull-down resistors are defined as follows:
RON(PU) = (VDDQ - V OUT)/|IOUT|, when RON(PD) is turned off
RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 2: Output Driver Voltages and Currents
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RON(PU)
DQ
IOUT
RON(PD)
VOUT
IPD
VSSQ
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TN-41-15: DDR3 VOL/VOH Specifications
DDR3 SDRAM VOL/VOH Specifications
Table 2: Output Slew Rate – Single-Ended
RON = RZQ/7
DDR3-800
DDR3-1066 DDR3-1333 DDR3-1600
DDR3-1866
DDR3-2133
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Singleended output slew
rate
SRQse(1)
2.5
5
2.5
5
2.5
5
2.5
5
2.5
5(2)
2.5
5(2)
V/ns
1. SR = Slew rate; Q = Query output; se = Single-ended signals.
2. In two cases, a maximum slew rate of 6 V/ns applies for a single DQ signal within a byte
lane.
Case 1 – Defined for a single DQ signal within a byte lane that is switching to a certain
direction (from HIGH to LOW or LOW to HIGH), while all remaining DQ signals in the
same byte lane are static (i.e., they stay HIGH or LOW).
Case 2 – Defined for a single DQ signal within a byte lane that is switching to a certain
direction (from HIGH to LOW or LOW to HIGH), while all remaining DQ signals in the
same byte lane are switching to the opposite direction (i.e., from LOW to HIGH or HIGH
to LOW, respectively). For the remaining DQ signal switching to the opposite direction,
the regular maximum limit of 5 V/ns applies.
Notes:
Output Driver DC Linearity
Output linearity is not tested under system load conditions. The output driver's current
is measured to the reference load in the data sheet. The output current is measured at
defined V OL/VOH test points. V OL(DC) and V OH(DC) describe these reference points.
Note: VOL(DC) and V OH(DC) are not test conditions. Output current is measured at V OL(DC)
and V OH(DC) test points for verification of output drive and linearity.
Table 3: 34Ω Output Driver DC Electrical Characteristics
RON(NOM)
Resistor
VOUT
Min
Nom
Max
Unit
Notes
34Ω
RON34(PD)
VOL(DC) = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
VOM(DC) = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOH(DC) = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
RON34(PU)
Pull-up/pull-down mismatch
(MMPUPD)
Notes:
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VOL(DC) = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
VOM(DC) = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOH(DC) = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
VOM(DC) = 0.5 × VDDQ
–10
N/A
10
%
1, 2, 4
1. Tolerance limits assume RZQ = 240Ω ±1% and are applicable after proper ZQ calibration
has been performed at a stable temperature and voltage. Refer to the Output Driver
Sensitivity section if either the temperature or the voltage changes after calibration.
2. Tolerance limits are specified under the following conditions: VDDQ = VDD; VSSQ = VSS.
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at
0.5 × VDDQ. Other calibration schemes may be used to achieve the linearity specification
above (calibration at 0.2 × VDDQ and 0.8 × VDDQ).
4
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TN-41-15: DDR3 VOL/VOH Specifications
DDR3 SDRAM VOL/VOH Specifications
4. Equation for mismatch between pull-up and pull-down (MMPUPD); measure both RON(PU)
and RON(PD) at 0.5 × VDDQ:
RON(PU) - RON(PD)
MMPUPD =
× 100
RON,nom
Defining System VOL and VOH
The SDRAM is not required to achieve the V OL and V OHvalues stated in the data sheet.
Actual system V OL and V OH are determined by the output drive from SDRAM, coupled
with the load being driven. System V OL and V OH are usage conditions, not DDR3
SDRAM specifications. Those values are determined by R ONdrive and ODT or the load
being driven.
Calculating System VOL and VOH
System V OL and V OH can be estimated using worst-case values:
RON = Largest value; ODT = Smallest value
RON(max) = 34.3Ω x 1.11 = 38Ω (properly calibrated; no V/T shift)
ODT60(min) = 60Ω x 0.59 = 35Ω (properly calibrated; no V/T shift)
If V DDQ = 1.5V and V SS = 0.0V (ideal values):
Expected V OL = ~390mV (0.26VDDQ, which is >0.2VDDQ)
Expected V OH = ~1.11V (0.74VDDQ, which is <0.8VDDQ)
As noted, values are different from the limits stated in the data sheet.
Figure 3: VOL Schematics
VDDQ
0.5(VDDQ)
VDDQ
ODT
(or equivalent RLOAD)
RPU
34W
RON
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34W
RON
RPD
VOL = (0.5 × VDDQ) - VSS ×
0.5(VDDQ)
34W
(34W + ODT)
5
+ VSS
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© 2013 Micron Technology, Inc. All rights reserved.
TN-41-15: DDR3 VOL/VOH Specifications
Conclusion
Figure 4: VOH Schematics
VDDQ
34W
RON
VDDQ
VDDQ
34W
RON
RPU
ODT
(or equivalent RLOAD)
RPD
0.5(VDDQ)
VOH = VDDQ -
34W
× (VDDQ - (0.5 × VDDQ))
(34W + ODT)
Conclusion
Data sheet parameters V OL(DC) and V OH(DC) are reference points to which DDR3 SDRAM
output driver currents are measured to confirm driver linearity. There is no specified
test condition or specification requirement related to those two parameters.
System V OL and V OH are system-dependent, and the data sheet parameters V OL(DC) and
VOH(DC) cannot be applied to DDR3 SDRAM system performance. A V OL that is too high
or a V OH that is too low indicates a violation of the DDR3 SDRAM specification. This can
happen if RON impedance is too low or if ODT impedance is too high.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
TN-41-15: DDR3 VOL/VOH Specifications
Revision History
Revision History
Rev. A – 07/13
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef8547ae28
tn-41-15_ddr3_vol_voh_specs.pdf - Rev. A 07/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.