AN-1291 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Digital Potentiometers: Frequently Asked Questions This application note answers a series of frequently asked questions (FAQs) about digital potentiometer products from Analog Devices, Inc. It includes general and specific questions, including product specific questions. In addition, it provides digital potentiometer configuration information. Rheostat mode has Terminal W hardwired to either Terminal A or Terminal B (see Figure 2). Some devices offer only two terminals: Terminal A and Terminal W. A W B Q: What is a digital potentiometer? A: A digital potentiometer is a digitally controlled resistor that changes the impedance between the terminals and the wiper depending on the code loaded in the RDAC register. Digital potentiometers avoid the problems that mechanical potentiometers face, such as physical size and wear and tear, as well as sensitivity to vibration, temperature, and humidity. A digital potentiometer can be configured in two different modes: potentiometer mode and rheostat mode. Potentiometer mode (see Figure 1) has three terminals: Terminal A, Terminal B, and Terminal W (wiper). A B 12052-001 W A W B 12052-002 INTRODUCTION Figure 2. Rheostat Mode Q: Where do I find the evaluation tools and software pertaining to the evaluation board? A: The Windows®-compatible evaluation software and the driver software are included on a CD that comes with the evaluation board kit. For newer products, the evaluation software and the driver software information is available on the product page of the Analog Devices website. Q: How can I obtain digital potentiometer technical support? A: EngineerZone is an Analog Devices online support community with support for the digital potentiometer available in the Precision DACs community. Customers from all over the world can post questions, view existing questions and answers, and review and contribute to ongoing discussions in this community. Figure 1. Potentiometer Mode Rev. A | Page 1 of 18 AN-1291 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Interfacing ................................................................................... 10 Revision History ............................................................................... 2 Gain .............................................................................................. 12 Digital Potentiometer FAQs by Category ...................................... 3 LED Driver .................................................................................. 13 General FAQs ................................................................................ 3 Voltage to Current Conversion................................................. 14 FAQs About Digital Potentiometers with EEPROM Memory.... 7 Filtering........................................................................................ 15 Circuit References............................................................................. 8 Other Usage Examples ............................................................... 17 Audio .............................................................................................. 8 REVISION HISTORY 3/15—Rev. 0 to Rev. A Updated Layout ................................................................... Universal Changes to Introduction Section.................................................... 1 Changes to General FAQs Section ................................................. 3 Changes to FAQs About Digital Potentiometers with EEPROM Memory Section................................................................................ 7 Changed Applications Information Section to Circuit References Section ............................................................................ 8 Changes to Audio Section and Figure 8 ........................................ 8 Changes to Figure 9 and Audio Volume Control Section ........... 9 Changes to Figure 11, Interfacing Section, and LCD Panel VCOM Adjustment Section .............................................................. 10 Changes to Manual Control with Rotary Encoder Section ...... 11 Changes to Multiple Devices on One I2C Bus Section, Level Shifting for Bidirectional Interface Section, and Gain Section ....... 12 Changes to Linear Gain Setting Mode Section........................... 13 Deleted Bipolar Programmable Gain Amplifier Section, Figure 18, and Table 3; Renumbered Sequentially........................................ 13 Changed Voltage to Current Conversion: Programmable Current Source Section to Programmable Current Source Section ....... 14 Changes to Programmable Current Source Section and Figure 21 .......................................................................................... 14 Changed Voltage to Current Conversion: Programmable Bidirectional Current Source Section to Programmable Bidirectional Current Source Section .......................................... 15 Changes to Programmable Bidirectional Current Source Section and Programmable Low-Pass Filter Section ............................... 15 Changes to Programmable State Variable Filter Section and Figure 24 .......................................................................................... 16 Changed Miscellaneous Section to Other Usage Examples Section.............................................................................................. 17 Changes to Programmable Oscillator Section ............................ 17 5/14—Revision 0: Initial Version Rev. A | Page 2 of 18 Application Note AN-1291 DIGITAL POTENTIOMETER FAQs BY CATEGORY Q: Why replace a mechanical potentiometer with a digital potentiometer? GENERAL FAQs Q: Is there a recommended power-up sequence? A: Yes. The relevant product data sheet provides a recommended start-up sequence to refer to before powering up the device. Generally, it is good practice to power the VDD pin first and the VSS pin second. The order of the voltages at Terminal A, Terminal B, and Terminal W (VA, VB, and VW, respectively) is not important, but power these last. There are ESD protection diodes between the VDD pin and Terminal A, Terminal B, and Terminal W. For example, the cathode of one of the diodes connects to the VDD pin and the anode connects to Terminal A. As a result, any voltage occurring at Terminal A before the VDD pin forward biases the diode and powers the VDD pin. For some of the digital potentiometers, power the digital signals after the VDD pin. This power sequence is documented in the relevant product data sheet. Q: Are all digital potentiometers limited to |5 V|? A: No. A wide portfolio of digital potentiometers are available to handle large unipolar and bipolar power supplies. See the Choosing the Correct digiPot for Your Application online brochure for an up to date product list. Q: Do digital potentiometers handle bipolar and ac operations? A: Yes. Analog Devices offers digital potentiometers with dual ±2.5 V, ±5 V, or ±15 V supplies that can handle bipolar or ac operation. The user can still achieve ac operation with a single dc supply by raising the dc offset. Terminal A, Terminal B, and Terminal W have no polarity constraints with respect to one another. Q: For dual-supply digital potentiometers, if VDD and VSS are +2.5 V and −2.5 V, respectively, can digital inputs be fed from a standard 3.3 V complementary metal-oxide semiconductor (CMOS) logic component without logic level translation? What are the logic level thresholds when VDD is +2.5 V and VSS is −2.5 V? A: When using a bipolar ±2.5 V digital potentiometer, the maximum digital supply is limited to VDD + 0.3 V or VLOGIC + 0.3 V. Otherwise, the internal protection diodes clamp the voltage and are damaged. See the relevant product data sheet for more details on digital potentiometer levels. Q: Is there a dependency between the logic level and power consumption? A: Yes. If the logic level is lower than the logic supply (VDD or VLOGIC, if available), the input gates do not switch completely and the device consumes more power. A: There are a few advantages to using a digital potentiometer vs. a mechanical potentiometer, namely • • • • • • Higher resolution More reliability Better stability Faster adjustment More functions Better dynamic control However, a digital potentiometer is not a direct replacement for a mechanical potentiometer. See the Is a digital potentiometer a real replacement for a mechanical potentiometer, or are there restrictions regarding voltage potentials? question for more information. Q: Is a digital potentiometer a real replacement for a mechanical potentiometer or are there restrictions regarding voltage potentials? A: A digital potentiometer is not an exact replacement for a mechanical potentiometer. VA and VB must not be greater than VDD or less than VSS (or GND if the device does not have a VSS pin). For example, if the desired VA and VB are +2 V and −2 V, respectively, VDD must be less than, or equal to, +2 V, and VSS must be greater than, or equal to, −2 V. See the AN-1121 Application Note, Replacing Mechanical Potentiometers with Digital Potentiometers, for more information on this topic. Q: For digital potentiometers without nonvolatile memory, what is the state during power-up? A: Most Analog Devices digital potentiometers (with the notable exception of the AD8400/AD8402/AD8403) contain power-on reset (POR) circuitry, which presets the wiper to terminal resistance to the middle value of the terminal to terminal resistance. For example, if the end to end resistance (RAB) = 10 kΩ, at power-up, RWB = RWA = 5 kΩ, where RWB is the resistance between Terminal W and Terminal B and RWA is the resistance between Terminal W and Terminal A. For the digital potentiometers that do not have this feature, the wiper to terminal resistance can be anything at power-up. See the relevant product data sheet for more details. Q: Is there a particularly low power digital potentiometer? A: Yes. The AD5165 is an Analog Devices product that offers ultralow power consumption. The Choosing the Correct digiPot for Your Application online brochure provides an up to date product list. Rev. A | Page 3 of 18 AN-1291 Application Note Q: Does the memory allow the device to return to the last stored value without an update from a microprocessor? A: Yes. The device is automatically set to the previously stored value each time the device is powered on. By default, the EEPROM is factory programmed to midscale. Q: How good is the resistance matching between Channel 1 (Ch1) and Channel 2 (Ch2) in a dual digital potentiometer? Q: What is the maximum current I can force into the digital potentiometer? A: The matching is typically within 0.1% to 0.2% and ±1% is specified as a maximum mismatch. See the relevant product data sheet for more information. A: The maximum current is limited by three boundaries at a given resistance setting. The three boundaries are the maximum applied voltage across any two of Terminal A, Terminal B, or Terminal W, the power dissipation of the package, and the maximum current handling capabilities of the internal switches. Q: How is the resistance matching, device to device? A: Assuming the devices come from the same batch, the resistance matching, device to device, is within ±1%. Q: What is the resistance tolerance of digital potentiometers? A: See the relevant product data sheet for an exact figure. If using the potentiometer in the 3-terminal potentiometer mode (without any series resistor), the tolerance is irrelevant because the resistances, RWA and RWB, are ratiometric. If using the potentiometer in the 2-terminal rheostat mode, account for the worst-case variation. On some nonvolatile digital potentiometers, resistance tolerance is stored in the memory at the factory with an accuracy of 0.1%. Thus, users can retrieve the resistance tolerance and calibrate the system accordingly. Q: Can I cascade, serialize, or parallel multiple digital potentiometers to get the resistance or resolution needed? My requirement is for a 250 Ω digital potentiometer with approximately 1 Ω per step. I plan to use four 1 kΩ AD8403 devices in parallel with each set to nominally the same value. A: Yes. See the AN-582 Application Note, Resolution Enhancements of Digital Potentiometers with Multiple Devices, for more information. Q: How is a digital potentiometer designed? How ideal are the wiper switches? A: A digital potentiometer is purely a CMOS device. All switches are large, CMOS transmission gates operated in the linear region to yield low, uniform on resistance of the CMOS (RDS(ON)). All resistor elements are polysilicon or thin film resistors. Q: What is the temperature coefficient (TC) of the digital potentiometer? RS = RAB 2N Each digital potentiometer data sheet refers to this maximum current in the Absolute Maximum Ratings section (see Table 1 for an example). Table 1. Maximum Current Through Digital Potentiometer Terminal: Absolute Maximum Ratings Table Example Parameter IA, IB, IW Pulsed Frequency > 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Frequency ≤ 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Continuous RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ 1 Rating ±6 mA/d1 ±1.5 mA/d1 ±6 mA/√d1 ±1.5 mA/√d1 ±6 mA ±1.5 mA Note that d is the pulse duty factor. Calculating the pulsed current is dependent on the frequency. If the frequency is less than or equal to 10 kHz, the formula is as follows: ID = IPEAK × √d where: ID is the maximum dc current. IPEAK is the maximum peak current value for waveform. d is the duty factor (0.1 = 10% duty cycle). If the frequency is greater than 10 kHz, the formula is as follows: A: Two components make up the resistance at any given setting: the polysilicon or thin film resistors (step resistor, RS), and the CMOS switch resistor (RSW = 50 Ω at 5 V supply). Together, these components add up such that RWB = RS + RSW The TC of the step resistor, which is published in the relevant product data sheet, is typically −35 ppm/°C for thin film resistors or 600 ppm/°C for polysilicon. The resistance of the switch, on the other hand, doubles at 100°C. As a result, the overall TC is nonlinear and it is worse off at low value codes where the switch resistance dominates. See the TC graphs in the relevant product data sheet for more detailed information. ID = IPEAK × d Q: Do Analog Devices digital potentiometers suffer from leakage currents, which could affect the gain of the circuit? A: Analog Devices digital potentiometers are manufactured with a very low leakage analog switch process, which results in low leakage currents. Digital potentiometers are usually specified with a typical common-mode leakage current of 1 nA. where N is the number of bits of the digital potentiometer. Rev. A | Page 4 of 18 Application Note AN-1291 Q: Regarding the specification on resistor differential nonlinearity (R-DNL), I am concerned only with relative adjustments. What if I am not concerned with the actual value of the resistor in the digital potentiometer, but need it to be monotonic? A: For a digital potentiometer that is in rheostat mode, there are two specifications known as resistor integral nonlinearity (R-INL) and R-DNL, respectively. INL is the maximum deviation between the ideal output of a digital-to-analog converter (DAC) and the actual output level. R-INL is the deviation from an ideal value measured between the maximum resistance wiper position and the minimum resistance wiper position. DNL is the maximum deviation between two consecutive codes over the DAC transfer function. R-DNL measures the relative step change from the ideal between successive tap positions. VW2 12052-005 VW1 Figure 4. Digital Step Response Crosstalk All Analog Devices digital potentiometers are guaranteed monotonic. Q: What is digital feedthrough? Q: Is there analog crosstalk between Ch1 and Ch2 of a dual digital potentiometer such that a sine wave applied to Ch1 occurs in Ch2 as well? A: Digital feedthrough is the amount of noise from clock or data coupled into the output. It is usually very small (low nV/sec range). Figure 5 shows an example of digital feedthrough. A: Yes. The relevant product data sheet details such performance. The performance is typically specified at −70 dB. Figure 3 is an example of analog crosstalk. VW VW2 12052-006 SCL 12052-004 VW1 Figure 5. Digital Feedthrough Q: How is the total harmonic distortion (THD) performance of the digital potentiometer? Figure 3. Analog Crosstalk Q: If Ch1 is programmed from zero to full scale, should the user expect Ch2 to be disturbed? A: This process is digital step response crosstalk, which is different from analog crosstalk, and the relevant product data sheet details this information. Digital step response crosstalk is typically in the range of 5 nV/sec to 10 nV/sec. Figure 4 shows an example of digital crosstalk. A: THD performance is dependent on both code and VDD. Typically, THD performance is in the range of −86.02 dB to −60 dB, but see the relevant product data sheet for specific performance. The best THD performance is achieved when the device operates at its maximum operating voltage. THD is also dependent on the end to end resistance. A higher end to end resistance yields better THD values, but reduces the −3 dB bandwidth. See the dynamic characteristics in the relevant product data sheet for more information. Rev. A | Page 5 of 18 AN-1291 Application Note Q: Can the wiper setting of digital potentiometers be read back? How about the contents of two RDAC registers of dual I2Ccompatible digital potentiometers, such as the AD5242 and AD5282? Q: How can I control a digital potentiometer that requires a 6-bit word length using an 8-bit word length from my controller? A: Serial peripheral interface (SPI) digital potentiometers operate by disregarding the first MSBs and reading the next six bits. See the relevant product data sheet for more information. A: Yes. The user can read back the wiper setting with some digital potentiometers. Q: How can I control a digital potentiometer that requires a 12-bit word length using an 8-bit word length from my controller? The user can also read back the RDAC register content (the RDAC address value of a specific channel); however, the user can only read the RDAC channel selected during the previous write mode. If the channel the user wants to read is different from the channel previously written to, a dummy write command is necessary to select the desired channel. Refer to the relevant product data sheet for details. A: Issue a 2-byte word. The first four MSBs are disregarded. See the relevant product data sheet for more information. Q: How can multiple digital potentiometers be daisy-chained? A: To daisy-chain digital potentiometers, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased due to propagation delay. Q: Is there a digital potentiometer controlled by a parallel input? In Figure 6, two AD5122/AD5142 digital potentiometers (U1 and U2) are tied together. In this setup, 32 bits are required. The first 16 bits are sent to U2 and the second 16 bits are sent to U1. During this 32-bit write, the SYNC pin remains low. A: No. Q: What are the WP pin, the PR pin, and the RDY pin features? A: The WP pin stands for write protect. For example, on the ADN2850, the WP pin disables any changes to the scratchpad register contents. A scratchpad register directly controls the digital resistor wiper and has no limit on the number of changes it can make (unlike the EEPROM, which has a limit on the number of writes). After all bits are clocked in, the SYNC pin is pulled high to complete the write. The AD5144 and similar SPI devices include internal counters to prevent data corruption due to noise. If the number of clocks is different from expected, the data is ignored. When the SYNC pin is high, the counter resets. See the relevant product data sheet for more information. However, commands that restore the wiper position using the EEPROM are allowed. Therefore, the WP pin is used as a method of protecting the EEPROM contents. Q: Can I program two channels of a multichannel digital potentiometer at the same time? In addition, on the ADN2850, the hardware override preset (PR) pin can be used to overwrite the scratchpad register with the EEPROM contents. A: Yes. With some digital potentiometers, such as the AD5251/ AD5252/AD5253/AD5254 and the AD5232/AD5233/AD5235, the user can increment and decrement all the channels simultaneously. In addition, the user can write to each electronically erasable memory (EEMEM) and then issue a reset command to update all the RDAC register settings simultaneously. The RDY pin signifies when commands have been completed, thus indicating readiness for the next command. See the relevant product data sheet for more information. Some products, such as the AD5144, include an LRDAC pin (for loading the RDAC input register), which transfers data from the input register to the RDAC register and updates the wiper position. A user can update either a single RDAC register or all RDAC registers at once. Q: What is the ESD rating of digital potentiometers? A: All digital potentiometers have ESD ratings higher than 1 kV. See the relevant product data sheet for more information. VLOGIC AD5122/ AD5142 MOSI SDI U1 RP 2.2kΩ SDO VLOGIC AD5122/ AD5142 SDI RP 2.2kΩ U2 SDO SCLK SYNC Figure 6. Daisy-Chaining Digital Potentiometers Rev. A | Page 6 of 18 SCLK 12052-007 SYNC DAISY CHAIN MICROCONTROLLER MISO SCLK SS Application Note AN-1291 Q: How can I determine the RAB value on the digital potentiometer package? A: The ordering guide section of each data sheet includes a model number and, for smaller packages, a branding code. For example, the AD8400 uses an SOIC package, which is branded with AD8400AR1, AD8400AR10, or AD8400AR100, and represents an RAB of 1 kΩ, 10 kΩ, or 100 kΩ, respectively. With the more compact packages, three letter codes are used. Using the branding code in the relevant data sheet helps determine the RAB. For other operating temperatures, see Figure 7. As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit before data retention is characterized. This cycling means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Note that retention lifetime, based on an activation energy of 0.7 eV, derates with TJ. This data applies to all nonvolatile memory digital potentiometers. 300 FAQs ABOUT DIGITAL POTENTIOMETERS WITH EEPROM MEMORY Measured as retention time, the discharge is extrapolated using a model defined in the “Experimental and Theoretical Investigation of Nonvolatile Memory Data-Retention” IEEE article. t R = t0 ANALOG DEVICES TYPICAL PERFORMANCE AT TJ = 55°C 150 100 50 Ea × e kT where: tR is retention time based on temperature. t0 is retention time corresponding to an infinite temperature. Ea is activation energy. k is Boltzmann’s constant. T is temperature. 200 0 40 50 60 70 80 90 100 TJ JUNCTION TEMPERATURE (°C) 110 12052-008 A: Yes. The EEPROM cells lose their charge over a period of 15 years when operating at 55°C. RETENTION (Years) 250 Q: Will the data in the EEMEM need to be refreshed after 15 years when it is operated at 55°C? Figure 7. Example of Data Retention vs. Temperature Q: After the specified EEMEM data retention timeout period, can the power be turned off and then back on so that the device is considered refreshed? A: No. Doing so refreshes only the RDAC register, not the EEPROM. The data must be reloaded again after 15 years to put a fresh charge into the EEPROM cell. The data is reloaded by writing the RDAC wiper register data back to the EEPROM before the end of 15 years. Q: Why is the maximum operating temperature for some digital potentiometers only 85°C instead of the standard 125°C? A: Digital potentiometers that contain EEPROMs have a maximum operating temperature of up to 85°C because EEPROMs are guaranteed to safely operate below 85°C only. Rev. A | Page 7 of 18 AN-1291 Application Note CIRCUIT REFERENCES AUDIO Q: Can digital potentiometers do log taper adjustments? Q: If I use the digital potentiometer in audio volume control, will I experience zipper noise? A: Pseudolog taper adjustment is preferred in applications such as audio control. The answer, however, is yes for AD5231/ AD5232/AD5233/AD5235 or ADN2850 users. Additionally, a pseudolog taper adjustment is possible in other linear adjustment potentiometers with a simple configuration. For more information, see the “Tack a Log Taper onto a Digital Potentiometer” EDN Network article published by Hank Zumbahlen in January 2000. A: There is noticeable zipper noise; however, a logarithmic audio volume control circuit with glitch reduction (developed by Analog Devices using the AD5292 digital potentiometer) is available (see Figure 8). See the AN-1209 Application Note, Logarithmic Audio Volume Control with Glitch Reduction Using the AD5292 Digital Potentiometer for more information. V+ +15V U1A VCC +3.3V 0V ±14V 1/2 AD8676 100kΩ R1 100kΩ ±0.1% V– –15V R4 90.9kΩ ±0.1% +1.657V 0.0133V R2 806Ω ±0.1% +3.3V VCC ADCMP371 GND – +3.3V R6 27.4kΩ ±0.1% U2 V+ +1.81V AD8541 V– +1.643V R7 33.2kΩ ±0.1% A U3 +1.645V ±1.4V R5 9.09kΩ ±0.1% +3.3V VDD +15V U6 AD5292 SERIAL INTERFACE +3.3V U5A 1/2 7408 U4 VCC ADCMP371 GND – R3 100kΩ ±0.1% U5B 2/2 7408 U1B W RAB 20kΩ 2/2 VOUT AD8676 SYNC R8 20kΩ B SYNC VSS –15V Figure 8. Logarithmic Audio Volume Control with Glitch Reduction (Simplified Schematic: Decoupling; All Connections Not Shown) Rev. A | Page 8 of 18 12052-010 C1 VIN 100nF Application Note AN-1291 C1 1µF +5V R1 100kΩ V+ R4 90kΩ C2 0.1µF ADCMP371 V– V+ +5V U3 ADCMP371 V– U6 V+ AD8541 V– 7408 5 6 1 AD7376 +15V U4A W 100kΩ 7408 2 CS CLK CLK SDI SDI CS R3 100Ω A VSS –15V U4B 4 +5V R5 10kΩ VDD C3 0.1µF U2 R2 200Ω U1 +15V +5V U5 V+ VOUT V– B –15V GND 12052-023 VIN Figure 9. Audio Volume Control Audio Volume Control Because of its good THD performance and high voltage capability, the AD7376 can be used for digital volume control. If the AD7376 is used directly as an audio attenuator or gain amplifier, a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector is inserted into the CS line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc levels rather than absolute zero volt level, zero crossing, in this case, means the signal is ac-coupled and the dc offset level is the signal zero reference point. The configuration to reduce zipper noise and the result of using this configuration are shown in Figure 9 and Figure 10, respectively. The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by the two ADCMP371 devices (U2 and U3) and two 7408 AND logic gates (U4A and U4B). The AD8541 (U6) is used to establish the signal zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND’ed with the chip select signal such that the AD7376 updates whenever the signal crosses the window. To avoid constant update of the device, the chip select signal is programmed as two pulses rather than the one shown in the AD7376 data sheet. 1 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p 12052-135 2 NOTES 1. THE LOWER TRACE SHOWS THAT THE VOLUME LEVEL CHANGES FROM QUARTER SCALE TO FULL SCALE, WITH THE CHANGE OCCURRING NEAR THE ZERO-CROSSING WINDOW. Figure 10. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 9 Audio Amplifier with Volume Control The AD5228 and the SSM2211 can form a 1.5 W audio amplifier with volume control that has adequate power and quality for portable devices, such as PDAs and cell phones. The SSM2211 can drive a single speaker differentially between Pin 5 and Pin 8 without any output capacitor. The high-pass cutoff frequency is as follows: In Figure 10, the lower trace shows that the volume level changes from a quarter scale to full scale when a signal change occurs near the zero-crossing window. The AD7376 shutdown sleep mode programming feature is used to mute the device at power-up by holding the SHDN pin low and programming zero scale. Rev. A | Page 9 of 18 fH1 = 1/(2π × R1 × C1) AN-1291 Application Note Figure 12 shows a rare exception in which a 5 V supply is available to power the digital potentiometer. The SSM2211 can drive two speakers, as shown in Figure 11. However, the speakers must be configured in single-ended mode and output coupling capacitors are needed to block the dc current. The output capacitor and the speaker load form an additional high-pass cutoff frequency as follows: VCC (~3.3V) VDD C7 0.1µF C6 10µF PUSH-UP BUTTON A PU PD GND PUSH-DOWN BUTTON A SCL MCU SDA W C1 R1 1µF 10kΩ B 4 B – W U1 AD8565 3.5V < VCOM < 4.5V + R3 25kΩ C3 470µF 10kΩ R2 10kΩ GND C5 5V 0.1µF PRE – VDD 6 V+ U2 5 R5 8Ω 12052-025 5V R5 10kΩ VLOGIC R2 10kΩ U1 AD5259 R6 10kΩ As a result, C3 and C4 must be large to make the frequency as low as fH1. ±2.5V p-p 14.4V R1 70kΩ C1 1µF fH2 = 1/(2π × R5 × C3) AUDIO_INPUT 5V Figure 12. VCOM Adjustment Application SSM2211 Q: Can I adjust the digital potentiometer for frequencies around 1 MHz to 10 MHz for adjusting the gain of a video signal? In the more common case shown in Figure 13, only analog voltage 14.4 V and digital logic 3.3 V supplies are available. By placing discrete resistors above and below the digital potentiometer, the VDD pin is tapped off the resistor string itself. Based on the chosen resistor values, the voltage at the VDD pin in this case equals 4.8 V, allowing the wiper to be safely operated up to 4.8 V. The current draw of the VDD pin does not affect the bias of the node because it is only on the order of microamperes. The VLOGIC pin is tied to the 3.3 V digital supply of the microcontroller because the VLOGIC pin draws the 35 mA needed when writing to the EEPROM. It is impractical to source 35 mA through the 70 kΩ resistor; therefore, the VLOGIC pin is not connected to the same node as the VDD pin. A: Bandwidth is a function of the code and RAB. Lower RAB and lower codes yield higher bandwidth. Note that 10 MHz bandwidth or above is possible on some digital potentiometers. Refer to the relevant product data sheet for the Bode plots. The VLOGIC pin and the VDD pin are two separate supply pins that can be either tied together or treated independently. The VLOGIC pin can supply the logic/EEPROM with power while the VDD pin biases Terminal A, Terminal B, and Terminal W for added flexibility. Q: What is the maximum frequency applicable to the digital potentiometer clock (CLK) input? For a detailed look at this application, see the “Simple VCOM Adjustment uses any Logic Supply Voltage” EDN magazine article in the September 30, 2004 issue. + V– 8 1 7 2 5V R3 10kΩ C2 0.1µF – C4 470µF R6 8Ω U3 AD8591 12052-024 + R4 10kΩ Figure 11. Audio Amplifier with Volume Control INTERFACING A: For SPI and up/down (U/D) digital interfaced digital potentiometers, the maximum clock frequency is 10 MHz to 50 MHz. For I2C-compatible digital potentiometers, the maximum CLK frequency is guaranteed for 400 kHz. VCC (~3.3V) SUPPLIES POWER TO BOTH THE MICRO AND THE LOGIC SUPPLY OF THE DIGITAL POT C1 1µF LCD Panel VCOM Adjustment R1 70kΩ AD5259 R6 10kΩ A special feature of the AD5259 is its separation of the VLOGIC supply pin and the VDD supply pin. The separation provides greater flexibility in applications that do not always provide the needed supply voltages. In particular, LCD panels require a VCOM voltage in the range of 3 V to 5 V to provide a reference voltage to the back plane of the LCD panel. 14.4V R5 10kΩ – VDD VLOGIC A MCU SCL SDA B R2 10kΩ W U1 AD8565 + 3.5V < VCOM < 4.5V GND R3 25kΩ Figure 13. Circuitry When a Separate Supply Is Not Available for the VDD Pin Rev. A | Page 10 of 18 12052-027 3 Application Note AN-1291 5V R1 10kΩ QUADRATURE DECODER R2 10kΩ R3 10kΩ 1 U1 ROTARY ENCODER 2 3 B C A 4 DIGITAL POTENTIOMETER A1 U3 U2 LS7084 RBIAS CLK VDD U/D VSS X4/X1 A B 8 1 7 2 AD5227 CLK VDD 8 6 U/D 3 A1 7 CS B1 6 5 4 W1 5 GND B1 W1 12052-028 RE11CT-V1Y12-EF2CS Figure 14. Manual Rotary Control Manual Control with Rotary Encoder 6-Bit Controller Figure 14 shows a way of using the AD5227 (U3) to emulate a mechanical potentiometer in a rotary knob operation. The rotary encoder, U1, has a ground terminal, C, and out of phase signals, Signal A and Signal B. The AD5227 can form a simple, 6-bit controller with a clock generator, a comparator, and output components. Figure 15 shows a generic 6-bit controller with a comparator that compares the sampling output with the reference level and then outputs either a high level or low level through the U/D pin of the AD5227. The AD5227 then changes step at every clock cycle in the direction indicated by the state of the U/D pin. This circuit is self contained, easy to design, and can adapt to various applications. When U1 is turned clockwise, a pulse generated from Terminal B leads a pulse generated from Terminal A and vice versa. Signal A and Signal B of U1 pass through a quadrature decoder, the LS7084 (U2), which translates the phase difference between Signal A and Signal B of U1 into compatible inputs for U3. Therefore, when Signal B leads Signal A (clockwise), U2 provides U3 with a logic high U/D signal, and vice versa. U2 also filters noise, jitter, and other transients and debounces the contact bounces generated by U1. See the AN-1150 Application Note for information on how to control the AD5111, AD5113, and AD5115 with a traditional dial interface. U1 5V AD5227 VDD CLK – U/D B CS GND U3 AD8531 OUTPUT + OP AMP – SAMPLING_OUTPUT + REF Figure 15. 6-Bit Controller Rev. A | Page 11 of 18 12052-031 U2 COMPARATOR AN-1291 Application Note 5V RP RP SDA MASTER SCL 5V SDA SCL AD1 AD0 AD5253/ AD5254 SDA SCL AD1 AD0 AD5253/ AD5254 5V SDA SCL SCL SDA AD1 AD1 AD0 AD0 AD5253/ AD5254 12052-033 5V AD5253/ AD5254 Figure 16. Multiple AD5253/AD5254 Devices on a Single Bus The AD5253/AD5254 are equipped with two addressing pins, the AD1 pin and the AD0 pin, which allow up to four AD5253/ AD5254 devices to be operated on one I2C bus. To operate both devices on one I2C bus, the states of the AD1 pin and the AD0 pin on each device must first be defined. An example of addressing the AD1 pin and the AD0 pin is shown in both Table 2 and Figure 16. In I2C programming, each device is issued a different slave address—01011(AD1)(AD0)—to complete the addressing. AD0 0 1 0 1 VDD1 = 3.3V VDD2 = 5V RP RP RP S SDA1 D SDA2 G M1 D S M2 3.3V Device Addressed U1 U2 U3 U4 RP G SCL1 Table 2. Multiple Device Addressing AD1 0 0 1 1 from, the EEPROM. Figure 17 shows one of the level shifting implementations. M1 and M2 can be any N-channel signal field effect transistors (FET), or if either VDD1 or VDD2 falls below 2.5 V, M1 and M2 can be low threshold FETs, such as the FDV301N. This circuit is not suitable for 1.8 V logic levels. SCL2 5V AD5247 EEPROM 12052-032 Multiple Devices on One I2C Bus Figure 17. Level Shifting for Operation at Different Potentials GAIN In wireless base station smart antenna systems that require arrays of digital potentiometers to bias the power amplifiers, large numbers of AD5253/AD5254 devices can be addressed by using extra decoders, switches, and input/output buses, as shown in Figure 16. For example, to communicate to 16 devices, the user needs 4 decoders and 16 sets of combinational switches (four sets are shown in Figure 16). Two input/output buses serve as the common inputs of the four 2 × 4 decoders and select four sets of outputs at each combination. Because the four sets of combination switch outputs are unique, as shown in Figure 16, a specific device is addressed by properly programming the I2C with the slave address defined as 01011(AD1)(AD0). This operation allows one of 16 devices to be addressed, provided that the inputs of the two decoders do not change states. The inputs of the decoders can change after the operation of the specified device is complete. Level Shifting for Bidirectional Interface While most legacy systems can be operated at one voltage, a new component can be optimized at another voltage. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, users can employ a 3.3 V EEPROM to interface with a 5 V digital potentiometer. A level shifting scheme enables a bidirectional communication so the setting of the digital potentiometer can be stored in, and retrieved The following circuits are designed for dc operation. If the circuits are used with an ac signal excitation, it can result in stability issues. To guarantee that the circuit does not oscillate, placing a 10 pF capacitor in the feedback loop is recommended. Additionally, if the recommended op amps are substituted, take note of the following restrictions. The gain bandwidth product (GBP) is less than the bandwidth of VOUT (BW(VOUT)), and BW(VOUT ) = 1 2π × ROUT × C where: C is the pin capacitance of the VOUT pin. ROUT is the amplifier output impedance. ROUT is generally specified in the data sheet specifications or in the typical performance characteristic plots. See the Practical Techniques to Avoid Instability Due to Capacitive Loading Analog Dialogue article, Volume 38, Number 2, 2004 for more information. Rev. A | Page 12 of 18 Application Note AN-1291 Linear Gain Setting Mode Digital potentiometers are ideal for controlling the gain in an amplifier or setting the output voltage of a power supply regulator. However, using the digital potentiometer in potentiometer mode results in a logarithmic transfer function. Logarithmic transfer functions are desirable in applications such as light or audio control because human senses respond better to these stimuli. For applications where a linear transfer function is preferred, there are some techniques that can be employed, such as the Analog Devices patented architecture, linear gain setting mode, implemented in the AD5144, AD5142, AD5144A, and AD5141. For more information on linear gain setting mode and other linearizing techniques, see the AN-1169 Application Note, Linear Setting Mode: A Detailed Description. Optimum compensation occurs when R1 × C1 = R2 × C2. Optimum compensation is not an option because of the variation of R2. As a result, the user can use the previous relationship and scale C2 as if R2 were at its maximum value. Scaling C2 overcompensates and compromises the performance when R2 is set at low values. Alternatively, this scaling avoids the ringing or oscillation at the worst case. For critical applications, find C2 empirically to suit the oscillation. In general, setting C2 in the range of a few picofarads to no more than a few tenths of picofarads is adequate for the compensation. Similarly, the capacitances of Terminal W and Terminal A are connected to the output (see Figure 18); their effect at this node is less significant and the compensation can be avoided in most cases. LED DRIVER Gain Control Compensation Manual Adjustable LED Driver A digital potentiometer is commonly used in gain control, such as the noninverting gain amplifier shown in Figure 18. The AD5228 can be used in many electronics level adjustments, such as LED drivers for LCD panel backlight controls. Figure 19 shows a manually adjustable LED driver. The AD5228 (U1) sets the voltage across the white LED D1 for brightness control. Because the AD8591 (U2) handles up to 250 mA of output current, a typical white LED with a forward voltage (VF) of 3.5 V requires a resistor, R1, to limit U2 current. This circuit is simple, but not power efficient. The shutdown pin of U2 can be toggled with a pulsewidth modulation (PWM) signal to conserve power. R2 250kΩ B R1 47kΩ A W U1 VO VI 5V 12052-030 C1 11pF Figure 18. Gain Control Compensation C1 1µF When the parasitic capacitance of Terminal B is connected to the op amp noninverting node, it introduces a zero for the 1/βO term with 20 dB/dec, whereas a typical op amp gain bandwidth product (GBP) has −20 dB/dec characteristics. A large R2 and finite C1 can cause the frequency of this zero to fall well below the crossover frequency. The rate of closure, therefore, becomes 40 dB/dec, and the system has a 0° phase margin at the crossover frequency. If an input is a rectangular pulse or step function, the output can ring or oscillate. Similarly, it is also likely to ring when switching between two gain values, which is equivalent to a stop change at the input. Depending on the op amp GBP, reducing the feedback resistor extends the frequency of the zero far enough to overcome the problem. A better approach is to include a compensation capacitor, C2, to cancel the effect caused by C1. Rev. A | Page 13 of 18 C2 0.1µF U1 AD5228 VDD PUSH-UP BUTTON PD A C3 0.1µF V+ – U2 AD8591 R1 SD 6Ω W 10kΩ PU PUSH-DOWN BUTTON 5V + WHITE LED D1 V– B PRE GND PWM Figure 19. Low Cost Adjustable LED Driver 12052-013 C2 2.2pF AN-1291 Application Note Adjustable Current Source for LED Driver VOLTAGE TO CURRENT CONVERSION Because LED brightness is a function of current rather than of VF, an adjustable current source is preferred over a voltage source, as shown in Figure 20. Programmable Current Source A programmable current source can be implemented with the circuit shown in Figure 21. The load current is represented as the voltage between the wiper and Terminal B (VWB) of the AD5227 divided by RSET. +5V U1 VIN 3 SLEEP VOUT 6 REF191 VOUT GND U1 ARMZ-1.5 SD PWM GND 5V AD5231 B CLK U/D –2.048V TO VL W 10kΩ A RSET 0.1Ω R1 418kΩ RL 100Ω VL IL Figure 21. Programmable Current Source – U3 + VL D1 ID IL 12052-014 AD8591 V– V– The REF191 (U1) is a unique, low supply, headroom precision reference that can deliver the up to 20 mA at 2.048 V. The load current (IL) is the voltage across Terminal B and Terminal W of the digital potentiometer divided by RS. 5V V+ V+ ADA4077-1 U2 –5V GND RS 102Ω +5V VDD CS W A 4 U2 AD5227 ADP3333 B C1 1µF + VIN – 5V 0V TO (2.048V + VL) 12052-019 2 V I D WB RSET Figure 20. Adjustable Current Source for LED Driver The ADP3333ARMZ-1.5 (U1) is a 1.5 V low dropout (LDO) regulator that is lifted above or lowered below 0 V. When the VWB of the AD5227 is at a minimum, there is no current through the diode (D1), and thus the GND pin of the ADP3333 (U1) is at −1.5 V if the AD8591 (U3) is biased with dual supplies. As a result, some of the AD5227 (U2) low resistance steps have no effect on the output until the GND pin of U1 is lifted above 0 V. When the VWB of the AD5227 is at its maximum, VOUT becomes the load voltage (VL) plus the voltage across U2 (VAB); thus, the U1 supply voltage must be biased with adequate headroom. Similarly, a PWM signal can be applied at the shutdown pin of U1 for power efficiency. This circuit works well for a single LED. VREF D RS 1024 where: D is the code of the digital potentiometer wiper (U3 in Figure 21). VREF is the voltage of the chosen reference (2.048 V in Figure 21). The circuit in Figure 21 is simple, but be aware that there are two issues. First, dual-supply op amps are ideal because the ground potential of the REF191 can swing from −2.048 V, at zero scale, to the voltage of the load (VL), at full scale, of the potentiometer mode setting. Although the circuit works under single supply, the programmable resolution of the system is reduced. Second, the voltage compliance at VL is limited to 2.5 V or equivalent to a 125 Ω load. If higher voltage compliance is needed, users can consider digital potentiometers such as the AD5260, the AD5280, and the AD7376. To achieve higher current, such as when driving a high power LED, the user can replace U1 in Figure 21 with an LDO, reduce RS, and add a resistor in series with Terminal A of the digital potentiometer. This procedure limits the current of the potentiometer and increases the current adjustment resolution. Rev. A | Page 14 of 18 Application Note AN-1291 Programmable Bidirectional Current Source FILTERING For applications that require bidirectional current control or higher voltage compliance, a Howland current pump is one solution (see Figure 22). Programmable Low-Pass Filter In analog-to-digital conversions, it is common to include an antialiasing filter to band limit the sampling signal. Therefore, the dual channel AD5235 (denoted by R1 and R2) can be used to construct a second order, Sallen-Key low-pass filter, as shown in Figure 23. If the resistors are matched, the load current is (R2A + R2B) IL = R1 / R2B × VW C1 R1 150kΩ R2 15kΩ +2.5V C1 +15V 10pF – ADA4077-2 + V– A2 +15V A + B W V+ ADA4077-2 – V– –2.5V A1 –15V R2A 14.95kΩ V+ W AD8601 R VO V– U1 C2 –2.5V ADJUSTED CONCURRENTLY VL Figure 23. Sallen-Key Low-Pass Filter RL 500Ω IL The design equations for the Sallen-Key low-pass filter are VO ωf 2 = VI S 2 + ωf S + ωf 2 Q Figure 22. Programmable Bidirectional Current Source R2B, in theory, can be made as small as necessary to achieve the current needed within the ADA4077-2 (A2) output current driving capability. In the circuit shown in Figure 22, A2 delivers ±5 mA in both directions and the voltage compliance approaches 15 V. It can be shown that the output impedance (ZO) is ZO = B A R2B 50Ω –15V R1 150kΩ B W R V+ 12052-020 +2.5V A VI R2 12052-021 R1 ωO = Q= R1' R2B(R1 + R2A) R1R2' − R1' (R2A + R2B) ZO can be infinite if the R1' and R2' resistors match precisely with R1 and R2A + R2B, respectively. On the other hand, ZO can be negative if the resistors are not matched. As a result, C1, in the range of 1 pF to 10 pF, is needed to prevent oscillation from the negative impedance. 1 R1R2C1C2 1 1 + R1C1 R2C2 First, users select convenient values for the capacitors. To achieve maximally flat bandwidth, where Q = 0.707, let C1 be twice the size of C2 and let R1 equal R2. As a result, the user can adjust R1 and R2 concurrently to the same setting to achieve the desirable bandwidth. Rev. A | Page 15 of 18 AN-1291 Application Note Programmable State Variable Filter For RWB2 = RWB3, R1 = R2, and C1 = C2, One of the standard circuits used to generate a low-pass filter or a band-pass filter is the state variable active filter. The AD5233 can be used in this application to provide full programmability of the frequency, gain, and Q of the filter outputs. ωO = where RWBx is the resistance between Terminal W and Terminal B corresponding to the RDACx register (where x is 1 to 4). Figure 24 shows a filter circuit using a 2.5 V virtual ground, which allows a ±2.5 V peak input and output swing; the RDAC2 register and the RDAC3 register set the low-pass, high-pass, and band-pass cut off and center frequencies, respectively. To maintain the best Q of the circuit, the RDAC2 register and the RDAC3 register are programmed with the same data (as with ganged potentiometers). AO = Q= ω AO × O S VBP Q = ωO 2 Vi S + S + ωO 2 Q RWA4 RWB1 × RWB4 R1 Figure 24 shows the measured filter response at the band-pass output as a function of the RDAC2 register and the RDAC3 register settings. The settings produce a range of center frequencies from 2 kHz to 20 kHz. where: AO is the gain. Vi is the voltage input. VBP is the voltage at the band-pass filter. The filter gain response at the band-pass output is shown in Figure 24. At a center frequency of 2 kHz, the gain is adjusted over the −20 dB to +20 dB range, determined by the RDAC1 register. The Q of the circuit is adjusted by the RDAC4 register and the RDAC1 register. Suitable op amps for this application are the ADA4077-2, the AD8604, the OP279, and the AD824. RDAC4 B VIN R1 10kΩ R2 10kΩ 0.01µF 0.01µF A1 B1 B RDAC2 A2 B RDAC3 2.5V B2 LOW-PASS BAND-PASS OP279 × 2 HIGH-PASS Figure 24. Programmable State Variable Filter Rev. A | Page 16 of 18 12052-122 B RWB1 RWA1 where RWAx is the resistance between Terminal W and Terminal A corresponding to the RDACx register (where x is 1 to 4). The transfer function for the band-pass filter is RDAC1 1 RWB2 × C1 Application Note AN-1291 OTHER USAGE EXAMPLES Programmable Oscillator Programmable Voltage Source with Boosted Output In a classic Wien bridge oscillator, the Wien network (R||C, R'C') provides positive feedback, whereas R1 and R2 (split into R2A and R2B) provide negative feedback (see Figure 27). FREQUENCY ADJUSTMENT VI B R 25kΩ A VO N1 A AD5235 RBIAS SIGNAL CC U2 W V+ B C 2.2nF IL This circuit can source a 100 mA maximum with a 5 V supply. For precision applications, a voltage reference, such as the ADR421or the ADR03, can be applied at Terminal A of the digital potentiometer. R = R' = AD5235 R2B = AD5231 D1 = D2 = 1N4148 The AD7376 can be configured as a high voltage DAC as high as 30 V. The circuit is shown in Figure 26. The output is ωO = 1 R×C fO = 1 2π × R × C VDD AD7376 U2 100kΩ B U1B VOUT ADA4610-2 2 VO = I D R2B + VD 3 12052-018 Figure 26. High Voltage DAC 1024 − D × RAB + RW 1024 At resonance, setting R2/R1 = 2 balances the bridge. In practice, set R2/R1 slightly larger than 2 to ensure that oscillation can start. On the other hand, the alternate turn on of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2, momentarily stabilizing the oscillation. When the frequency is set, the oscillation amplitude can be turned by R2B because R2 R1 AMPLITUDE ADJUSTMENT where R is equal to RWA such that RWA (D) = ADR512 D2 At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R', C = C', and R2 = R2A/(R2B + RDIODE), where RDIODE is the resistance of the two diodes (D1 and D2), the oscillation frequency is VDD V+ ADA4610-2 V– A Or where D is the decimal code from 0 to 127. D1 B W R2A 2.1kΩ Figure 27. Programmable Oscillator with Amplitude Control R2 1.2 V × 1 + R1 U1A VO D1 R2B 10kΩ R1 1kΩ High Voltage DAC RBIAS U1 V+ –2.5V In this circuit, the inverting input of the op amp forces VO to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET, N1 (see Figure 25). N1 power handling must be adequate to dissipate (VI − VO) × IL power. D 128 B ADA4077-2 – V– Figure 25. Programmable Booster Voltage Source VO (D) = W 12052-016 V– A W +2.5V 2.2nF + LD AD8601 R' 25kΩ C' VP 12052-022 For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 25). where: ID is the current through the diode. VD is the voltage drop across the diode. VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium is reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance must not be too large to saturate the output. Rev. A | Page 17 of 18 AN-1291 Application Note Constant Bias with Supply to Retain Resistance Setting 3.50 Users who consider EEMEM potentiometers, but cannot justify the additional cost and programming for their designs, can consider constantly biasing the AD5227 with the supply to retain the resistance setting, as shown in Figure 28. 3.49 TA = 25°C 3.47 3.46 3.45 3.44 3.43 3.42 12052-035 BATTERY VOLTAGE (V) The AD5227 is designed specifically with low power to allow power conservation even in battery operated systems. As shown in Figure 29, a similar low power digital potentiometer is biased with a 3.4 V, 450 mA/hour, Li-Ion cell phone battery. The measurement shows that the device drains negligible power. Constantly biasing the potentiometer is a practical approach because most portable devices do not require detachable batteries for charging. Although the resistance setting of the AD5227 is lost when the battery must be replaced, this event occurs so infrequently that the inconvenience is minimal for most applications. 3.48 3.41 3.40 0 2 U1 U2 AD5227 VDD COMPONENT X COMPONENT Y GND GND + GND – GND 12052-034 BATTERY OR SYSTEM POWER VDD Figure 28. Constant Bias of the AD5227 for Resistance Retention I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN12052-0-3/15(A) Rev. A | Page 18 of 18 8 10 Figure 29. Battery Consumption Measurement U3 VDD 6 DAYS VDD SW1 4 12