CSD17484F4 30 V N-Channel FemtoFET

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CSD17484F4
SLPS550 – MAY 2015
CSD17484F4 30 V N-Channel FemtoFET™ MOSFET
1 Features
•
•
•
•
1
•
•
•
•
Product Summary
Low On-Resistance
Ultra-Low Qg and Qgd
Low Threshold Voltage
Ultra-Small Footprint (0402 Case Size)
– 1.0 mm × 0.6 mm
Ultra-Low Profile
– 0.2 mm Height
Integrated ESD Protection Diode
– Rated >4 kV HBM
– Rated >2 kV CDM
Lead and Halogen Free
RoHS Compliant
TA = 25°C
30
V
Qg
Gate Charge Total (4.5 V)
920
pC
Qgd
Gate Charge Gate-to-Drain
VGS(th)
75
Drain-to-Source On-Resistance
pC
VGS = 1.8 V
170
mΩ
VGS = 2.5 V
125
mΩ
VGS = 4.5 V
107
mΩ
VGS = 8.0 V
99
mΩ
Threshold Voltage
0.85
V
.
Ordering Information(1)
Device
CSD17484F4
•
•
UNIT
Drain-to-Source Voltage
RDS(on)
2 Applications
•
•
TYPICAL VALUE
VDS
CSD17484F4T
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Battery Applications
Handheld and Mobile Applications
Qty
Media
3000
7-Inch
Reel
250
7-Inch
Reel
Package
Ship
Femto(0402)
1.0 mm × 0.6 mm
Land Grid Array (LGA)
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
3 Description
VGS
Gate-to-Source Voltage
12
V
This 99 mΩ, 30 V N-Channel FemtoFET™ MOSFET
is designed and optimized to minimize the footprint in
many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
ID
Continuous Drain Current(1)
3.0
A
IDM
Pulsed Drain Current(1)(2)
18
A
Continuous Gate Clamp Current
35
Pulsed Gate Clamp Current(2)
350
Power Dissipation
500
mW
4
kV
2
kV
–55 to 150
°C
2.5
mJ
.
Typical Part Dimensions
0.2
m
0m
IG
PD
Human Body Model (HBM)
ESD
Rating Charged Device Model (CDM)
TJ,
Tstg
Operating Junction and
Storage Temperature Range
EAS
Avalanche Energy, single pulse ID = 7.1 A,
L = 0.1 mH, RG = 25 Ω
mA
(1) Typical RθJA = 85°C/W on 1 inch2 (6.45 cm2), 2 oz.
(0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4
PCB.
(2) Pulse duration ≤100 μs, duty cycle ≤1%
m
m
Top View
0.
60
1.
0
0
D
m
m
.
.
G
S
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17484F4
SLPS550 – MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1 Trademarks ............................................................... 7
6.2 Electrostatic Discharge Caution ................................ 7
6.3 Glossary .................................................................... 7
1
1
1
2
3
7
7.1
7.2
7.3
7.4
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Mechanical, Packaging, and Orderable
Information ............................................................. 8
Device and Documentation Support.................... 7
Mechanical Dimensions ............................................ 8
Recommended Minimum PCB Layout...................... 9
Recommended Stencil Pattern ................................. 9
CSD17484F4 Embossed Carrier Tape
Dimensions .............................................................. 10
4 Revision History
2
DATE
REVISION
NOTES
May 2015
*
Initial release.
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SLPS550 – MAY 2015
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-Source Voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = 24 V
100
nA
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 12 V
50
nA
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, IDS = 250 μA
RDS(on)
gƒs
Drain-to-Source On-Resistance
Transconductance
30
0.65
V
0.85
1.10
V
VGS = 1.8 V, IDS = 0.5 A
170
270
mΩ
VGS = 2.5 V, IDS = 0.5 A
125
160
mΩ
VGS = 4.5 V, IDS = 0.5 A
107
128
mΩ
VGS = 8 V, IDS = 0.5 A
99
121
mΩ
VDS = 15 V, IDS = 0.5 A
4
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
150
195
pF
44
57
Crss
Reverse Transfer Capacitance
pF
2.2
2.9
pF
RG
Series Gate Resistance
Qg
Gate Charge Total (4.5 V)
920
1200
pC
Qg
Gate Charge Total (8.0 V)
1570
2040
pC
Qgd
Gate Charge Gate-to-Drain
75
pC
Qgs
Gate Charge Gate-to-Source
280
pC
Qg(th)
Gate Charge at Vth
140
pC
Qoss
Output Charge
1400
pC
td(on)
Turn On Delay Time
3
ns
tr
Rise Time
1
ns
td(off)
Turn Off Delay Time
11
ns
tƒ
Fall Time
4
ns
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Ω
8
VDS = 15 V, IDS = 0.5 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode Forward Voltage
ISD = 0.5 A, VGS = 0 V
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
VDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs
0.73
0.9
V
1300
pC
6.2
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
Junction-to-Ambient Thermal Resistance
(1)
Junction-to-Ambient Thermal Resistance (2)
TYPICAL VALUES
85
245
UNIT
°C/W
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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SLPS550 – MAY 2015
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5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
10
VGS = 1.8 V
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
9
8
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
10
7
6
5
4
3
2
1
TC = 125°C
TC = 25°C
TC = -55°C
9
8
7
6
5
4
3
2
1
0
0
0
0.25
0.5
0.75
1
1.25
1.5
VDS - Drain-to-Source Voltage (V)
1.75
2
0
0.5
D002
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
4
D003
VDS = 5V
Figure 2. Saturation Characteristics
4
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Figure 3. Transfer Characteristics
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SLPS550 – MAY 2015
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
1000
7
6
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
8
5
4
3
2
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10
1
1
0
0
0.2
0.4
0.6
0.8
1
Qg - Gate Charge (nC)
ID = 0.5 A
1.2
1.4
0
1.6
3
6
D004
30
D005
Figure 5. Capacitance
250
RDS(on) - On-State Resistance (m:)
1.15
VGS(th) - Threshold Voltage (V)
27
VDS = 15 V
Figure 4. Gate Charge
1.05
0.95
0.85
0.75
0.65
0.55
0.45
0.35
-75
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
TC = 25°C, I D = 0.5 A
TC = 125°C, I D = 0.5 A
225
200
175
150
125
100
75
50
-50
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
0
175
2
D006
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
10
1.4
VGS = 2.5 V
VGS = 4.5 V
ISD - Source-To-Drain Current (A)
Normalized On-State Resistance
1.5
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
TC = 25qC
TC = 125qC
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
0
0.2
0.4
0.6
0.8
VSD - Source-To-Drain Voltage (V)
D008
1
D009
ID = 0.5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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CSD17484F4
SLPS550 – MAY 2015
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
IAV - Peak Avalanche Current (A)
IDS - Drain-To-Source Current (A)
100
10
1
0.1
100 ms
10 ms
0.01
0.01
1 ms
100 µs
10 µs
0.1
1
10
VDS - Drain-To-Source Voltage (V)
50
TC = 25q C
TC = 125q C
10
1
0.1
0.001
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single Pulse, Typical RθJA = 85°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125
TA - Ambient Temperature (°C)
150
175
D012
Figure 12. Maximum Drain Current vs Temperature
6
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CSD17484F4
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SLPS550 – MAY 2015
6 Device and Documentation Support
6.1 Trademarks
FemtoFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD17484F4
SLPS550 – MAY 2015
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
(1)
All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
(2)
This drawing is subject to change without notice.
(3)
This package is a PB-free solder land design.
Pin Configuration
Position
8
Designation
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
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SLPS550 – MAY 2015
7.2 Recommended Minimum PCB Layout
(1)
All dimensions are in millimeters.
7.3 Recommended Stencil Pattern
(1)
All dimensions are in millimeters.
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CSD17484F4
SLPS550 – MAY 2015
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7.4 CSD17484F4 Embossed Carrier Tape Dimensions
(1)
10
Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket
holes.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD17484F4
ACTIVE
PICOSTAR
YJJ
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
G2
CSD17484F4T
ACTIVE
PICOSTAR
YJJ
3
250
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
G2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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29-Jun-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
CSD17484F4
PICOST
AR
YJJ
3
3000
178.0
9.2
CSD17484F4T
PICOST
AR
YJJ
3
250
178.0
9.2
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
0.7
1.1
0.28
4.0
8.0
Q2
0.7
1.1
0.28
4.0
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17484F4
PICOSTAR
YJJ
3
3000
220.0
220.0
35.0
CSD17484F4T
PICOSTAR
YJJ
3
250
220.0
220.0
35.0
Pack Materials-Page 2
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