AS3677 Data Sheet

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Datasheet
AS3677
Triple Channel Lighting Management Unit with DCDC step/up,
ALS, 2xDLS(=DBC) and RGB Driver
2 Key Features
The AS3677 incorporates one Step Up DC/DC Converter for white backlight LEDs one Analog-to-Digital
Converter, six current sinks, LED in-circuit function test,
2
an I C serial interface, and control logic all onto a single
device. It includes a charge pump to control e.g. an RGB
together with an internal pattern generator for smooth
blinking effects.
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It supports ambient light sensor processing and two
Dynamic Luminance Scaling (DLS) (also called
Dynamic Backlight Control - DBC) input.
High-Efficiency Step Up DC/DC Converter
- Up to 25V, up to 50mA for White LEDs
- Programmable Over voltage Protection
(10V, 16V or 25V)
50mA Charge Pump
- 1:1 and 1:2 Mode with automatic Up Switching
- Only 2 External Capacitors Required
6 Current Sinks
- Fully Programmable (8-bit) from: 0.1mA to 25.5mA
- 3xHigh Voltage capable (up to 25V)
- 3xLow voltage for use with the CP (up to 5.5V)
- Selectively Enable/Disable Current Sinks
- Dual Dynamic Luminance Scaling (DLS) support to
improve backlight operating time (can adjust any
current source)
- Light Sensor input with internal hardware processing to control backlight according to ambient light
using 3 groups
Internal PWM Generation
- 8 Bit resolution
- Autonomous Logarithmic up/down dimming
Led Pattern Generator
- Autonomous driving of Fun RGB or indicator LEDs
10-bit Successive Approximation ADC
- 27µs Conversion Time
- Selectable Inputs: VANA, DLS1, DLS2, ALS/
GPIO1, GPIO2, CURR1, CURR2, CURR6, VBAT,
RGB1, RGB2 and RGB3
- Internal Temp. Measurement
- Light Sensor input with Java support (JSR-256):
read ADC processed value
Support for automatic LED testing (open and
shorted LEDs can be identified)
Programmable LDO
- 1.8 to 3.35V, 10mA
- Programmable via Serial Interface
Wide Battery Supply Range: 3.0V to 5.5V
2
I C Serial Interface Control with address control pin
Over current and Thermal Protection
Package
WL-CSP25, 2.2x2.2x0.6mm, 0.4mm pitch
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The AS3677 is a highly-integrated CMOS Power and
Lighting Management Unit for mobile telephones, and
other Li+ battery powered devices.
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1 General Description
Internally the PWM signal for DLS can be used to
change the analog current through the current sources
(two channels can be used simultaneously). This avoids
noise in the system as the changes of backlight control
happen continuously without using the PWM modulation
scheme.
Output voltages and output currents are fully programmable.
The AS3677 is part of the austriamicrosystems AS3675,
AS3687/87XM, AS3688 and AS3689 lighting management unit family. It is software compatible to AS3675,
AS3676, AS3687/87XM, AS3688 and AS3689.
The AS3677 is available in a space-saving WL-CSP
package measuring only 2.2x2.2x0.6mm and operates
over the -30ºC to +85ºC temperature range.
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Figure 1. Function Diagram
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AS3677
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3 Applications
Lighting Management Unit for mobile phones, smartphones, PMP or PND
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AS3677
Datasheet - A p p l i c a t i o n s
The application circuit including all external components is shown in Figure 2:
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Figure 2. Application Circuit AS3677
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AS3677
Datasheet - P i n o u t
4 Pinout
4.1
Pin Assignments
Figure 3. Pin Assignments (Top View)
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AS3677
4.2
Pin Description
Table 1. Pin Description
Pin Number
A1
A2
Charge pump output capacitor
VSS_DCDC
SW
C1_N
ALS/GPIO1
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B2
CPOUT
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B1
C1_P
VBAT_CP
A4
A5
Description
Charge pump flying capacitor
Charge pump supply voltage
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A3
Pin Name
DCDC and charge pump power ground pad - make a short connection to
capacitor C1 and C2 (and C5)
Power pad - DCDC switch transistor output
Charge pump flying capacitor
Ambient Light Sensor input and General Purpose Input Output 1
VBAT
Positive supply pad - Connect to battery.
B4
VSS
ground pad
B5
VSS
ground pad
C1
VANA
C2
INT
interrupt output - open drain active low
C3
ADR
I C address select input
C4
RGB2
Analog current sink input
C5
RGB1
Analog current sink input
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B3
LDO Output pad
2
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AS3677
Datasheet - P i n o u t
Table 1. Pin Description
Pin Number
Pin Name
Description
D1
GPIO3
D2
CLK
Digital input - Clock input for serial interface.
D3
DLS2
Digital Luminance Scaling PWM input2 (or General Input)
D4
RGB3
Analog current sink input
D5
CURR1
Analog current sink input
E1
GPIO2
General Purpose Input Output 2
E2
DATA
Digital input/output - Serial interface data
E3
DLS1
Digital Luminance Scaling PWM input1 (or General Input)
E4
CURR6
Analog current sink input
E5
CURR2
Analog current sink input
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General Purpose Input Output 3
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AS3677
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Table 3, “General
Operating Conditions; typical values are at VBAT=3.7V and 25ºC,” on page 5 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
VIN_HV
26V Pins
-0.3
26
V
Applicable for high-voltage
current sink pins CURR1,
CURR2, CURR6, SW
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Symbol
5V Pins
-0.3
7.0
V
VIN_LV
3.3V Pins
-0.3
5.0
V
Applicable for 3.3V pins
ALS/GPIO1, GPIO2, GPIO3,
DLS1, DLS2, VANA
GND pins
0.0
0.0
V
2xVSS, VSS_DCDC
Input Pin Current without causing
latchup
-25
+25
mA
At 25ºC, Norm: EIA/JESD78
Tstrg
Storage Temperature Range
-55
125
ºC
IIN
Humidity
5
85
%
Non-condensing
HBM
-2000
2000
V
Norm: JESD22-A114F
CDM
-500
500
V
Norm: JEDEC JESD 22C101E
MM
-100
100
V
Norm: JEDEC JESD 22A115-B
Total Power Dissipation
0.75
W
TA = 70 ºC, Tjunc_max =
125ºC; RTHJU=73 K/W
Peak Body Temperature
260
ºC
T = 20 to 40s, in accordance
with IPC/JEDEC J-STD 020.
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VIN_MV
Applicable for 5V pins
VBAT, VBAT_CP, CLK,
DATA, ADR, RGB1, RGB2,
RGB3, CPOUT, C1_P, C1_N,
INT
VESD
Pt
TBODY
Moisture sensitivity level
1
Represents a max. floor life
time of unlimited
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MSL
6 Electrical Characteristics
Symbol
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Table 3. General Operating Conditions; typical values are at VBAT=3.7V and 25ºC
Parameter
Condition
Min
High Voltage
Applicable for high-voltage current sink pins
CURR1, CURR2 and CURR6.
0.0
VBAT
Battery Voltage
Pin VBAT, VBAT_CP
3.0
VPERI
Periphery Supply
Voltage
For serial interface pins.
1.5
TAMB
Operating
Temperature Range
IACTIVE
Battery current
Normal Operating current (see Operating
Modes on page 58)
110
ISTANDBY
Standby Mode Current
Current consumption in standby mode.
Interface active
10
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VHV
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Typ
3.7
25
Max
Unit
26.0
V
5.5
V
5.5
V
85
ºC
µA
15
µA
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AS3677
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. General Operating Conditions; typical values are at VBAT=3.7V and 25ºC
Parameter
Condition
ISHUTDOWN
Shutdown Mode
Current
interface inactive (CLK and DATA set to 0V)
Min
Typ
Max
Unit
0.1
3
µA
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Symbol
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AS3677
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
Measured at VBAT=3.7V and TAMB=25ºC unless otherwise specified.
85
80
80
75
70
65
60
60
50
40
30
Vout: 25V, L=NRH3012
55
70
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DCDC Efficiency (%)
90
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Figure 5. Charge Pump: Efficiency vs. VBAT
90
Iload=50mA
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DCDC Efficiency (%)
Figure 4. DCDC Efficiency vs. Load Current
Vout: 15V, L=NRH3012
50
Iload=20mA
20
0
10
20
30
40
50
2,8
60
3
3,2
3,4
IOUT (mA)
Figure 6. Charge Pump: Battery current vs. VBAT
100
80
4,2
Figure 7. Current Sink CURR1 vs. V(CURRx)
Code=255
Code=128
Code=32
ICURR (mA)
20
70
60
15
50
40
10
30
20
5
Iload=50mA
10
Iload=20mA
0
2,8
3
3,2
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IBAT (mA)
4
25
90
3,4
3,6
VBAT [V]
3,8
4
0
4,2
0
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0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
VCURR [V]
2
Figure 9. LDO Output Voltage VANA vs. Code
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Figure 8. Current Sink RGB1 vs. V(CURRx)
3,4
3,2
3
20
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ICURR (mA)
Code=255
Code=128
Code=32
VANA [V]
25
3,8
30
110
30
3,6
VBAT [V]
15
2,8
2,6
2,4
2,2
10
2
5
1,8
1,6
0
0
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
VCURR [V]
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2
0
5
10
15
20
25
30
binary code
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AS3677
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 10. LDO Output Voltage VANA vs. Load
Figure 11. Charge Pump input and output ripple
50mA Load
2,79
1
2
3
4
5
6
ILOAD [mA]
7
8
9
10
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1:2 Mode
2,8
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VANA [V]
2,81
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
8.1
LDO
The LDO is a general purpose LDO and the output pin connected to VANA and intended to power an external light
sensor. Stability is guaranteed with ceramic output capacitors of 100nF ±20% (X5R).
The LDO is off by default after start-up.
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Figure 12. LDO Block Diagram
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AS3677
Table 4. Electrical Characteristics
Parameter
ILOAD
Output current
RON
On Resistance
VDROPOUT
Dropout Voltage
ION
Supply Current
tstart
Start-up Time
Vout_tol
Output Voltage
Tolerance
VOUT
Output Voltage
8.1.1
Condition
Min
Typ
0
10
Without load
Max
Unit
10
mA
25
Ω
250
mV
19
µA
200
µs
-3
+3
%
VBAT > 3.0V
1.8
2.75
V
Full Programmable Range
1.8
3.35
V
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Symbol
LDO Registers
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Table 5. Reg control Register
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Addr: 00
Bit Name
0
ldo_on
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs,
current sinks, the Step Up DC/DC Converter, and low-power mode.
Default Access
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Bit
Reg control
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0
R/W
Description
0
LDO is switched off
1
LDO is switched on
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 6. LDO Voltage Register
LDO Voltage
Addr: 07h
Bit
This register sets the output voltage (VANA) for the LDO.
Bit Name
Default Access
Description
ldo_voltage
4:0
8.2
00000b
R/W
00000b
1.8V
...
LSB=50mV
11111b
3.35V
Step Up DC/DC Converter
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Controls LDO voltage selection.
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The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to e.g.
25V/50mA. A constant switching-frequency results in a low noise on the supply and output voltages.
Figure 13. Step Up DCDC Converter Internal Block Diagram
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Table 7. Step Up DC/DC Converter Parameters
Symbol
Parameter
Condition
IVDD
Quiescent Current
Pulse skipping mode.
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Min
Typ
200
Max
Unit
µA
10 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 7. Step Up DC/DC Converter Parameters (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VFB
Feedback Voltage for
Current Sink
Regulation
on CURR1, CURR2 or CURR6 in regulation.
0.4
0.5
0.6
V
Coil current limit
1200
step_up_lowcur=1
750
For fixed startup time of
500us
step_up_lowcur=0
600
330
Switch Resistance
ON-resistance of external switching transistor.
0.42
ILOAD
Load Current
At 25V output voltage
0
fIN
Switching Frequency
Internally trimmed
0.9
1
COUT
Output Capacitor
Ceramic, ±20%. Use nominal 4.7µF capacitors
to obtain at least 0.7µF under all conditions
(voltage dependence of capacitors)
0.7
4.7
L
Inductor
tMIN_ON
Vripple
Ω
50
mA
1.1
MHz
µF
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step_up_lowcur=1
RSW
mA
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ICOIL_MAX
step_up_lowcur=0
Use inductors with small Cparasitic (<100pF) to
get high efficiency.
7
10
13
µH
Minimum on Time
90
140
190
ns
Maximum Duty Cycle
90
160
mV
40
mV
Voltage ripple >20kHz
Voltage ripple <20kHz
Efficiency
Cout=4.7µF,Iout=0..45mA, VBAT=3.0...4.2V
Efficiency
Iout=20mA,Vout=17V,VBAT=3.8V
%
85
%
To ensure soft startup of the dcdc converter, the over current limits are reduced for a fixed time after enabling the dcdc
converter. The total startup time for an output voltage of e.g. 26V is less than 2ms.
8.2.1
Feedback Selection
Register DCDC control1 and DCDC control2 selects the type of feedback for the Step Up DC/DC Converter.
The feedback for the DC/DC converter can be selected to any of the current sinks (CURR1, CURR2, CURR6). If the
register bit step_up_fb_auto is set, the feedback path is automatically selected between CURR1, CURR2 and CURR6
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(the lowest voltage of these current sinks is used) . The Step Up DC/DC Converter is regulated such that the required
current at the feedback path can be supported.
Note: Always choose the path with the highest voltage drop as feedback to guarantee adequate supply for the other
(unregulated) paths or enable the register bit step_up_fb_auto.
Over voltage Protection
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8.2.2
ch
The over voltage protection is controlled by the register step_up_vmax (can be programmed to 10V, 16V or 25V) to
protect the external components (especially the output capacitor C1. If the voltage on the pin SW exceeds this voltage,
the DCDC is immediately disabled and the register bit step_up_ov is set. To re-enable the DCDC set step_up_on=0
and afterwards step_up_on=1.
2
The voltage rating of the external components must be chosen to fit to the software setting of step_up_vmax .
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Note: The voltage on CURR1, CURR2 and CURR6 must not exceed 26V (see page 20)
1. It is recommended to leave step_up_fb_auto=1 (default) all the times.
2. If the voltage is the DCDC overvoltage protection is chosen above the voltage ratings of the external components, permanent damage might result.
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
8.2.3
PCB Layout Hints
To ensure good EMC performance of the DCDC converter, keep its external power components C1, L1, D1 and C2
close together. Connect the ground of C1, C2 locally together and connect this with a short path to AS3677 VSS. This
ensures that local high-frequency currents will not flow to the battery.
8.2.4
Step up Registers
Reg control
Addr: 00
Bit
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Table 8. Reg control Register
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit Name
Default Access
Description
step_up_on
0
R/W
0b
Disable the Step Up DC/DC Converter
1b
Enable the Step Up DC/DC Converter
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Enable the step up converter
Table 9. DCDC control1 Register
Addr: 21h
Bit
DCDC control1
This register controls the Step Up DC/DC Converter.
Bit Name
Default Access
Description
Defines the clock frequency of the Step Up DC/DC
Converter.
step_up_frequ
0
0
R/W
0
1MHz
1
500kHz
Controls the feedback source if step_up_fb_auto = 0
step_up_fb
2:1
01
R/W
00
no feedback selected - don’t use
01
CURR1 feedback enabled
(default)
10
CURR2 feedback enabled
11
CURR6 feedback enabled
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Overvoltage protection for the DCDC step up
step_up_vmax
00
R/W
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4:3
00
16V
01
10V
10
25V
11
don’t use (15.5V)
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Table 10. DCDC control2 Register
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Addr: 22h
Bit
1
Bit Name
DCDC control2
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Default Access
Description
Step Up DC/DC Converter output voltage at low loads,
when pulse skipping is active
skip_fast
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0
R/W
0
Accurate output voltage, more ripple
1
Elevated output voltage, less ripple
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 10. DCDC control2 Register (Continued)
DCDC control2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Bit
Bit Name
3
step_up_lowcur
Default Access
Description
Step Up DC/DC Converter coil current limit
R/W
0
Normal current limit
1
Current limit reduced by approx. 33%
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1
Step Up DC/DC overvoltage triggered
R
No overvoltage triggered
1
Overvoltage triggered; this bit is automatically
reset by step_up_on=0
0
step_up_fb select the feedback of the DCDC
converter
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step_up_fb_auto
7
1
R/W
1
8.3
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step_up_ov
4
0
The feedback is automatically chosen within the
current sinks CURR1, CURR2 and CURR6
(never DCDC_FB). Only those are used for this
selection, which are enabled (currX_mode must
not be 00) and not connected to the charge
pump (currX_on_cp must be 0).
Charge Pump
The Charge Pump uses the external flying capacitor C4 to generate output voltages higher than the battery voltage.
There are two different operating modes of the charge pump itself:
1:1 Bypass Mode
- Battery input and output are connected by a low-impedance switch
- battery current = output current.
1:2 Mode
- The output voltage is up to 2 times the battery voltage (without load), but is limited to VCPOUTmax all the time
- battery current = 2 times output current
As the battery voltage decreases, the Charge Pump must be switched from 1:1 mode to 1:2 mode in order to provide
enough supply for the current sinks. Depending on the actual current the mode with best overall efficiency can be automatically or manually selected:
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The charge pump mode switching can be done manually or automatically with the following possible software settings:
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Automatic
- Start with 1:1 mode
- Switch up automatically to 1:2 mode
Manual
- Set modes 1:1 and 1:2 by software
The Charge Pump requires the external components listed in the following table:
Table 11. Charge Pump External Components
Parameter
Condition
C4
External Flying
Capacitor
Ceramic low-ESR capacitor between pins
C1_P and C1_N
470
nF
C5
External Storage
Capacitor
Ceramic low-ESR capacitor between pins
CPOUT and VSS, pins CPOUT and VSS_CP
1.0
µF
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Symbol
Min
Typ
Max
Unit
Note: The connections of the external capacitors C4 and C5 should be kept as short as possible.
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
The maximum voltage on the flying capacitor C4 is VBAT.
Table 12. Charge Pump Characteristics
Condition
Min
ICPOUT
Output Current
Continuous
Depending on PCB layout
0.0
VCPOUTmax
Output Voltage
Internally limited, Including output ripple
η
Efficiency
Including current sink loss;
ICPOUT < 50mA.
80
ICP1_2
Power Consumption
without Load,
fclk = 1 MHz
1:2 Mode
2.15
1:1 Mode; VBAT = 3V
8.8
Rcp1_1
Effective Charge
Pump Output
Resistance (Open
Loop, fclk = 1MHz)
Rcp1_2
Accuracy of Clock
Frequency
currhv_switch
CURR1, 2, 6
minimum voltage
currlv_switch
RGB1-3 minimum
voltage
tdeb
CP automatic upswitching debounce
time
8.3.1
Max
Unit
50
mA
5.6
V
%
mA
Ω
31
-10
10
%
0.45
V
0.2
V
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fclk Accuracy
1:1.2 Mode; VBAT = 3V
Typ
al
id
Parameter
lv
Symbol
If the voltage drops below this threshold, the
charge pump will use the next available
mode
(1:1 -> 1:2)
cp_start_debounce=0
240
µsec
After switching on CP (cp_on set to 1), if
cp_start_debounce=1
2000
µsec
Charge Pump Mode Switching
If automatic mode switching is enabled (cp_mode_switching (see page 16) = 00 or cp_mode_switching = 01) the
charge pump monitors the current sinks, which are connected via a led to the output CPOUT. To identify these current
sources (sinks), the registers CP mode Switch1 and CP mode Switch2 (register bits rgb1_on_cp … rgb3_on_cp,
curr1_on_cp, curr2_on_cp and curr6_on_cp) should be setup before starting the charge pump (cp_on (see page 16) =
1). If any of the voltage on these current sources drops below the threshold (currlv_switch, currhv_switch), the next
higher mode is selected after the debounce time.
Te
ch
ni
ca
If the currX_on_cp=0 and the according current sink is connected to the charge pump, the current sink will be functional, but there is no up switching of the charge pump, if the voltage compliance is too low for the current sink to supply the specified current.
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 14. Automatic Mode Switching
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0-
$1
0-1
2
AS3677
8.3.2
Soft Start
)
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)
ni
An implemented soft start mechanism reduces the inrush current. Battery current is smoothed when switching the
charge pump on and also at each switching condition. This precaution reduces electromagnetic radiation significantly.
ch
8.3.3 Unused Charge Pump
Te
If the charge pump is not used, capacitors C4 and C5 (not C2) can be removed. The pins C1_P, C1_N and CPOUT
should be left open and keep register cp_on and cp_auto_on at 0 (default value).
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
8.3.4
Charge Pump Registers
Table 13. Reg control Register
Reg control
Addr: 00h
This register controls the Charge Pump.
Bit Name
2
cp_on
Default Access
0
R/W
Description
0
Set Charge Pump into 1:1 mode (off state) unless
cp_auto_on is set
1
Enable manual or automatic mode switching
al
id
Bit
Table 14. CP control Register
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit Name
Default Access
Description
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Bit
lv
CP control
Addr: 23h
Clock frequency selection.
cp_clk
0
0
R/W
0
1 MHz
1
500 kHz
Charge Pump mode (in manual mode sets this mode, in
automatic mode reports the actual mode used)
00
cp_mode
2:1
00b
R/W
1:1 mode
01
10
1:2 mode
11
Set the mode switching algorithm
00
4:3
cp_mode_switching
00b
R/W
Automatic Mode switching
01
cp_auto_on
0
1
R/W
R/W
11
Manual Mode switching; register cp_mode defines
the actual charge pump mode used
0
Mode switching debounce timer is always 240µs
1
Upon startup (cp_on set to 1) the mode switching
debounce time is first started with 2ms then
reduced to 240µs
0
Charge Pump is switched on/off with cp_on
1
Charge Pump is automatically switched on if a
current sink, which is connected to the charge
pump (defined by registers CP Mode Switch 1 & 2)
is switched on
Te
ch
6
cp_start_debounce
ni
5
ca
10
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 15. CP mode Switch1 Register
CP mode Switch1
Setup which current sinks are connected (via leds) to the charge pump; if set to
‘1’ the correspond current source (sink) is used for automatic mode selection of
the charge pump
Bit Name
4
rgb1_on_cp
Default Access
1
rgb2_on_cp
5
1
rgb3_on_cp
1
R/W
R/W
0
current Sink RGB1 is not connected to charge
pump
1
current sink RGB1 is connected to charge pump
0
current Sink RGB2 is not connected to charge
pump
1
current sink RGB2 is connected to charge pump
0
current Sink RGB3 is not connected to charge
pump
1
current sink RGB3 is connected to charge pump
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6
R/W
Description
al
id
Bit
lv
Addr: 24h
Table 16. CP mode Switch2 Register
CP mode Switch2
Addr: 25h
Bit
Bit Name
0
curr1_on_cp
Setup which current sinks are connected (via LEDs) to the charge pump; if set
to ‘1’ the correspond current source (sink) is used for automatic mode selection
of the charge pump
Default Access
0
curr2_on_cp
1
0
curr6_on_cp
7
0
R/W
R/W
R/W
Description
0
current Sink CURR1is not connected to charge
pump
1
current sink CURR1 is connected to charge pump
0
current Sink CURR2 is not connected to charge
pump
1
current sink CURR2 is connected to charge pump
0
current Sink CURR6 is not connected to charge
pump
1
current sink CURR6 is connected to charge pump
ca
Table 17. Curr low voltage status1 Register
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
ni
Addr: 2Ah
Bit Name
Default Access
ch
Bit
Curr low voltage status1
rgb1_low_v
NA
R
5
rgb2_low_v
NA
R
6
rgb3_low_v
NA
R
7
curr6_low_v
NA
R
Te
4
www.austriamicrosystems.com/AS3677
Description
0
voltage of current Sink RGB1 >currlv_switch
1
voltage of current Sink RGB1 <currlv_switch
0
voltage of current Sink RGB2 >currlv_switch
1
voltage of current Sink RGB2 <currlv_switch
0
voltage of current Sink RGB3 >currlv_switch
1
voltage of current Sink RGB31 <currlv_switch
0
voltage of current Sink CURR6 >currlv_switch
1
voltage of current Sink CURR6 <currlv_switch
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 18. Curr low voltage status2 Register
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit Name
0
curr1_low_v
NA
curr2_low_v
1
NA
Description
0
R
R
voltage of current Sink CURR1 >currhv_switch
1
voltage of current Sink CURR1 <currhv_switch
0
voltage of current Sink CURR2 >currhv_switch
1
voltage of current Sink CURR2 <currhv_switch
Current Sinks
lv
8.4
Default Access
al
id
Bit
The AS3677 contains three general purpose current sinks intended to control backlight LEDs.
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CURR1, CURR2 and CURR6 are used as feedback for the Step Up DC/DC Converter (regulated to 0.5V in this configuration) see Feedback Selection on page 11.
Table 19. Current Sink Function Overview
Current Sink
RGB1
RGB2
RGB3
CURR1
CURR2
CURR6
Max.
Voltage (V)
Max.
Current
(mA)
Resolution
(Bits)
(mA)
Software Current
Control
Hardware On/Off
Control
5.5
25.5
8
0.1
Separate
Internal PWM; external
PWM at DLS1, Pattern
generator
Internal PWM; external
PWM at DLS1, Pattern
generator
26.0
25.5
8
0.1
Separate
Internal PWM; external
PWM at DLS1 or
DLS2, Pattern
generator
Te
ch
ni
ca
The processing inside the AS3677 is shown in Figure 15 (shown for one current source only):
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 15. Internal processing of the different signals
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8.4.1 Unused Current Sinks
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Unused current sinks can be left open or used as ADC inputs (see Analog-to-Digital Converter on page 50).
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
8.4.2 High Voltage Current Sinks CURR1, CURR2, CURR6
The high voltage current sinks have a resolution of 8 bits.
Table 20. HV Current Sinks Characteristics
Parameter
Condition
Min
Typ
IBIT7
Current sink if Bit7 = 1
12.8
IBIT6
Current sink if Bit6 = 1
6.4
IBIT5
Current sink if Bit5 = 1
3.2
IBIT4
Current sink if Bit4 = 1
IBIT3
Current sink if Bit3 = 1
IBIT2
Current sink if Bit2 = 1
0.4
IBIT1
Current sink if Bit1 = 1
0.2
IBIT0
Current sink if Bit0 = 1
Δm
matching Accuracy
Δ
absolute Accuracy
VCURR1,2,6x
Voltage compliance
IQCURR1,2,6
Quiescent current
1.6
For V(CURRx) > 0.45V
Unit
mA
lv
0.8
Max
al
id
Symbol
+7
%
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nt
st
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0.1
-7
%
-15
CURR1,CURR2,CURR6
+15
0.45
25
165
V
µA
High Voltage Current Sinks CURR1, CURR2, CURR6 Registers
Table 21. Curr1 current Register
Addr: 09h
Bit
Bit Name
Curr1 current
This register controls the High voltage current sink current.
Default Access
Description
Defines current into current sink curr1
curr1_current
7:0
0
R/W
00h
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
ca
Table 22. Curr2 current Register
Bit Name
curr2_current
Te
7:0
Curr2 current
This register controls the High voltage current sink current.
Default Access
ch
Bit
ni
Addr: 0Ah
www.austriamicrosystems.com/AS3677
Description
Defines current into current sink curr2
0
R/W
00h
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 23. Curr6 current Register
Curr6 current
Addr: 2Fh
Bit
This register controls the High voltage current sink current.
Bit Name
Default Access
Description
0
R/W
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
Table 24. curr12 control Register
curr12 control
Bit
This register select the mode of the current sinks controls High voltage current
sink current.
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Addr: 01h
lv
curr6_current
7:0
00h
al
id
Defines current into current sink CURR6
Bit Name
Default Access
Description
Select the mode of the current sink curr1
curr1_mode
1:0
0
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
Select the mode of the current sink curr2
curr2_mode
3:2
0
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
Table 25. curr rgb control Register
Bit Name
This register select the mode of the current sinks CURR6.
Default Access
ni
Bit
curr6_mode
0
Description
Select the mode of the current sink CURR6
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
Te
ch
7:6
curr rgb control
ca
Addr: 02h
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
8.4.3
Current Sinks RGB1, RGB2, RGB3
These current sinks have a resolution of 8 bits and can sink up to 25.5mA.
Table 26. Current Sinks RGB1, RGB2, RGB3 Parameters
Parameter
Condition
Min
Typ
IBIT7
Current sink if Bit7 = 1
12.8
IBIT6
Current sink if Bit6 = 1
6.4
IBIT5
Current sink if Bit5 = 1
3.2
IBIT4
Current sink if Bit4 = 1
IBIT3
Current sink if Bit3 = 1
IBIT2
Current sink if Bit2 = 1
0.4
IBIT1
Current sink if Bit1 = 1
0.2
IBIT0
Current sink if Bit0 = 1
Δm
matching Accuracy
Δ
absolute Accuracy
1.6
For V(RGBx) > 0.2V
Unit
mA
lv
0.8
Max
al
id
Symbol
+10
%
am
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on A
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nt
st
il
0.1
VRGBX
Voltage compliance
IQRGB1,2,3
Quiescent current
-10
RGB1, RGB2, RGB3
-15
+15
%
0.2
CPO
UT
V
165
µA
RGB Current Sinks Registers
Table 27. curr rgb control Register
Addr: 02h
Bit
Bit Name
curr rgb control
This register select the mode of the current sinks RGB1, RGB2, RGB3
Default Access
Description
Select the mode of the current sink RGB1
rgb1_mode
ni
rgb2_mode
ch
3:2
Te
5:4
0
ca
1:0
rgb3_mode
www.austriamicrosystems.com/AS3677
0
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
Select the mode of the current sink RGB2
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
Select the mode of the current sink RGB3
0
R/W
00b
off
01b
on
10b
PWM controlled
11b
LED pattern controlled
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 28. Rgb1 current Register
Rgb1 current
Addr: 0Bh
Bit
Bit Name
This register controls the RGB current sink current.
Default Access
Description
rgb1_current
7:0
0
R/W
00h
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
Rgb2 current
Addr: 0Ch
Bit Name
This register controls the RGB current sink current.
Default Access
Description
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Bit
lv
Table 29. Rgb2 current Register
al
id
Defines current into Current sink RGB1
Defines current into Current sink RGB2
rgb2_current
7:0
0
R/W
00h
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
Table 30. Rgb3 current Register
Rgb3 current
Addr: 0Dh
Bit
Bit Name
This register controls the RGB current sink current.
Default Access
Description
Defines current into Current sink RGB3
rgb3_current
8.4.4
0
ca
7:0
R/W
00h
0 mA
01h
0.1 mA
....
....
FFh
25.5 mA
LED Pattern Generator
ni
The LED pattern generator is capable of producing a pattern with 32 bits length and 1 second duration (31.25ms for
nd
rd
th
3
each bit). The pattern itself can be started every second, every 2 , 3 up to 7 second .
ch
With this pattern all current sinks can be controlled. The pattern itself switches the configured current sources between
0 and their programmed current.
Te
If everything else is switched off, the current consumption in this mode is IACTIVE. (excluding current through switched
on current source) and the charge pump, if required. The charge pump can be automatically switched on/off depending
on the pattern (set register cp_auto_on on page 16=1) to reduce the overall current consumption.
3. All times can be extended by a factor of 8 by setting pattern_slow=1 (this result in a delay of up to 56s)
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 16. LED Pattern Generator AS3677 for pattern_color = 0
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To select the different current sinks to be controlled by the LED pattern generator, see the ‘xxxx’_mode registers
(where ‘xxxx’ stands for the to be controlled current sink, e.g. curr1_mode for CURR1 current sink). See also the
description of the different current sinks.
To allow the generator of a color patterns set the bit pattern_color to ‘1’. Then the pattern can be connected to CURRx
as follows:
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Figure 17. LED Pattern Generator AS3677 for pattern_color = 1
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Only those current sinks will be controlled, where the ‘xxxx’_mode register is configured for LED pattern.
If the register bit pattern_slow is set, all pattern times are increased by a factor of eight. (bit duration: 250ms if
pattern_color=0 / 800ms if pattern_color=1, delays between pattern up to 56s).
Soft Dimming for Pattern
ca
The internal pattern generator can be combined with the internal pwm dimming modulator to obtain as shown in the following figure:
ch
ni
Figure 18. Soft dimming Architecture for the AS3677 (softdim_pattern=1 and pattern_color = 1)
Te
www.austriamicrosystems.com/AS3677
1v3-1
! !
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$%%&%
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24 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
With the AS3677 smooth fade-in and fade-out effects can be automatically generated.
As there is only one dimming ramp generator and one pwm modulator following constraints have to be considered
when setting up the pattern (applies only if pattern_color=1):
Figure 19. Soft dimming example Waveform for CURR30-32
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! However using the identical dimming waveform for two channels is possible as shown in the following figure:
Figure 20. Soft dimming example Waveform for CURR30-32
LED Pattern Registers
Table 31. Pattern data0...Pattern data3 Registers
Pattern data0, Pattern data1, Pattern data2, Pattern data3
ca
Addr: 19h,1Ah,1Bh,1Ch
Bit
Bit Name
7:0
pattern_data_0
1
7:0
Description
0
R/W
Pattern data0
pattern_data_1
0
R/W
Pattern data1
pattern_data_2
0
R/W
Pattern data2
0
R/W
Pattern data3
ch
7:0
Default Access
ni
7:0
This registers contains the pattern data for the current sinks.
pattern_data_3
Te
1. Update any of the pattern register only if none of the current sources is connected to the pattern generator
('xxxx'_mode must not be 11b). The pattern generator is automatically started at the same time when any of the
current sources is connected to the pattern generator
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 32. Pattern control Register
Pattern control
Addr: 18h
Bit
This register controls the LED pattern
Bit Name
Default Access
Description
Defines the pattern type for the current sinks
0
pattern_delay
2:1
R/W
00b
R/W
0b
single 32 bit pattern (also set currX_mode = 11)
1b
RGB pattern with each 10 bits (set all
currX_mode = 11)
al
id
pattern_color
0
Delay between pattern, details (see Table 35); together with
pattern_delay2 sets the delay time between patterns
softdim_pattern
0b
R/W
0
Pattern generator directly control current
sources
1
‘Soft Dimming’ is performed (see page 24)
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3
lv
Enable the ‘soft’ dimming feature for the pattern generator
Table 33. Gpio current Register
Addr: 2Ch
Bit
Bit Name
4
pattern_delay2
Gpio current
Default Access
0
R/W
Description
Delay between pattern (see Table 35 on page 26); together
with pattern_delay sets the delay time between patterns
Pattern timing control
pattern_slow
6
0
R/W
0b
normal mode
1b
slow mode (all pattern times are increased by a
factor of eight)
Table 34. Pattern End Register
Addr: 54h
Bit
Pattern End
Bit Name
Default Access
pattern_end
0
R
ca
0
Description
pattern_end is toggled from 0 to 1 (or from 1 to 0) at each
end of the pattern just before restarting of the internal
pattern generator at the first bit of the pattern data
(can be used to synchronize the baseband software to the
1
pattern generator)
ni
1. pattern_end toggles whenever the AS3677 is in active mode (see Section 8.11 Operating Modes on page 58)
even if no pattern data has been setup.
ch
Table 35. LED Pattern timing
pattern_delay2
Te
pattern_slow
pattern_delay[1..0]
delay between patterns
bit duration [ms]
pattern
[s]
delay [s] duration
cycle
between (total
time:
pattern_color=0 pattern_color=1 patterns
pattern +
delay)
0
0
00
31
100
0
1
1
0
0
01
31
100
1
2
0
0
10
31
100
2
3
0
0
11
31
100
3
4
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1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 35. LED Pattern timing
pattern_delay2
pattern_slow
pattern_delay[1..0]
delay between patterns
bit duration [ms]
pattern
[s]
delay [s] duration
cycle
between (total
time:
pattern_color=0 pattern_color=1 patterns
pattern +
delay)
1
00
31
100
4
5
0
1
01
31
100
5
0
1
10
31
100
6
0
1
11
31
100
7
1
0
00
250
800
0
1
0
01
250
800
8
1
0
10
250
800
1
0
11
250
800
1
1
00
250
800
32
40
1
1
01
250
800
40
48
1
1
10
250
800
48
56
1
1
11
250
800
56
64
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0
6
7
8
8
lv
16
24
24
32
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16
1. Even by setting 000 for pattern delay, there is a small delay before the new patterns starts.
8.4.5 PWM Generator
The PWM generator can be used for any current sink. The setting applies for all current sinks, which are controlled by
the pwm generator (e.g. CURR1 is pwm controlled if curr1_mode = 10). The pwm modulated signal can switch on/off
the current sinks and therefore depending on its duty cycle change the brightness of an attached LED.
Internal PWM Generator
The internal PWM generator uses the 2MHz internal clock as input frequency and its dimming range is 6 bits digital
(2MHz / 2^6 = 31.3kHz pwm frequency) and 2 bits analog. Depending on the actual code in the register pwm_code the
following algorithm is used:
If pwm_code bit 7 = 1
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Then the upper 6 bits (Bits 7:2) of pwm_code are used for the 6 bits PWM generation, which controls the selected currents sinks directly
If pwm_code bit 7 =0 and bit 6 = 1
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Then bits 6:1 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected current sinks, but
the analog current of these sinks is divided by 2
If pwm_code bit 7 and bit 6 = 0
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Then bits 5:0 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected current sinks, but
the analog current of these sinks is divided by 4
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1v3-1
27 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 21. PWM Control
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Automatic Up/Down Dimming
If the register pwm_dim_mode is set to 01 (up dimming) or 10 (down dimming) the value within the register pwm_code
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is increased (up dimming) or decreased (down dimming) every time and amount (either 1/4 or 1/8 ) defined by the
register pwm_dim_speed. The maximum value of 255 (completely on) and the minimum value of 0 (off) is never
exceeded. It is used to smoothly and automatically dim the brightness of the LEDs connected to any of the current
sinks. The PWM code is readable all the time (also during up and down dimming).
The waveform for up dimming looks as follows (cycles omitted for simplicity):
Figure 22. PWM Dimming Waveform for up dimming (pwm_dim_mode = 01); currX_mode = PWM controlled (not
all steps shown)
The internal pwm modulator circuit controls the current sinks as shown in the following figure:
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Figure 23. PWM Control Circuit (currX_mode = 10b (PWM controlled)); X = any current sink
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The adder logic (available for all current sinks) is intended to allow dimming not only from 0% to 100% (or 100% to 0%)
of currX_current, but also e.g. from 10% to 110% (or 110% to 10%) of currX_current. The starting current for up dimming is defined by 0 + currX_adder and the end current is defined by currX_current + currX_adder.
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1v3-1
28 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
An overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register settings (currX_current +
currX_adder must not exceed 255).
Note: The adder logic operates independent of the currX_mode setting, but its main purpose is to work together with
the pwm modulator (improved up/down dimming)
If the adder logic is not used anymore, set the bit currX_adder to 0. (Setting adder_currentX to 0 is not sufficient)
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At the end of up/down dimming, the pwm_code register keeps its final value (for up-dimming 255 and for downdimming 0). This can be used to identify the exact time, when up/down dimming is finished.
Table 36. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
5msec/
Step
2.5msec/
Step
0,000s
0,000s
0,005s
0,003s
%Dimming
PWM
%Dimming
PWM
50msec/
Step
25msec/
Step
1
100,0
255
100,0
255
0,00s
0,00s
2
75,3
192
87,8
224
0,05s
0,03s
3
56,5
144
76,9
196
0,10s
0,05s
0,010s
0,005s
4
42,4
108
67,5
172
0,15s
0,08s
0,015s
0,008s
5
31,8
81
59,2
151
0,20s
0,10s
0,020s
0,010s
6
23,9
61
52,2
133
0,25s
0,13s
0,025s
0,013s
7
18,0
46
45,9
117
0,30s
0,15s
0,030s
0,015s
8
13,7
35
40,4
103
0,35s
0,18s
0,035s
0,018s
9
10,6
27
35,7
91
0,40s
0,20s
0,040s
0,020s
10
8,2
21
31,4
80
0,45s
0,23s
0,045s
0,023s
11
6,3
16
27,5
70
0,50s
0,25s
0,050s
0,025s
12
4,7
12
24,3
62
0,55s
0,28s
0,055s
0,028s
13
3,5
9
21,6
55
0,60s
0,30s
0,060s
0,030s
14
2,7
7
19,2
49
0,65s
0,33s
0,065s
0,033s
15
2,4
6
16,9
43
0,70s
0,35s
0,070s
0,035s
16
2,0
5
14,9
38
0,75s
0,38s
0,075s
0,038s
17
1,6
18
1,2
19
0,8
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Step
13,3
34
0,80s
0,40s
0,080s
0,040s
3
11,8
30
0,85s
0,43s
0,085s
0,043s
2
10,6
27
0,90s
0,45s
0,090s
0,045s
0,4
1
9,4
24
0,95s
0,48s
0,095s
0,048s
0,0
0
8,2
21
1,00s
0,50s
0,100s
0,050s
22
7,5
19
1,05s
0,53s
0,105s
0,053s
23
6,7
17
1,10s
0,55s
0,110s
0,055s
24
5,9
15
1,15s
0,58s
0,115s
0,058s
25
5,5
14
1,20s
0,60s
0,120s
0,060s
26
5,1
13
1,25s
0,63s
0,125s
0,063s
27
4,7
12
1,30s
0,65s
0,130s
0,065s
28
4,3
11
1,35s
0,68s
0,135s
0,068s
29
3,9
10
1,40s
0,70s
0,140s
0,070s
20
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1v3-1
29 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 36. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
PWM
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
30
3,5
9
1,45s
0,73s
0,145s
0,073s
31
3,1
8
1,50s
0,75s
0,150s
0,075s
32
2,7
7
1,55s
0,78s
0,155s
0,078s
33
2,4
6
1,60s
0,80s
0,160s
0,080s
34
2,0
5
1,65s
0,83s
0,165s
0,083s
35
1,6
4
1,70s
0,85s
0,170s
0,085s
36
1,2
3
1,75s
0,88s
37
0,8
2
1,80s
0,90s
38
0,4
1
1,85s
0,93s
0,0
0
1,90s
0,95s
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PWM
0,175s
0,088s
0,180s
0,090s
0,185s
0,093s
0,190s
0,095s
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%Dimming
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%Dimming
Step
PWM Generator Registers
Table 37. Pwm control Register
Addr: 16h
Bit
Bit Name
Pwm control
This register controls PWM generator
Default Access
Description
Selects the dimming mode
pwm_dim_mode
00b
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000b
01b
logarithmic up dimming (codes are increased).
Start value is actual pwm_code
10b
logarithmic down dimming (codes are
decreased). Start value is actual pwm_code;
switch off the dimmed current source after
dimming is finished to avoid unnecessary
quiescent current
11b
NA
Defines dimming speed by increase/decrease pwm_code
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pwm_dim_speed
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5:3
no dimming; actual content of register
pwm_code is used for pwm generator
R/W
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2:1
00b
R/W
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000b
by 1/4 every 50 msec (total dim time 1.0s)
001b
by 1/8 every 50 msec (total dim time 1.9s)
010b
by 1/4 every 25 msec (total dim time 0.5s)
011b
by 1/8 every 25 msec (total dim time 0.95s)
100b
by 1/4 every 5 msec (total dim time 100ms)
101b
by 1/8 every 5 msec (total dim time 190ms)
110b
by 1/4 every 2.5 msec (total dim time 50ms)
111b
by 1/8 every 2.5 msec (total dim time 95ms)
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 38. Pwm code Register
Pwm code
Addr: 17h
Bit
This register controls the Pwm code.
Bit Name
Default Access
Description
pwm_code
7:0
00b
R/W
00h
0% duty cycle
....
....
FFh
100% duty cycle
Adder Current 1
Addr: 30h
This register defines the current which can be added to CURR1, CURR30,
CURR41, RGB1
Bit Name
Default Access
Description
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Table 39. Adder Current 1 Register
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Selects the PWM code
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
adder_current1
7:0
00b
R/W
00h
0 (represents 0mA)
....
....
FFh
255 (represents 25.5mA)
Table 40. Adder Current 2 Register
Adder Current 2
Addr: 31h
Bit
Bit Name
This register defines the current which can be added to CURR2, CURR31,
CURR42, RGB2
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
adder_current2
00b
R/W
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7:0
00h
0 (represents 0mA)
....
....
FFh
255 (represents 25.5mA)
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Table 41. Adder Current 3 Register
Addr: 32h
Bit Name
ch
Bit
Te
7:0
Adder Current 3
This register defines the current which can be added to CURR6, CURR32,
CURR43, RGB3
Default Access
adder_current3
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Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00b
R/W
00h
0 (represents 0mA)
....
....
FFh
255 (represents 25.5mA)
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 42. Adder Enable 2 Register
Adder Enable 2
Addr: 34h
Bit
Enables the adder circuit for the selected current sources
Bit Name
Default Access
Description
Enables adder circuit for current source CURR1
0
0
Normal Operation of the current source
1
adder_current1 gets added to the current
source current; if curr1_amb_group is not 00,
the adder current is multiplied by the ALS group
selected by curr1_amb_group
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curr1_adder
0
R/W
Enables adder circuit for current source CURR2
0
Normal Operation of the current source
1
adder_current2 gets added to the current
source current; if curr2_amb_group is not 00,
the adder current is multiplied by the ALS group
selected by curr2_amb_group
R/W
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0
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curr2_adder
1
Enables adder circuit for current source CURR6
curr6_adder
2
0
0
Normal Operation of the current source
1
adder_current3 gets added to the current
source current; if curr6_amb_group is not 00,
the adder current is multiplied by the ALS group
selected by curr6_amb_group
R/W
Table 43. Adder Enable 1 Register
Addr: 33h
Bit
Bit Name
Adder Enable 1
Enables the adder circuit for the selected current sources
Default Access
Description
Enables adder circuit for current source RGB1
rgb1_adder
0
0
R/W
0
Normal Operation of the current source
1
adder_current1 gets added to the current
source current
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Enables adder circuit for current source RGB2
rgb2_adder
rgb3_adder
0
0
Normal Operation of the current source
1
adder_current2 gets added to the current
source current
0
R/W
0
Normal Operation of the current source
1
adder_current3 gets added to the current
source current
ALS - Ambient Light Sensing
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R/W
Enables adder circuit for current source RGB3
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1
4
The ADC converts every 1ms the ambient light sensor signal from pin ALS/GPIO1 . This signal is pre-processed with
a offset defined by amb_offset and a gain defined by amb_gain (1/4, 1/2, 1, 2). Then it is low-pass filtered with a programmable cut-off frequency going from 0.25Hz to 32Hz. Increasing signals and decreasing signal can have individual
cut-off frequencies adjustable from 0.25Hz to 32Hz (amb_filter_up and amb_filter_down).
This filtered signal can be readout from the register amb_result<7:0>.
4. adc_select=02h (select ALS/GPIO1 input)
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1v3-1
32 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Each of the available three channels (N=1 or 2) has six 8-bit registers:
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- groupN_y0: define current multiplier for values below groupN_X1
- groupN_y3: define current multiplier for high values (actual starting point defined by groupN_x1,groupN_k1 and
groupN_x2,groupN_k2)
- groupN_x1, groupN_k1: If ADC reading is > groupN_x1 then groupN_k1 divided by 32 defines the slope of the
first ramp
- groupN_x2, groupN_k2: If ADC reading is > groupN_x2 then groupN_k2 divided by 32 defines the slope of the
second ramp
Each current sources has a 2 bit register (currX_amb_group) to select None, Group1 or Group2 of ambient light sensing.
The calculations are done every 1ms resulting in a flicker-free 1000Hz update rate of the current sources.
Note: The ADC is switched off between conversion to save power.
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All groupN_k1 and groupN_k2 values are divided by 32 except group3_k1 (see page 39), which is divided by
1. This allows a step response to a small change in the input signal (e.g. for keyboard backlight).
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Table 44. ALS Parameters
Symbol
Parameter
Condition
excluding LDO supplying external
ALS operating current averaged;
sensor - see LDO on page 9
Typ
19
Max
Unit
µA
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Min
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1v3-1
33 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 24. Ambient Light Sensor and Interrupt Logic internal circuit
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Table 45. ALS control Register
ALS control
Addr: 90h
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Bit
0
Bit Name
control ambient light sensing
Default Access
Description
Enables the ambient light sensing feature
amb_on
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0
R/W
0
ambient light sensor disabled
1
ambient light sensor enabled
1v3-1
34 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 45. ALS control Register (Continued)
ALS control
Addr: 90h
Bit
control ambient light sensing
Bit Name
Default Access
Description
amb_gain
2:1
0
R/W
00
gain = 1/4
01
gain = 1/2
10
gain = 1
11
gain = 2
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Control Ambient Light Sensor preprocessing gain
amb_keep
0
R/W
0
Group output is enabled (S/H = sampling)
1
Groups outputs on hold (S/H = hold)
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Enable S/H of group tables output - see Figure 24 on
page 34
Table 46. ALS filter Register
Addr: 91h
Bit
Bit Name
ALS filter
control for ambient light sensor filtering
Default Access
Description
Controls the filter cut off (-3dB) frequency (increasing)
amb_filter_up
2:0
000
R/W
000
0.25Hz
001
0.5Hz
010
1Hz
011
2Hz
100
4Hz
101
8Hz
110
16Hz
111
32Hz
amb_filter_down
000
R/W
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Controls the filter cut off (-3dB) frequency (decreasing)
000
0.25Hz
001
0.5Hz
010
1Hz
011
2Hz
100
4Hz
101
8Hz
110
16Hz
111
32Hz
Table 47. ALS offset Register
Addr: 92h
Bit
Bit Name
7:0
amb_offset
ALS offset
Default Access
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00h
R/W
Description
Controls the offset of the ambient light sensor
1v3-1
35 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 48. ALS result Register
Addr: 93h
ALS result
Bit Name
7:0
amb_result
Default Access
00h
Description
R
Filtered result of the ambient light sensor value
W
Pre-set the value of the ALS filter (especially useful when
doing gain switching of the ALS sensor)
Table 49. ALS curr12 group Register
ALS curr12 group
Addr: 94h
controls the group mapping for CURR1 and CURR2
Bit Name
Default Access
Description
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Bit
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Bit
CURR1 is mapped to ambient light sensor group
curr1_amb_group
00
R/W
None - no ambient light sensor control
01
Group 1
10
Group 2
11
Group 3
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1:0
00
CURR2 is mapped to ambient light sensor group
3:2
curr2_amb_group
00
R/W
00
None - no ambient light sensor control
01
Group 1
10
Group 2
11
Group 3
Table 50. ALS rgb group Register
Addr: 95h
Bit
Bit Name
ALS rgb group
controls the group mapping for RGB1, RGB2, RGB3 and CURR6
Default Access
Description
RGB1 is mapped to ambient light sensor group
Te
5:4
00
ca
rgb2_amb_group
ch
3:2
rgb1_amb_group
ni
1:0
rgb3_amb_group
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00
R/W
00
None - no ambient light sensor control
01
Group 1
10
Group 2
11
Group 3
RGB2 is mapped to ambient light sensor group
R/W
00
None - no ambient light sensor control
01
Group 1
10
Group 2
11
Group 3
RGB3 is mapped to ambient light sensor group
00
R/W
00
None - no ambient light sensor control
01
Group 1
10
Group 2
11
Group 3
1v3-1
36 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 50. ALS rgb group Register (Continued)
ALS rgb group
Addr: 95h
Bit
controls the group mapping for RGB1, RGB2, RGB3 and CURR6
Bit Name
Default Access
Description
CURR6 is mapped to ambient light sensor group
00
R/W
01
Group 1
10
Group 2
11
Group 3
Group1
Table 51. ALS group 1 Y0 Register
ALS group 1 Y0
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Addr: 98h
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curr6_amb_group
None - no ambient light sensor control
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7:6
00
Bit
Bit Name
7:0
group1_y0
Default Access
00h
Description
R/W
Group 1 y0 value - divided by 256
Table 52. ALS group 1 Y3 Register
Addr: 99h
Bit
Bit Name
7:0
group1_y3
ALS group 1 Y3
Default Access
00h
Description
R/W
Group 1 y3 value - divided by 256
Table 53. ALS group 1 X1 Register
Addr: 9Ah
Bit
Bit Name
7:0
group1_x1
ALS group 1 X1
Default Access
00h
Description
R/W
Group 1 x1 value
Table 54. ALS group 1 K1 Register
Addr: 9Bh
Bit Name
7:0
group1_k1
Default Access
ca
Bit
ALS group 1 K1
00h
R/W
Description
Group 1 k1 value - divided by 32 defines first slope
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Table 55. ALS group 1 X2 Register
Addr: 9Ch
Bit
Default Access
group1_x2
00h
ch
7:0
Bit Name
ALS group 1 X2
Description
R/W
Group 1 x2 value
Table 56. ALS group 1 K2 Register
Te
Addr: 9Dh
Bit
Bit Name
7:0
group1_k2
ALS group 1 K2
Default Access
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00h
R/W
Description
Group 1 k2 value- value divided by 32 defines second slope
1v3-1
37 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Group2
Table 57. ALS group 2 Y0 Register
Addr: 9Eh
Bit Name
7:0
group2_y0
Default Access
00h
Description
R/W
Group 2 y0 value - divided by 256
Table 58. ALS group 2 Y3 Register
Addr: 9Fh
Bit Name
7:0
group2_y3
Default Access
00h
Description
R/W
Group 2 y3 value - divided by 256
Table 59. ALS group 2 X1 Register
Addr: A0h
Bit Name
7:0
group2_x1
Default Access
Description
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ALS group 2 X1
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ALS group 2 Y3
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Bit
ALS group 2 Y0
00h
R/W
Group 2 x1 value
Table 60. ALS group 2 K1 Register
Addr: A1h
Bit
Bit Name
7:0
group2_k1
ALS group 2 K1
Default Access
00h
R/W
Description
Group 2 k1 value - divided by 32 defines first slope
Table 61. ALS group 2 X2 Register
Addr: A2h
Bit
Bit Name
7:0
group2_x2
ALS group 2 X2
Default Access
00h
Description
R/W
Group 2 x2 value
Table 62. ALS group 2 K2 Register
Addr: A3h
Bit Name
7:0
group2_k2
Default Access
00h
ca
Bit
ALS group 2 K2
Group3
R/W
Description
Group 2 k2 value- value divided by 32 defines second slope
ni
Table 63. ALS group 3 Y0 Register
Addr: A4h
Bit Name
ch
Bit
ALS group 3 Y0
Default Access
group3_y0
7:0
00h
Description
R/W
Group 3 y0 value - divided by 256
Te
Table 64. ALS group 3 Y3 Register
Addr: A5h
Bit
Bit Name
7:0
group3_y3
ALS group 3 Y3
Default Access
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00h
Description
R/W
Group 3 y3 value - divided by 256
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 65. ALS group 3 X1 Register
Addr: A6h
Bit
Bit Name
7:0
group3_x1
ALS group 3 X1
Default Access
00h
Description
R/W
Group 3 x1 value
Addr: A7h
Bit
Bit Name
7:0
group3_k1
ALS group 3 K1
Default Access
00h
R/W
Description
Group 3 k1 value - divided by 1 defines first slope
Addr: A8h
7:0
group3_x2
Default Access
00h
Description
R/W
Group 3 x2 value
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Bit Name
ALS group 3 X2
lv
Table 67. ALS group 3 X2 Register
Bit
al
id
Table 66. ALS group 3 K1 Register
Table 68. ALS group 3 K2 Register
Addr: A9h
Bit
Bit Name
7:0
group3_k2
ALS group 3 K2
Default Access
00h
R/W
Description
Group 3 k2 value- value divided by 32 defines second slope
The output of the group selection circuit (after the S/H circuit) can be observed with following registers:
Table 69. ALS group output 1 Register
Addr: AAh
Bit
Bit Name
7:0
amb_group1
ALS group output 1
Default Access
00h
R
Description
Ambient Light Sensor Group 1 output register
Table 70. ALS group output 2 Register
Addr: ABh
Bit Name
7:0
amb_group2
Default Access
00h
ca
Bit
ALS group output 2
R
Description
Ambient Light Sensor Group 2 output register
Table 71. ALS group output 3 Register
Bit
Bit Name
ALS group output 3
Default Access
amb_group3
00h
ch
7:0
ni
Addr: ACh
R
Description
Ambient Light Sensor Group 3 output register
Te
The range selection interrupt threshold and interrupt enable is defined by following registers amb_range_int_high and
amb_range_int_low:
Table 72. ALS range high interrupt threshold Register
Addr: ADh
Bit
Bit Name
7:0
amb_range_int_high
ALS range high interrupt threshold
Default Access
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00h
R/W
Description
If the filter output amb_result >= amb_range_int_high then
an amb_too_high interrupt is asserted
If amb_range_int_high=0, the interrupt is disabled
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 73. ALS range low interrupt threshold Register
Addr: AEh
Bit
Bit Name
7:0
amb_range_int_low
ALS range low interrupt threshold
Default Access
00h
R/W
Description
If the filter output amb_result <= amb_range_int_low then
an amb_too_low interrupt is asserted
If amb_range_int_low=0, the interrupt is disabled
Table 74. Interrupt Status Register
Addr: AFh
Bit Name
Default Access
Description
lv
Bit
Interrupt Status
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id
The range selection generates an interrupt by pulling the pin INT low (if any of the register bit of Interrupt Status are
set, INT is pulled low(. When the register Interrupt Status is readout, the interrupt is automatically cleared:
Comparator for amb_result >= amb_range_int_high
amb_too_high
0
R/sC
0
not triggered
1
triggered
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0
1
Comparator for amb_result <= amb_range_int_low
amb_too_low
1
0
1
R/sC
0
not triggered
1
triggered
1. Read - self clear. The register automatically clears it content after readout. This avoids any lost interrupts.
8.4.7
DLS(=DBC) - Dynamic Luminance Scaling Input
The pins DLS1 and DLS2 can be used for dynamic backlight scaling input. Dynamic backlight scaling is used to reduce
the power of the backlight especially when showing dark picture contents on the display. The control unit to operate
DLS is the display processor sending a PWM signal to the AS3677 and in parallel changing the display content to compensate for a reduced brightness backlight.
The AS3677 can use the DLS (Dynamic Luminance Scaling) (also called DBC = Dynamic Backlight Control) in two different operating modes:
Te
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ni
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1. Digital DLS Mode - selected by dls_analog=0: The input signal from pins DLS1 and DLS2 are controlling the
current source directly. A logic ‘L’ switches off the selected current source and a logic ‘H’ enables the current
source with the configured current. This operating mode is compatible to the AS3676 processing of DLS.
2. Analog DLS Mode - selected by dls_analog=1: In this operating mode, the input signals form DLS1 and DLS2
are digitally filtered (two parallel filters are possible!) and smoothly controls the current through the selected
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Datasheet - D e t a i l e d D e s c r i p t i o n
current source(s). Therefore the output signal does not show any PWM signal and therefore reduces the noise
in noise sensitive systems - especially if the connection to the LED used long wires.
Note: For any current source, do not use DLS and the internal PWM generator (see PWM Generator on page 27) at
the same time.
Table 75. DLS Input Parameters
DLS input frequency
range
fDLS_FILTER
DLS internal filter 3dB
cutoff frequency
VIHDLS
High Level Input
Voltage
VILDLS
Low Level Input
Voltage
ILEAK
Input Leakage Current
1. For duty cycles >5%
pins DLS1 and DLS2 if
used for DLS (any bit set:
curr1_on_dls,
curr2_on_dls or
curr6_on_dls); pin DLS1 if
used for RGB1, RGB2 and
RGB3 (only ‘digital’ DLS)
Min
dls_analog=0
25
dls_analog=1
300
Typ
Max
Unit
1000
kHz
1
25000
dls_analog=1, low pass filter 4th order
1.38
pins DLS1 and DLS2
to VBAT or VSS
1
2
Hz
kHz
VBAT
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fDLS
Condition
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Parameter
lv
Symbol
-5
V
0.52
V
5
µA
Note: If using dls_analog=1, the minimum PWM ratio is limited by the LED performance. If the analog current is
reduced too much, it might result in unevenness of the display backlight (as the LEDs are usually not specified
at very low current operation).
RGB1, RGB2 and RGB3 can only use ‘digital’ DLS - the register dls_analog does have no influence.
The analog processing of the DLS signal works as follows (dls_analog=1):
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1. The input signal from pins DLS1 and DLS2 are feed into the digital filter. A logic ‘L’ is converted into ‘0.000’ and
a logic ‘H’ is converted into ‘1.000’.
2. The digital filter processes this signal. The filter itself is implemented as a 4th order low pass filter with fixed
coefficients. Its 3dB cut-off frequency is set to fDLS_FILTER.
3. The output signal (fixed comma binary 8 bit signal) is multiplied by the individual current setting.
4. From this 8 x 8 multiplication (16bit result), the 8 MSBs are used.
This value is converted with a current DAC into a current, which controls the LED.
8.4.8 Unused DLS Input Pins
ni
The pins DLS1 and DLS2 should be connected to VSS if not used.
8.4.9 DLS Internal Processing
Te
ch
The internal processing is shown in Figure 25:
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 25. DLS (Dynamic Luminance Scaling) internal circuit shown for a single current sink
12
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Table 76. DLS mode control1 Register
DLS mode control1
Te
Addr: 56h
Bit
Bit Name
4
rgb1_on_dls
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Default Access
Description
0
0
R/W
1
1
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1v3-1
RGB1 current sink is not combined with DLS
RGB1 current sink is combined with DLS (only
‘digital’ DLS with input pin DLS1)
42 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 76. DLS mode control1 Register (Continued)
DLS mode control1
Addr: 56h
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
5
rgb2_on_dls1
Default Access
Description
0
0
rgb3_on_dls
6
0
dls_analog
R/W
0
RGB2 current sink is not combined with DLS
1
RGB2 current sink is combined with DLS (only
‘digital’ DLS with input pin DLS1)
0
RGB3 current sink is not combined with DLS
1
1
RGB3 current sink is combined with DLS (only
‘digital’ DLS with input pin DLS1)
0
‘digital’ DLS for all current sinks
1
‘analog’ DLS for CURR1, CURR2 and CURR6 if
enabled
1
R/W
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7
R/W
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Bit Name
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Bit
1. When this bit is set, do not use the internal PWM generator for this current source at the same time.
Table 77. DLS mode control2 Register
DLS mode control2
Addr: 57h
Bit
Bit Name
0
curr1_on_dls
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Default Access
curr2_on_dls
1
Description
0
0
0
R/W
R/W
curr2_dls2
0
R/W
6
curr6_dls2
0
R/W
7
curr6_on_dls
ca
5
R/W
CURR1 current sink is not combined with DLS
1
CURR1 current sink is combined with DLS
0
CURR2 current sink is not combined with DLS
1
1
CURR2 current sink is combined with DLS
0
CURR2 uses DLS1 as input
1
CURR2 uses DLS2 as input
0
CURR6 uses DLS1 as input
1
CURR6 uses DLS2 as input
0
CURR6 current sink is not combined with DLS
1
1
CURR6 current sink is combined with DLS
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0
1
Te
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1. When this bit is set, do not use the internal PWM generator for this current source at the same time.
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Datasheet - D e t a i l e d D e s c r i p t i o n
8.5
General Purpose Input / Output
The pin DLS1, DLS2 are digital input, INT is an open drain output and ALS/GPIO1, GPIO2 and GPIO3 are a highlyconfigurable general purpose input/output pins which can be used for the following functionality:
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DLS1 and DLS2 primary function is a DLS input - see DLS(=DBC) - Dynamic Luminance Scaling Input on page 40
ALS/GPIO1 primary function is ALS input - see ALS - Ambient Light Sensing on page 32
Digital Schmitt Trigger Input
Digital Output with 4mA Driving Capability at 2.8V Supply (VANA)
Tristate Output
Analog Input to the ADC
Default Mode for ALS/GPIO1 is ADC input (as required for the ALS function), GPIO2 and GPIO3 is Input with PullDown
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Table 78. GPIO Pin Function Summary
GPIO3 Pin
Configuration
Additional Function
ALS/GPIO1
Digital Input, Totem-Pole Output (Push/Pull),
Open Drain (PMOS or NMOS), High-Z, PullDown or Pull-Up Resistor
ADC Input, ALS - light sensor input (see
page 32)
DLS1, DLS2
Digital Input
ADC Input, PWM Input, DLS input (see page
40)
Open Drain Output
ADC Input
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INT
ADC Input
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GPIO2, GPIO3
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 26. GPIOs and VANA Blockdiagram
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8.5.1 Unused GPIO and digital Input Pins
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If the pins ALS/GPIO1, GPIO2 or GPIO3 are not used, they can be left open (an internal pulldown, which is enabled by
default, will pull them to GND, ALS/GPIO1 is configured as ADC input). The pins DLS1 and DLS2 should be connected
to VSS, INT can be left open.
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8.5.2 GPIO and Digital Inputs Characteristics
Table 79. GPIO and digital inputs DC Characteristics
Symbol
Parameter
Condition
Min
Rpull
Pull up/Pull down
Resistance
enabled by gpio1_pulls,
gpio2_pulls and gpio3_pulls
VGPIO
Supply Voltage
=VANA
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1v3-1
Typ
Max
Unit
30
75
kΩ
1.8
3.35
V
45 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 79. GPIO and digital inputs DC Characteristics
Symbol
Parameter
VIHGPIO
High Level Input
Voltage
VILGPIO
Low Level Input
Voltage
VHYS
Hysteresis
ILEAK
Input Leakage Current
VOHGPIO
High Level Output
Voltage
Low Level Output
voltage
CLOAD
Unit
VANA
V
0.52
V
0.1
to VANA or VSS
-5
V
5
0.8·VANA
0.2·
VANA
0.2
Pin INT at 4mA
VANA = 2.8V,
gpio1_low_curr or
gpio2_low_curr or
gpio3_low_curr= 1
4
VANA = 2.8V,
gpio1_low_curr or
gpio2_low_curr or
gpio3_low_curr= 0
10
µA
V
at Iout
Driving Capability
IOUT
1.38
Max
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VOLINT
pins ALS/GPIO1, GPIO2 and
GPIO3
Typ
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Low Level Output
Voltage
Min
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VOLGPIO
Condition
V
mA
1
Capacitive Load
50
pF
1. Limited by LDO driving capability - see LDO on page 9
8.5.3
GPIO Registers
Table 80. GPIO output 2 Register
Addr: 50h
Bit Name
0
gpio1_out
1
gpio2_out
2
gpio3_out
This register controls GPIO3 outputs.
Default Access
Description
R/W
Writes a logic signal to pin ALS/GPIO1; this is independent
of any other bit setting e.g., gpio1_mode Table 82.
0
R/W
Writes a logic signal to pin GPIO2; this is independent of
any other bit setting e.g., gpio2_mode Table 82
0
R/W
Writes a logic signal to pin GPIO3; this is independent of
any other bit setting e.g., gpio3_mode Table 83
0
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ca
Bit
GPIO output 2
ch
Table 81. GPIO signal 2 Register
GPIO signal 2
Addr: 51h
Bit
Bit Name
This register controls GPIO3 outputs.
Default Access
Description
gpio1_in
N/A
R
Reads a logic signal from pin ALS/GPIO1; this is
independent of any other setting e.g.,Table 82 except
gpio1_pulls=11
1
gpio2_ in
N/A
R
Reads a logic signal from pin GPIO2; this is independent of
any other setting e.g.,Table 82 except gpio2_pulls=11
2
gpio3_ in
N/A
R
Reads a logic signal from pin GPIO3; this is independent of
any other setting e.g.,Table 83 except gpio3_pulls=11
Te
0
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Datasheet - D e t a i l e d D e s c r i p t i o n
Table 82. GPIO control Register
GPIO control
Addr: 1Eh
Bit
Bit Name
This register controls GPIO3 and GPIO31 pin functions.
Default Access
Description
Defines the direction for pin ALS/GPIO1
R/W
01
Output (push and pull)
10
Output (open drain, only push; only NMOS is
active)
11
Output (open drain, only pull; only PMOS is
active)
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00
Input only
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gpio1_mode
1:0
00
Adds the following pullup/pulldown to pin ALS/GPIO1; this
is independent of setting of bits gpio1_mode
None
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00
gpio1_pulls
3:2
11
R/W
01
Pulldown
10
Pullup
11
ADC input (gpio1_mode = XX); recommended
for analog signals
Defines the direction for pin GPIO2
gpio2_mode
5:4
00
R/W
00
Input only
01
Output (push and pull)
10
Output (open drain, only push; only NMOS is
active)
11
Output (open drain, only pull; only PMOS is
active)
Adds the following pullup/pulldown to pin GPIO2; this is
independent of setting of bits gpio2_mode
gpio2_pulls
01
R/W
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7:6
00
None
01
Pulldown
10
Pullup
11
ADC input (gpio2_mode = XX); recommended
for analog signals
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Table 83. GPIO control 3 Register
GPIO control 3
ch
Addr: 1Fh
Te
Bit
1:0
Bit Name
This register enables low current mode for GPIO3s.
Default Access
gpio3_mode
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Description
Defines the direction for pin GPIO3
00
R/W
00
Input only
01
Output (push and pull)
10
Output (open drain, only push; only NMOS is
active)
11
Output (open drain, only pull; only PMOS is
active)
1v3-1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 83. GPIO control 3 Register (Continued)
GPIO control 3
Addr: 1Fh
Bit
Bit Name
This register enables low current mode for GPIO3s.
Default Access
Description
Adds the following pullup/pulldown to pin GPIO3; this is
independent of setting of bits gpio3_mode
R/W
01
Pulldown
10
Pullup
11
ADC input (gpio3_mode = XX); recommended
for analog signals
Table 84. GPIO driving cap Register
Bit
GPIO driving cap
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Addr: 20h
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01
None
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gpio3_pulls
3:2
00
Bit Name
This register enables low current mode for GPIO3s.
Default Access
Description
Defines the driving capability of pin ALS/GPIO1
gpio1_low_curr
0
0
R/W
0
Iout
1
Iout /4
Defines the driving capability of pin GPIO2
gpio2_low_curr
1
0
R/W
0
Iout
1
Iout /4
Defines the driving capability of pin GPIO3
gpio3_low_curr
0
R/W
0
Iout
1
Iout /4
Te
ch
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ca
2
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Datasheet - D e t a i l e d D e s c r i p t i o n
8.6
LED Test
Figure 27. LED Function Testing
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The AS3677 supports the verification of the functionality of all the connected LEDs (open and shorted LEDs and short
to VSS can be detected). This feature is especially useful in production test to verify the correct assembly of the LEDs,
all its connectors and cables. It can also be used in the field to verify if any of the LEDs is damaged. A damaged LED
can then be disabled (to avoid unnecessary currents).
The current sources, dcdc converter, charge pump and the internal ADC are used to verify correct operation of each
LED string.
Function Testing for single LEDs connected to the Charge Pump
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8.6.1
ch
For any current source connected to the charge pump (CURR30-33) where only one LED is connected between the
charge pump and the current sink (see Figure 27) use:
Table 85. Function Testing for LEDs connected to the Charge Pump
Action
Example Code
1
Switch on the charge pump and set it into manual
1:2 mode (to avoid automatic mode switching
during measurements)
Reg 23h ≤ 14h (cp_mode = 1:2, manual)
Reg 00h ≤ 04h (cp_on = 1)
2
Switch on the current sink for the LED to be tested
e.g. for register CURR31set to 9mA use
Reg 0Dh ≤ 5Ah (rgb1_current = 9mA)
Reg 02h ≤ 01h (rgb1_mode = on)
3
Measure with the ADC the voltage on CPOUT
Reg 26h ≤ 95h (adc_select=CPOUT,start ADC)
Fetch the ADC result from Reg 27h and 28h
Te
Step
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Datasheet - D e t a i l e d D e s c r i p t i o n
Table 85. Function Testing for LEDs connected to the Charge Pump
Action
Example Code
4
Measure with the ADC the voltage on the switched
on current sink
Reg 26h ≤ 85h (adc_select=RGB1,start ADC)
Fetch the ADC result from Reg 27h and 28h
5
Switch off the current sink for the LED to be tested
Reg 02h ≤ 00h (rgb1_mode = off)
6
Compare the difference between the ADC
measurements (which is the actual voltage across
the tested LED) against the specification limits of
the tested LED
Calculation performed in baseband uProcessor
7
Do the same procedure for the next LED starting
from point 2
Jump to 2. If not all the LEDs have been tested
8
Switch off the charge pump
set charge pump automatic mode
Reg 00h ≤ 00h (cp_on = 0)
Reg 23h ≤ 00h
Function Testing example for LEDs connected to the DCDC
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Use following procedure as an example:
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8.6.2
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Step
Table 86. Function Testing procedure for LEDs connected to the DCDC
Action
Example Code
1
Switch on one current sink (only one!) for the LED
string to be tested (CURR1,2 or 6) - this example
uses CURR1
e.g. Test LEDs on CURR1:
Reg 01h ≤ 01h (curr1_mode=on)
Reg 09h ≤ 3ch (curr1_current = 9mA)
2
Select the feedback path for the LED string to be
tested (e.g. step_up_fb = 01 for LED string on
CURR1) and disable automatic feedback
Reg 21h ≤ 02h (step_up_fb=CURR1)
Reg 22h <- 04h (step_up_fb_auto=off)
3
Set step_up_vmax to fit the external components
used (e.g. max 16V)
Reg 21h <- 00h (for 16V maximum output voltage)
4
Switch on the DCDC converter
Reg 00h ≤ 08h
5
Wait 2ms (dcdc startup time and some margin)
6
Measure the voltage on CURR1
Reg 26h ≤ 98h (adc_select=CURR1, start ADC;
Fetch the ADC result from Reg 27h and 28h)
7
If the voltage on CURR1 is below 1.0V but above
0.1V, this LED string is working fine (typical value
will be at 0.5V)
For a proper working LED result must be below
<199h (1.0V) and above >29h (0.1V)
8
Switch off current sink CURR1
Reg 01h ≤ 00h (curr1_mode=off)
9
ca
Step
Repeat whole procedure for each used LED string
(replace CURR1 with CURR2 or CURR6)
8.7
ni
Note: With the above described procedures electrically open and shorted LEDs can be automatically detected
Analog-to-Digital Converter
Te
ch
The AS3677 has a built-in 10-bit successive approximation analog-to-digital converter (ADC). It is internally supplied
which is also the full-scale input range (0V defines the ADC zero-code). For input signals exceeding 2.5V a resistor
divider with a gain of 0.5 (Ratioprescaler) is used to scale the input of the ADC converter. Consequently the resolution
is:
Table 87. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
VLSB
Note
ALS/GPIO1, GPIO2, GPIO3 and
VANA, DLS1, DLS2
0V-2.5V
2.44mV
VLSB=2.5/1024
ADCTEMP_CODE
-30°C to 125°C
1 / ADCTC
junction temperature
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 87. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
VLSB
Note
VBAT, CPOUT, RGB1, RGB2, RGB3
0V-5V
4.88mV
VLSB=(2.5/1024)/0.4; internal
resistor divider used
CURR1, CURR2, CURR6
0V-1.0V
2.44mV
VLSB=2.5/1024
Symbol
Parameter
Condition
Min
Resolution
Typ
10
Max
Unit
Bit
see
Table
87
VIN
Input Voltage Range
VSS
DNL
Differential NonLinearity
INL
Integral Non-Linearity
Vos
Input Offset Voltage
Rin
Input Impedance
Cin
Input Capacitance
VSUPPLY
Power Supply Range
± 2%, internally trimmed.
2.5
V
Idd
Power Supply Current
During conversion only.
286
µA
TTOL
Temperature Sensor
Accuracy
@ 25 °C
ADCTOFFSET
ADC temperature
measurement offset
value
ADCTC
Code temperature
coefficient
RatioPRESCALE
Ratio of Prescaler
± 0.25
LSB
± 0.5
LSB
± 0.25
LSB
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R
V
lv
VSUPPLY = 2.5V
al
id
Table 88. ADC Parameters
100
9
-10
+10
MΩ
pF
°C
375
°C
Temperature change per ADC LSB
1.293
9
°C/
Code
For all low voltage current sinks, CPOUT
and VBAT
0.4
Transient Parameters (2.5V, 25 ºC)
Tc
Conversion Time
Clock Frequency
ts
Settling Time of S&H
ca
fc
All signals are internally generated and
triggered by start_conversion
27
µs
1.0
MHz
16
µs
ni
The junction temperature (TJUNCTION) can be calculated with the following formula (ADCTEMP_CODE is the adc conversion result for channel 17h selected by register adc_select = 010111):
TJUNCTION [°C] = ADCTOFFSET - ADCTC · ADCTEMP_CODE
(EQ 1)
ch
ADC Registers
Table 89. ADC_MSB result Register
Te
Addr: 27h
Bit
Bit Name
6:0
adc_result_msb
ADC_MSB result
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
Default Access
www.austriamicrosystems.com/AS3677
N/A
Description
R
ADC results register.
1v3-1
51 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 89. ADC_MSB result Register (Continued)
ADC_MSB result
Addr: 27h
Bit
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
Bit Name
Default Access
Description
Indicates end of ADC conversion cycle
N/A
R
0
Result is ready
1
Conversion is running
Table 90. ADC_LSB result Register
lv
ADC_LSB result
Addr: 28h
al
id
result_not_ready
7
Together with Register 28h, this register contains the results (LSB) of an ADC
cycle
Bit Name
2:0
adc_result_lsb
Default Access
Description
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Bit
N/A
R
ADC result register
Table 91. ADC_control Register
Addr: 26h
Bit
ADC_control
This register input source selection and initialization of ADC
Bit Name
Default Access
Description
Selects input source as ADC input
1
5:0
02h
R/W
Te
ch
ni
ca
adc_select
7
start_conversion
N/A
W
000000 (00h)
GPIO2
000001 (01h)
VANA
000010 (02h)
ALS/GPIO1
000100 (04h)
GPIO3
000101 (05h)
RGB1
000110 (06h)
RGB2
000111 (07h)
RGB3
001000 (08h)
CURR1
001001 (09h)
CURR2
010001 (11h)
DLS1
010010(12h)
DLS2
010011 (13h)
CURR6
010100 (14h)
VBAT
010101 (15h)
CPOUT
010111 (17h)
ADCTEMP_CODE (junction temperature)
other codes
reserved
Writing a 1 into this bit starts one ADC conversion cycle.
1. See Table Table 87 for ADC ranges and resolution.
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 28. ADC Circuit
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AS3677
Power-On Reset
The internal reset is controlled by two sources:
VBAT Supply
Serial interface state (CLK, DATA)
The internal reset is forced if VBAT is low or if both interface pins (CLK, DATA) are low for more than tPOR_DEB (typ.
5
100ms) . Then device enters shutdown mode. For details see section Operating Modes on page 58.
Te
ch
ni
ca
The reset levels control the state of all registers. As long as VBAT and CLK/DATA are below their reset thresholds, the
register contents are set to default. Access by serial interface is possible once the reset thresholds are exceeded.
5. Only if shutdwn_enab=1
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 29. Zero Power Device Wakeup block diagram
AS3677
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Table 92. Power On Reset Parameters
Symbol
Parameter
Condition
VPOR_VBAT
Overall Power-On
Reset
Monitor voltage on VBAT; power-on reset for
all internal functions.
2.0
V
VPOR_PERI
Reset Level for pins
CLK, DATA
Monitor voltage on pins CLK, DATA
1.0
V
tPOR_DEB
Reset debounce time
for pins CLK, DATA
100
ms
tstart
Interface Startup Time
6
ms
8.8.1
Min
Typ
Max
Unit
Reset control register
ca
Table 93. Overtemp control Register
Addr: 29h
ni
Bit Name
shutdwn_enab
Description
Enable Shutdown mode and serial interface reset.
1
R/W
0
Serial Interface reset disabled. Device does not
enter Shutdown mode
1
Serial Interface reset enabled, device enters
shutdown when SCL and SDA remain low for
min. 100ms
Te
4
This register reads and resets the overtemperature flag.
Default Access
ch
Bit
Overtemp control
8.9
Temperature Supervision
An integrated temperature sensor provides over-temperature protection for the AS3677. This sensor generates a flag
if the device temperature reaches the overtemperature threshold of 140º. The threshold has a hysteresis to prevent
oscillation effects.
If the device temperature exceeds the T140 threshold all current sources, the charge pump and the dcdc converter is
disabled and the ov_temp flag is set. After decreasing the temperature by THYST operation is resumed.
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the register bit rst_ov_temp.
Bit ov_temp_on = 1 activates temperature supervision Table 95. It is recommend to leave this bit set (default state).
Table 94. Overtemperature Detection
Parameter
T140
ov_temp Rising
Threshold
Condition
Min
140
ºC
THYST
ov_temp Hysteresis
5
ºC
Table 95. Overtemp control Register
Overtemp control
Addr: 29h
Max
Unit
This register reads and resets the overtemperature flag.
Bit Name
Description
Default Access
lv
Bit
Typ
al
id
Symbol
Activates/deactivates device temperature supervision.
Default: Off - all other bits are only valid if this bit is set to 1
0
Temperature supervision is disabled. No reset
will be generated if the device temperature
exceeds 140ºC
1
Temperature supervision is enabled
1
Indicates that the overtemperature threshold
has been reached; this flag is not cleared by an
overtemperature reset. It has to be cleared
using rst_ov_temp
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st
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ov_temp_on
0
1
W
1
ov_temp
N/A
R
2
rst_ov_temp
0
R/W
8.10
Serial Interface
The ov_temp flag is cleared by first setting this bit to 1, and
then setting this bit to 0.
The AS3677 is controlled using serial interface pins CLK and DATA:
Figure 30. Serial interface block diagram
ca
Te
ch
ni
AS3677
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1v3-1
55 - 67
AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
The clock line CLK is never held low by the AS3677 (as the AS3677 does not use clock stretching of the bus).
Table 96. Serial Interface Voltages and Timings
Parameter
VIHI/F
High Level Input
Voltage
VILI/F
Low Level Input
Voltage
Condition
Min
Max
Unit
1.38
VBAT
V
0.0
0.52
V
Pins DATA and CLK
VHYSTI/F
Hysteresis
tRISE
Rise Time
0
tFALL
Fall Time
0
VOL
Low Level Output
voltage
tCLK_FILTER
Spike Filter on CLK
tDATA_FILTER
Spike Filter on DATA
Typ
0.1
V
1000
ns
300
ns
0.2
V
lv
Pin DATA at 4mA
al
id
Symbol
ns
300
ns
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st
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100
The AS3677 is compatible to the NXP two wire specification http://www.nxp.com/acrobat_download/literature/9398/
39340011.pdf, Version 2.1, January 2000 for standard and fast mode (no high speed mode).
8.10.1 Serial Interface Features
Fast Mode Capability (Maximum Clock Frequency is 400 kHz)
7-bit Addressing Mode
Write Formats
- Single-Byte Write
- Page-Write
Read Formats
- Current-Address Read
- Random-Read
- Sequential-Read
DATA Input Delay and CLK spike filtering by integrated RC components
8.10.2 Device Address Selection
The serial interface address of the AS3677 has the following address:
ca
If ADR is connected to VSS: 80h – Write Commands, 81h – Read Commands
If ADR is connected to VBAT: 82h – Write Commands, 83h – Read Commands
ch
DATA
ni
Figure 31. Complete Serial Data Transfer
Te
CLK
S
Start
Condition
1-7
Address
8
9
R/W
ACK
1-7
8
Data
9
ACK
1-7
Data
8
9
ACK
P
Stop
Condition
Serial Data Transfer Formats
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Definitions used in the serial data transfer format diagrams are listed in the following table:
Table 97. Serial Data Transfer Byte Definitions
Definition
R/W (AS3677 Slave)
Note
S
Start Condition after Stop
R
1 bit
Sr
Repeated Start
R
1 bit
DW
Device Address for Write
R
10000000b (80h) ADR=VSS
10000010b (82h) ADR=VBAT
DR
Device Address for Read
R
10000001b (81h) ADR=VSS
10000011b (83h) ADR=VBAT
WA
Word Address
R
8 bits
A
Acknowledge
W
1 bit
N
Not Acknowledge
R
reg_data
Register Data/Write
R
data (n)
Register Data/read
R
Stop Condition
R
8 bits
Increment Word Address Internally
R
During Acknowledge
WA++
lv
1 bit
8 bits
1 bit
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st
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P
al
id
Symbol
Figure 32. Serial Interface Byte Write
S
DW
A
WA
A
reg_data
A P
Write Register
WA++
AS3675 (= Slave) receives data
AS3675 (= Slave) transmits data
Figure 33. Serial Interface Page Write
S
DW
A
WA
A
reg_data 1
A
reg_data 2
Write Register
WA++
A
…
Write Register
WA++
reg_datan
A P
Write Register
WA++
ca
AS3675 (= Slave) receives data
AS3675 (= Slave) transmits data
Byte Write and Page Write formats are used to write data to the slave.
ni
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write address is followed by the word address. After the word address any number of data
bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on
subsequent address locations.
Te
ch
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register
byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave.
The word address is incremented internally.
The following diagrams show the serial read formats supported by the AS3677.
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 34. Serial Interface Random Read
S
DW
A
WA
A Sr
DR
A
data
N P
Read Register
WA++
AS3675 (= slave) receives data
AS3675 (= slave) transmits data
al
id
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
lv
In order to change the data direction a repeated START condition is issued on the 1st CLKpulse after the ACKNOWLEDGE bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master
responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP condition on the bus.
S
DW
A
am
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nt
st
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Figure 35. Serial Interface Sequential Read
WA
A Sr
DR
A
data 1
A
data 2
...
data n
A
N P
Read Register
WA++
AS3675 (= slave) receives data
AS3675 (= slave) transmits data
Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently transferred.
In contrast to the Random Read, in a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the
word-address counter). To terminate the transmission the master has to send a NOT ACKNOWLEDGE following the
last data byte and subsequently generate the STOP condition.
Figure 36. Serial Interface Current Address Read
S
DR
A
data 1
Read Register
WA++
A
data 2
Read Register
WA++
…
A
data n
N P
Read Register
WA++
ca
AS3675 (= slave) receives data
AS3675 (= slave) transmits data
ni
To keep the access time as small as possible, this format allows a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
address.
ch
Analogous to Random Read, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st register
byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes must
be responded to with an ACKNOWLEDGE from the master.
Te
For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a subsequent STOP condition.
8.11
Operating Modes
If the voltages on CLK and DATA is less than VPOR_PERI for > tPOR_DEB (see Table 92 on page 54), the AS3677 is in
shutdown mode and its current consumption is minimized (IBAT = ISHUTDOWN) and all internal registers are reset to their
default values.
If the voltage at CLK or DATA rises above VPOR_PERI, the AS3677 serial interface is enabled and the AS3677 and the
standby mode is selected. The AS3677 is switched automatically from standby mode (IBAT = ISTANBY) into active mode
(IBAT = IACTIVE) and back, if one of the following blocks are activated:
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AS3677
Datasheet - D e t a i l e d D e s c r i p t i o n
al
id
Charge pump
Step up regulator
Any current sink
ADC conversion started
PWM active
Pattern mode active.
If any of these blocks are already switched on the internal oscillator is running and a write instruction to the registers is
directly evaluated within 1 internal CLK cycle (typ. 1µs)
If all these blocks are disabled, a write instruction to enable these blocks is delayed by 64 CLK cycles (oscillator will
startup, within max 200µs).
The mode switching is shown in Figure 37:
lv
Figure 37. Startup and Operating Mode Selection
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1v3-1
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AS3677
Datasheet - R e g i s t e r M a p
9 Register Map
Table 98. Registermap
Addr
Default
Reg control
00h
00
curr12 control
01h
00h
curr rgb control
02h
00h
LDO Voltage
07h
00h
Curr1 current
09h
00h
curr1_current
Curr2 current
0Ah
00h
curr2_current
Rgb1 current
0Bh
00h
rgb1_current
Rgb2 current
0Ch
00h
rgb2_current
Rgb3 current
0Dh
00h
rgb3_current
Pwm control
16h
00h
Pwm code
17h
00h
Pattern control
18h
00h
Pattern data0
19h
00h
pattern_data_0
Pattern data1
1Ah
00h
pattern_data_1
Pattern data2
1Bh
00h
pattern_data_2
Pattern data3
1Ch
00h
pattern_data_3
GPIO control
1Eh
4Ch
GPIO control 3
1Fh
04h
GPIO driving cap
20h
00h
DCDC control1
21h
02h
DCDC control2
22h
88h
CP control
23h
40h
cp_start cp_mode_switchin
cp_auto _deboun
_on
g
ce
CP mode Switch1
24h
70h
rgb3_on rgb2_on rgb1_on
_cp
_cp
_cp
b6
curr6_mode
b5
b4
b2
step_up
_on
cp_on
rgb3_mode
b1
b0
ldo_on
curr2_mode
curr1_mode
rgb2_mode
rgb1_mode
ldo_voltage
am
lc s
on A
te G
nt
st
il
pwm_dim_speed
pwm_dim_mode
pwm_code
softdim_
pattern
gpio2_pulls
gpio2_mode
pattern_delay
pattern_
color
gpio1_pulls
gpio1_mode
gpio3_pulls
gpio3_mode
gpio3_lo gpio2_lo gpio1_lo
w_curr
w_curr
w_curr
ca
step_up_vmax
step_up
_fb_auto
ch
step_up
_ov
CP mode Switch2
25h
00h
curr6_on
_cp
ADC_control
26h
02h
start_co
nversion
ADC_MSB result
27h
NA
result_n
ot_ready
ADC_LSB result
28h
NA
Overtemp control
29h
11h
shutdwn
_enab
Curr low voltage
status1
2Ah
NA
curr6_lo rgb3_low rgb2_low rgb1_low
w_v
_v
_v
_v
Te
b3
al
id
b7
ni
Name
Content
lv
Register
Definition
step_up_fb
step_up
_lowcur
step_up
_frequ
skip_fast
cp_mode
cp_clk
curr2_on curr1_on
_cp
_cp
adc_select
adc_result_msb
adc_result_lsb
www.austriamicrosystems.com/AS3677
1v3-1
rst_ov_t
ov_temp ov_temp
emp
_on
60 - 67
AS3677
Datasheet - R e g i s t e r M a p
Table 98. Registermap
Addr
Default
Register
Definition
Curr low voltage
status2
2Bh
NA
Gpio current
2Ch
80h
Curr6 current
2Fh
00h
curr6_current
Adder Current 1
30h
00h
adder_current1
(can be enabled for CURR1)
Adder Current 2
31h
00h
adder_current2
(can be enabled for CURR2)
Adder Current 3
32h
00h
adder_current3
(can be enabled for CURR6)
Adder Enable 1
33h
00h
rgb3_ad rgb2_ad rgb1_ad
der
der
der
Adder Enable 2
34h
00h
curr6_ad curr2_ad curr1_ad
der
der
der
ASIC ID1
3Eh
A6h
1
0
1
0
ASIC ID2
3Fh
5Xh
0
1
0
1
GPIO output 2
50h
00h
gpio3_o
ut
GPIO signal 2
51h
00h
gpio3_ in gpio2_ in gpio1_in
Pattern End
54h
00h
pattern_
end
DLS mode
control1
56h
00h
dls_anal rgb3_on rgb2_on rgb1_on
og
_dls
_dls1
_dls
DLS mode
control2
57h
00h
curr6_on curr6_dl
_dls
s2
ALS control
90h
00h
ALS filter
91h
00h
ALS offset
92h
00h
amb_offset
ALS result
93h
00h
amb_result
ALS curr12 group
94h
00h
b5
b4
b1
b0
curr2_lo
w_v
curr1_lo
w_v
pattern_
delay2
0
1
ca
gpio1_o
ut
amb_on
amb_filter_up
rgb3_amb_group
curr2_amb_group
curr1_amb_group
rgb2_amb_group
rgb1_amb_group
00h
ALS group 1 Y0
98h
00h
group1_y0
ch
95h
ALS group 1 Y3
99h
00h
group1_y3
ALS group 1 X1
9Ah
00h
group1_x1
ALS group 1 K1
9Bh
00h
group1_k1
ALS group 1 X2
9Ch
00h
group1_x2
ALS group 1 K2
9Dh
00h
group1_k2
ALS group 2 Y0
9Eh
00h
group2_y0
ALS group 2 Y3
9Fh
00h
group2_y3
ALS group 2 X1
A0h
00h
group2_x1
1v3-1
gpio2_o
ut
amb_gain
amb_filter_down
www.austriamicrosystems.com/AS3677
0
curr2_on curr1_on
_dls
_dls
curr2_dl
s2
amb_ke
ep
curr6_amb_group
1
revision
ALS rgb group
Te
b2
am
lc s
on A
te G
nt
st
il
pattern_
slow
b3
al
id
b6
lv
b7
ni
Name
Content
61 - 67
AS3677
Datasheet - R e g i s t e r M a p
Table 98. Registermap
Addr
Default
ALS group 2 K1
A1h
00h
group2_k1
ALS group 2 X2
A2h
00h
group2_x2
ALS group 2 K2
A3h
00h
group2_k2
ALS group 3 Y0
A4h
00h
group3_y0
ALS group 3 Y3
A5h
00h
group3_y3
ALS group 3 X1
A6h
00h
group3_x1
ALS group 3 K1
A7h
00h
group3_k1
ALS group 3 X2
A8h
00h
group3_x2
ALS group 3 K2
A9h
00h
group3_k2
ALS group output
1
AAh
00h
amb_group1
ALS group output
2
ABh
00h
amb_group2
ALS group output
3
ACh
00h
amb_group3
ALS range high
interrupt threshold ADh
00h
amb_range_int_high
ALS range low
interrupt threshold AEh
00h
amb_range_int_low
Interrupt Status
b6
b5
b4
b3
b2
b1
b0
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Name
Content
lv
Register
Definition
AFh
amb_too amb_too
_low
_high
00h
Note: If writing to register, write 0 to unused bits
Write to read only bits will be ignored
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yellow color = read only
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1v3-1
62 - 67
AS3677
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
10 Application Information
10.1
External Components
Table 99. External Components List
Value
Typ
Min
C1
Max
2.2µF
tol.
(min.)
±20%
Package
1
(min.)
Rating
(max)
Notes
6.3V
Ceramic, X5R (Vana1 output)
(e.g. Taiyo Yuden
JMK107BJ225MA-T or
LMK107BJ225MA)
only required if LDO is used
0603
1206
(0805)
3.2x1.6x0.
85mm
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Part Number
4.7µF
±20%
25V
C3
100nF
±20%
6.3V
Ceramic, X5R (LDO output
capacitor) (e.g. Taiyo Yuden
JMK063BJ104KP-F)
0402
470nF
±20%
6.3V
Ceramic, X5R (Charge Pump
flying capacitor) (e.g. Taiyo
Yuden JMK105BJ474KV-F)
0402
1µF
±20%
6.3V
Ceramic, X5R (Charge Pump
output) (e.g. Taiyo Yuden
JMK105BJ105KV-F)
0402
DATA Pullup resistor – usually
already inside master
0201
CLK Pullup resistor – usually
already inside master
0201
Recommended Type:
Murata LQH3NPN100NJ0 or
Panasonic ELLSFG100MA
or TDK VLF3012A or Taiyo
Yuden NRH3012T100MN
(7µH min. at 600mA)
3x3x
1.2mm (H
is max)
Schottky diode
SOT666
1.6x1.6x0.
6mm
Light Sensor
e.g. Rohm BH1620FVC or
Toshiba TPS856
1.6x1.6x
0.55mm
LED
As required by application
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C2
Ceramic, X5R, X7R (Step Up
DCDC output)
(e.g. Taiyo Yuden
TMK316BJ475KD)
C4
C5
R1
1-10kΩ
R2
L1
10µH
PMEG4010BEA
ca
D1
±20%
X1
ni
D2:D10
1. in 1/100 inch (unless otherwise specified)
Layout Recommendations
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10.2
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1. GND Planes: Connect the VSS pins (B4, B5) to the low noise GND-plane.
VSS_DCDC (A4) should be connected to a separated GND-plane. Connect also the charge pump output
capacitor (C5) and the DCDC-caps (C1, C2) to this separated GND-plane. Connect all other blocking caps to
the low noise GND-plane. Keep the area of the separated GND plane as small as possible and connect it to
the star point of the low noise GND plane. Do not connect VSS (B4, B5) directly to VSS_DCDC (A4).
2. Supplies: The pins VBAT (B3) and VBAT_CP (A3) can be connected directly together. Put a blocking Cap
close to VBAT_CP.
3. DCDC: Put L1, D1, C1 and C2 close together and also close to the pins SW (A5) and VSS_DCDC (A4).
4. LDO: Put C3 close to pin VANA (C1)
www.austriamicrosystems.com/AS3677
1v3-1
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AS3677
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
11 Package Drawings and Markings
Figure 38. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Package Drawing
"
"
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AS3677
<Code>
!
"
"
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Line 1:
Line 2:
Line 3:
!
Note:
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AS3677
<Code>
Encoded datecode 4 characters
Figure 39. WL-CSP25 2.2x2.2x0.6mm 5x5 Balls Detail Dimensions
#$%
&$'
%
*
*
+
+
%)
%
%
%
%
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%
%
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)
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*
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+
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+
+
,
,
,
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,
,
+
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)
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The coplanarity of the balls is 40µm.
www.austriamicrosystems.com/AS3677
1v3-1
64 - 67
12mm
8mm
NOMINAL
HUB WIDTH
24.8
16.8
12.8
8.8
1 -.4
38.2
30.2
22.2
18.2
14.2
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16mm
32.8
DECIMAL
(EXCEPT AS NOTED)
TOLERANCES
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MATTE FINISH THESE AREAS
330.0 REF
24mm
50.2
W 2 MAX
32mm
44.8
62.2
102.0 REF
W1 (MEASURED AT HUB)
NO.
DESCRIPTION
- All Dimensions in Millimeters -
U.S. PATENT 4726534
W2 (MEASURED AT HUB)
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U.S. PAT. 4726534
+ .6
44mm
56.8
ni
LOCK FEATURE 6 PLACES
LOKREEL
MINNEAPOLIS, USA
W
56mm
9/11/96
NONE
DATE
ASSEMBLED 330mm LOKREEL, 4" HUB
SCALE
DATE
DRAWN BY
CHK'D
APP'D
T.S.
TRACED
MATERIAL
N/A
DRAWING NO.
A0911-96-1
BY
65 - 67
1v3-1
www.austriamicrosystems.com/AS3677
SEE DETAIL "A"
Ø20.2 MIN
0.5
Ø13.0+-0.2
±
FRACTIONAL
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Tape & Reel Information
11.1
2.0±0.5
DETAIL "A"
±
ANGULAR
±
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AS3677
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 40. Tape & Reel Dimensions
AS3677
Datasheet - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 100.
Table 100. Ordering Information
Description
Delivery Form
Package
AS3677-ZWLT
AS3677
Wafer Level Chip Scale Package,
size 2.2x2.2x0.6mm, 5x5 balls, 0.4mm pitch,
Green, Pb-Free
Tape & Reel
25pin WL-CSP
(2.2x2.2x0.6mm)
RoHS compliant / Pb-Free
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AS3677Z
Temperature Range: -30ºC - 85ºC
WL Package: Wafer Level Chip Scale Package (WL-CSP) 2.2x2.2x0.6mm
T
Delivery Form: Tape & Reel
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Note: AS3677-ZWLT
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Model
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1v3-1
66 - 67
AS3677
Datasheet - O r d e r i n g I n f o r m a t i o n
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
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All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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Contact Information
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Headquarters
austriamicrosystems AG
Te
Tobelbaderstrasse 30
Schloss Premstaetten
A-8141 Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com/AS3677
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