RD151TS501US PLL clock generator series REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Description RD151TS501US is phase-locked loop clock generator with high-performance. And RD151TS501US is low-jitters and will enable high density mounting by shrink small-size package (SSOP-8). Features • Input frequency: • Output frequency: 27.0 to 36.0 MHz 54.0 to 72.0 MHz (1 : 2), 67.5 to 72.0 MHz (1 : 2.5) 27.0 to 36.0 MHz (1 : 1), 33.75 to 36.0 MHz (1 : 1.25) (Selectable) Key Specifications • • • • • • • Supply voltages: VDD = 2.7 to 3.6 V Operating temperature = -10 to 75 °C Cycle to cycle jitter = ±75 ps typ. Clock output duty cycle = 50±5% Stabilization time: 2ms max Power-down mode is supported Ordering Information Part Name Package Type Package Code (Previous Package Code) Package Abbreviation Taping Abbreviation (Quantity) RD151TS501USE SSOP-8 pin PVSP0008KA–A (TTP-8DBV) US E (3,000 pcs / Reel) Pin Arrangement VDD 1 8 DIV2 VDD 2 7 IN VSS 3 6 SEL OUT 4 5 PDWN (Top view) REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 1 of 6 RD151TS501US Block Diagram VDD VSS 1/M IN DIV Synthesizer OUT Rpd = 100 kΩ 1/N PDWN Rpd = 100 kΩ SEL Rpd = 100 kΩ DIV2 Rpd = 100 kΩ Pin Descriptions Pin name VDD VSS OUT PDWN SEL IN DIV2 Note: No. 1,2 3 4 5 6 7 8 Type Power Ground Output Input Input Input Input Description Power supply GND Clock signal output Power-down control *1 Frequency select *1 Clock signal input *1 Frequency select *1 1. LVCMOS level input. Pull-down by internal resistor (100 kΩ). Power-down Function Table PDWN L H Note: IC Operating Power-down Active OUTPUT Low level Clock signal output Remark Default *1 1. All Circuits are set stand-by condition. Clock Frequency Table Note: SEL DIV2 Output Frequency (IN:OUT Ratio) L H L H L L H H 54.0 to 72.0 MHz (1:2) 67.5 to 72.0 MHz (1:2.5) 27.0 to 36.0 MHz (1:1) 33.75 to 36.0 MHz(1:1.25) 1. In case of selection of “SEL = H”, input frequency is limited 27 to 28.8 MHz. REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 2 of 6 Remark Default *1 *1 RD151TS501US Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Input clamp current *1 Output clamp current *1 Continuous output current Maximum power dissipation Storage temperature Symbol VDD VI VO IIK IOK IO PW Tstg Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDD+0.5 –50 –50 ±50 0.2 –65 to +150 Unit V V V mA mA mA W °C Conditions VI < 0 VO < 0 VO = 0 to VDD Ta = 25°C (in still air) Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage DC input signal voltage VDD 2.7 –0.3 3.3 — 3.6 VDD+0.3 V V Operating temperature Ta –10 — 75 °C Conditions DC Electrical Characteristics Ta = –10 to 75 °C, VDD = 2.7 to 3.6 V Item Input voltage Input current Input capacitance Output voltage Output current Symbol VIL VIH Min — 2.0 Typ — — Max 0.8 — Unit V V II — — ±100 µA CI VOL — — 3 — — 0.5 pF VOH VDD–0.2 — VDD IOL — 15 — mA IOH — –15 — mA — 30 — Ω 80 k 100 k 120 k Ω Output impedance Pull-down resister Note: Rpd V Test Conditions IN, PDWN, SEL, DIV2 pins IN, PDWN, SEL, DIV2 pins VI = 0 V or 3.6 V, IN, PDWN, SEL, DIV2 pins IN, PDWN, SEL, DIV2 pins VOL = 1 mA, VDD = 3.3 V, OUT pin VOH = –1 mA, VDD = 3.3 V, OUT pin VOL = 1.65 V, VDD = 3.3 V, OUT pin VOH = 1.65 V, VDD = 3.3 V, OUT pin OUT pin The condition of the minimum and maximum value must use the value specified under “Recommended Operating Conditions”. Parameters are target of design. Not 100% tested in production. REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 3 of 6 RD151TS501US AC Electrical Characteristics Ta = –10 to 75 °C, VDD = 2.7 to 3.3 V, CL = 15 pF Item Symbol Min Typ Max Unit IDD — 10 17 mA IDDPD tCCJ — — –50 0.7 45 — 15 |75| — 1.5 50 — 35 — 50 6.0 55 2 µA ps ppm ns % ms Operating current Stand-by current Cycle to cycle jitter Frequency accuracy Rise time / Fall time Clock duty cycle Stabilization time tr / tf tDT tSB Test Conditions Notes VDD= 3.3 V, PDWN = 1, CL = 0 pF, fout = 72MHz VDD = 3.3 V, PDWN = 0, IN = 0 V CL = 0 pF Figure 1 *1 VDD = 3.3 V, 0.2VDD to 0.8VDD *2 Notes: Parameters are target of design. Not 100% tested in production. 1. The accuracy of the output frequency to a set value. 2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. OUT tcycle n tcycle n+1 tCC = (tcycle n) – (tcycle n+1) Figure 1 Cycle to cycle jitter DIV2 fout fout/2 OUT f f f f f/2 f /2 Figure 2 Timing chart REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 4 of 6 f/2 f f ... RD151TS501US Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Figure 3. VDD decoupling is important to reduce Jitter performance. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. VDD C2 C1 GND GND GND OUT Notes: DIV2 1 8 2 7 3 6 SEL 4 5 PDWN IN R1 C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF recommended) R1 = Match value to line impedance. (Please use R1 if nessesarry) Figure 3 Recommended circuit configuration Remark for use Please do not use the pull-up resistance for the OUT terminal to prevent wrong operation of IC. REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 5 of 6 RD151TS501US Package Dimensions JEITA Package Code P-VSSOP8-2.3x2-0.50 RENESAS Code PVSP0008KA-A Previous Code TTP-8DB/TTP-8DBV MASS[Typ.] 0.010g D F 1.5 ±0.2 8 5 bp c HE E c1 b1 Terminal cross section L1 4 bp A1 ( 0.17 ) e A2 1 Detail F REJ03D0897-0102 Rev.1.02 Apr 25, 2007 Page 6 of 6 Reference Dimension in Millimeters Symbol Min Nom Max D 1.8 2.0 2.2 E 2.2 2.3 2.4 A2 0.6 0.7 0.8 A1 0.1 0 A bp 0.15 0.22 0.3 b1 0.20 c 0.08 0.13 0.23 c1 0.11 θ HE 2.8 3.1 3.4 e (0.5) x y Z L L1 (0.4) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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