ROHM BU9847GUL-W

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◇ STRUCTURE
Silicon Monolithic Integrated Circuit
◇ PRODUCT
I2C BUS 4Kbit (512×8bit) EEPROM
◇
PART NUMBER
BU9847GUL-W
PART NUMBER
BU9847GUL-W
◇ FEATURES
PACKAGE
VCSP50L1
Two wire serial interface
Wide operating voltage range (1.7V~5.5V)
Endurance : 1,000,000 erase/write cycles
◇ ABSOLUTE MAXIMUM RATING (Ta=25℃)
Parameter
Symbol
Rating
Supply Voltage
Vcc
-0.3~6.5
Power Dissipation
Pd
220 (BU9847GUL-W)
*1
Storage Temperature
Tstg
-65~125
-40~85
Operating Temperature
Topr
-
*2
Terminal Voltage
-0.3~Vcc+1.0
*1 Degradation is done at 2.2mW/℃(*1) for operation above 25℃.
*2 The max value of terminal voltage is not over 6.5V.
◇ RECOMMENDED OPERATING CONDITION
Parameter
Symbol
Rating
Supply Voltage
Vcc
1.7~5.5
Input Voltage
VIN
0~Vcc
Unit
V
V
REV. A
Unit
V
mW
℃
℃
V
2/4
◇ MEMORY CELL CHARACTERISTICS (Ta=25℃, Vcc=1.7~5.5V)
Specification
Unit
Parameter
Min.
Typ.
Max.
Write/Erase Cycle
*1
1,000,000
-
-
Cycles
Data Retention
*1
40
-
-
Years
○Initial Data FFh in all address.
*1 Not 100% TESTED
◇ DC OPERATING CHARACTERISTICS
◇ AC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-40~85℃, Vcc=1.7~5.5V)
(Unless otherwise specified Ta=-40~85℃, Vcc=1.7~5.5V)
FAST-MODE
Specification
1.7V≦Vcc≦5.5V
Parameter
Test Condition
Unit
Symbol
Min.
Typ.
Parameter
Symbol
Max.
Unit
Min.
Typ.
Max.
- Vcc+1.0 V
2.5V≦Vcc≦5.5V
Clock Frequency
fSCL
-
-
400
kHz
V
2.5V≦Vcc≦5.5V
Data Clock High Period
tHIGH
0.6
-
-
μs
- Vcc+1.0 V
1.8V≦Vcc<2.5V
Data Clock Low Period
tLOW
1.2
-
-
μs
V
1.8V≦Vcc<2.5V
SDA and SCL Rise Time
*1
tR
-
-
0.3
μs
- Vcc+1.0 V
1.7V≦Vcc<1.8V
SDA and SCL Fall Time
*1
tF
-
-
0.3
μs
-0.3
-
0.1Vcc
V
1.7V≦Vcc<1.8V
Start Condition Hold Time
tHD:STA
0.6
-
-
μs
-
-
0.4
V
IOL=3.0mA,2.5V≦Vcc≦5.5V(SDA)
Start Condition Setup Time
tSU:STA
0.6
-
-
μs
VOL2
-
-
0.2
V
IOL=0.7mA,1.7V≦Vcc<2.5V(SDA)
Input Data Hold Time
tHD:DAT
0
-
-
ns
Input Leakage Current
ILI
-1
-
1
μA VIN=0V~Vcc
Input Data Setup Time
tSU:DAT
100
-
-
ns
Output Leakage Current
ILO
-1
-
1
μA VOUT=0V~Vcc(SDA)
Output Data Delay Time
tPD
0.1
-
0.9
μs
Vcc=5.5V,fSCL=400kHz,tWR=5ms
0.1
-
-
μs
-
-
2.0
Output Data Hold Time
tDH
ICC1
Byte Write,Page Write
Stop Condition Setup Time
tSU:STO
0.6
-
-
μs
Vcc=5.5V,fSCL=400kHz
Bus Free Time
tBUF
1.2
-
-
μs
Random Read,Current Read,Sequential Read
Write Cycle Time
tWR
-
-
5
ms
Vcc=5.5V,SDA,SCL=Vcc
Noise Spike Width (SDA and SCL)
tI
-
-
0.1
μs
A0,A1,A2=GND,WP=GND
WP Hold Time
tHD:WP
0
-
-
ns
WP Setup Time
tSU:WP
0.1
-
-
μs
WP High Period
tHIGH:WP
1.0
-
-
μs
"H" Input Voltage1
VIH1
0.7Vcc
"L" Input Voltage1
VIL1
-0.3
"H" Input Voltage2
VIH2
0.8Vcc
"L" Input Voltage2
VIL2
-0.3
"H" Input Voltage3
VIH3
0.9Vcc
"L" Input Voltage3
VIL3
"L" Output Voltage1
VOL1
"L" Output Voltage2
-
-
0.3Vcc
0.2Vcc
mA
Operating Current
ICC2
Standby Current
ISB
-
-
-
-
0.5
2.0
mA
μA
○This product is not designed for protection against
○radioactive rays.
*1 Not 100% TESTED
◇ BLOCK DIAGRAM
◇ PIN CONFIGURATION
VCC
GND
4 Kbit
EEPROM
ARRAY
9bit
ADDRESS
DECODER
9bit
SLAVE・WORD
ADDRESS REGISTER
START
A2
B
8bit
DATA
REGISTER
A
WP
B1
○
A1
○
B2
○
A2
○
B3
○
A3
○
1
2
3
STOP
SCL
CONTOROL LOGIC
◇ PIN No., PIN NAME
ACK
HIGH VOLTAGE GEN.
SDA
VCC LEVEL DETECT
Fig.-1 BLOCK DIAGRAM
REV. A
PIN No.
B3
B2
B1
A3
A2
A1
PIN NAME
A2
GND
SDA
VCC
WP
SCL
INDEX POST
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◇ NOTES FOR POWER SUPPLY
Vcc rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device
may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of
P.O.R. and LVCC. In the case of power up, keep the following conditions to ensure functions of P.O.R. and LVCC.
1. It is necessary to be "SDA='H'" and "SCL='L' or 'H'".
2. Follow the recommended conditions of tR, tOFF, Vbot for the function of P.O.R. during power up.
tR
Vcc
tOFF
0
Vbot
◇RECOMMENDED CONDITIONS OF tR, tOFF, Vbot
tR
tOFF
Vbot
Below 10ms
Above 10ms
Below 0.3V
Below 100ms
Above 10ms
Below 0.2V
Fig.-2 Vcc RISING WAVEFORM
3. Prevent SDA and SCL from being "High-Z".
In case that condition 1. and/or 2. cannot be met,
take following actions.
A) Unable to keep condition 1.
Vcc
tLOW
( SDA is "LOW" during power up.)
SCL
→ Control SDA ,SCL to be "HIGH" as Fig.-3(a),
3(b).
SDA
After Vcc becomes stable
B) Unable to keep condition 2.
tDH tSU:DAT
→ After power becomes stable, execute
Fig.-3(a) SCL='H' and SDA='L'
software reset.
C) Unable to keep both conditions 1 and 2.
→ Follow the instruction A first, then the instruction B.
After Vcc becomes stable
tSU:DAT
Fig.-3(b) SCL='L' and SDA='L'
◇CAUTIONS ON USE
(1) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are
exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum
ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such
as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(2) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower
than that of GND terminal.
(3) Thermal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(4) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging
may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source,
terminal and GND owing to foreign matter, LSI may be destructed.
(5) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently.
REV. A
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◇PHYSICAL DIMENSION
Product Name : BU9847GUL-W
9847
LOT NO.
Fig-4 PHYSICAL DIMENSION (VCSP50L1) (Unit:mm)
REV. A
Notice
Notes
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